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[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 128

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET                                                        0
`define EXEU_INITIAL_STATE                                              1
`define EXEU_WAIT_FOR_DECODE                                            2
`define EXEU_FETCH_DECODED_INST                                 3
`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
`define EXEU_WRITE_BACK_TO_RAM                                  5
`define EXEU_HANDLE_JUMP                                                        7
 
 
 
module ExecutionFSM
(
input wire                                                              Clock,
input wire                                                              Reset,
 
input   wire                                                                            iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
//output        reg                                                                     ReadyForNextInstruction,
output wire                                                                     oJumpFlag                       ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
output  wire                                                                    oRAMWriteEnable         ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
output  wire                                                                    oExeLatchedValues,
output  reg                                                                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
output  wire                                                                                                    oTriggerALU,
 
input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
input wire                                                                                                              iALUOutputReady,
input   wire                                                                                                            iBranchTaken,
input wire                                                                                                              iBranchNotTaken,
 
`ifdef DEBUG
        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
        input wire [`MAX_CORES-1:0]         iDebug_CoreID,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
assign oALUChannelX1 = iSource1[95:64];
assign oALUChannelY1 = iSource1[63:32];
assign oALUChannelZ1 = iSource1[31:0];
 
assign oALUChannelX2 = iSource0[95:64];
assign oALUChannelY2 = iSource0[63:32];
assign oALUChannelZ2 = iSource0[31:0];
 
/*
FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[95:64] ),
        .Q( oALUChannelX1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[63:32] ),
        .Q( oALUChannelY1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[31:0] ),
        .Q( oALUChannelZ1 )
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[95:64] ),
        .Q(oALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[63:32] ),
        .Q(oALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[31:0] ),
        .Q(oALUChannelZ1)
);
*/
/*
FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[95:64] ),
        .Q( oALUChannelX2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[63:32] ),
        .Q( oALUChannelY2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[31:0] ),
        .Q( oALUChannelZ2 )
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[95:64] ),
        .Q(oALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[63:32] ),
        .Q(oALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[31:0] ),
        .Q(oALUChannelZ2)
);
*/
//Finally one more latch to store 
//the iOperation and the destination
 
 
assign oALUOperation = iOperation;
//assign oRAMWriteAddress = iDestination;
/*
FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iOperation  ),
        .Q( oALUOperation )
 
);
 
 
FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
(
        .Clock( wLatchNow  ),
        .Clear( Reset ),
        .D( iDestination  ),
        .Q( oRAMWriteAddress )
 
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iOperation ),
        .Q(oALUOperation)
);
*/
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iDestination ),
        .Q(oRAMWriteAddress)
);
 
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
                CurrentState <= `EXEU_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
                  //------------------------------------------
                  `EXEU_AFTER_RESET:
                  begin
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /**
                        At the same time iDecodeDone goes to 1, our Flops
                        will store the value, so next clock cycle we can
                        tell IDU to go ahead and decode the next instruction
                        in the pipeline.
                  */
                  `EXEU_WAIT_FOR_DECODE:
                  begin
 
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                        if ( iDecodeDone )      //This same thing triggers the ALU
                                NextState       <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /*
                  If the instruction is aritmetic then pass the parameters
                  the ALU, else if it store iOperation then...
                  */
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         //*
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      0;               //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
                                        NextState <= `EXEU_WAIT_FOR_DECODE;
                                else
                                        NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                  end
                  //------------------------------------------
                  `EXEU_WRITE_BACK_TO_RAM:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      1;
 
                        if ( iDecodeDone )
                                NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState <= `EXEU_WAIT_FOR_DECODE;
 
                  end
 
                  //------------------------------------------
                  default:
                  begin
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
                                NextState <= `EXEU_AFTER_RESET;
                  end
                  //------------------------------------------
        endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
        $display("Opening ucode dump file....\n");
        ucode_file = $fopen("Code.log","w");
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
        $display("Opening Register lof file...\n");
        reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[95:64] ),
        .Q(wALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[63:32] ),
        .Q(wALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[31:0] ),
        .Q(wALUChannelZ1)
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[95:64] ),
        .Q(wALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[63:32] ),
        .Q(wALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[31:0] ),
        .Q(wALUChannelZ2)
);
 
 
        always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
        begin
                `LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
        end
 
        always @ (negedge  Clock && iDebug_CoreID == `DEBUG_CORE)
        begin
        if ( iALUOutputReady )
        begin
 
 
                if (iBranchTaken)
                        `LOGME"<BT>");
 
                if (iBranchNotTaken     )
                        `LOGME"<BNT>");
 
                if (oRAMWriteEnable)
                        `LOGME"<WE>");
 
                `LOGME "(%dns ",$time);
                                        case ( oALUOperation )
                                        `RETURN: `LOGME"RETURN");
                                        `ADD:   `LOGME"ADD");
                                        `SUB:           `LOGME"SUB");
                                        `DIV:           `LOGME"DIV");
                                        `MUL:   `LOGME"MUL");
                                        `MAG:           `LOGME"MAG");
                                        `JGX:           `LOGME"JGX");
                                        `JLX:           `LOGME"JLX");
                                        `JGEX:  `LOGME"JGEX");
                                        `JGEY:  `LOGME"JGEY");
                                        `JGEZ:  `LOGME"JGEZ");
                                        `JLEX:  `LOGME"JLEX");
                                        `JLEY:  `LOGME"JLEY");
                                        `JLEZ:  `LOGME"JLEZ");
                                        `JMP:           `LOGME"JMP");
                                        `ZERO:  `LOGME"ZERO");
                                        `JNEX:  `LOGME"JNEX");
                                        `JNEY:  `LOGME"JNEY");
                                        `JNEZ:  `LOGME"JNEZ");
                                        `JEQX:  `LOGME"JEQX");
                                        `JEQY:  `LOGME"JEQY");
                                        `JEQZ:  `LOGME"JEQZ");
                                        `CROSS: `LOGME"CROSS");
                                        `DOT:           `LOGME"DOT");
                                        `SETX:  `LOGME"SETX");
                                        `SETY:  `LOGME"SETY");
                                        `SETZ:  `LOGME"SETZ");
                                        `NOP:   `LOGME"NOP");
                                        `COPY:  `LOGME"COPY");
                                        `INC:           `LOGME"INC");
                                        `DEC:           `LOGME"DEC");
                                        `MOD:           `LOGME"MOD");
                                        `FRAC:  `LOGME"FRAC");
                                        `NEG:    `LOGME"NEG");
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
                                        `MULP:          `LOGME"MULP");
                                        `XCHANGEX:      `LOGME"XCHANGEX");
                                        `IMUL:      `LOGME"IMUL");
                                        `UNSCALE:      `LOGME"UNSCALE");
                                        `INCX: `LOGME"INCX");
                                        `INCY: `LOGME"INCY");
                                        `INCZ: `LOGME"INCZ");
                                        `DEBUG_PRINT:
                                        begin
                                                `LOGME"DEBUG_PRINT");
 
                                        end
                                        default:
                                        begin
                                                `LOGME"**********ERROR UNKNOWN OP*********");
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
                                        //      $stop();
                                        end
                                        endcase
 
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
                                        oRAMWriteAddress,
                                        wALUChannelX1,wALUChannelY1,wALUChannelZ1,
                                        wALUChannelX2,wALUChannelY2,wALUChannelZ2
 
                                        );
 
                                        if (oALUOperation == `RETURN)
                                                `LOGME"\n\n\n");
 
                end
        end //always
 
        always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
        begin
        if ( iALUOutputReady )
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
        end //always
`endif
 
endmodule

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Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 128

Line No.	Rev	Author	Line
1	26	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define EXEU_AFTER_RESET 0
23			`define EXEU_INITIAL_STATE 1
24			`define EXEU_WAIT_FOR_DECODE 2
25			`define EXEU_FETCH_DECODED_INST 3
26			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
27			`define EXEU_WRITE_BACK_TO_RAM 5
28			`define EXEU_HANDLE_JUMP 7
29
30
31
32			`module ExecutionFSM`
33			`(`
34			`input wire Clock,`
35			`input wire Reset,`
36
37			`input wire iDecodeDone,`
38			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
39			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
40			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
41			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
42			`//output reg ReadyForNextInstruction,`
43			`output wire oJumpFlag ,`
44			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
45			`output wire oRAMWriteEnable ,`
46			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
47			`output wire oExeLatchedValues,`
48			`output reg oBusy ,`
49
50			`//ALU ports and control signals`
51			output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
52			output wire [`WIDTH-1:0] oALUChannelX1,
53			output wire [`WIDTH-1:0] oALUChannelY1,
54			output wire [`WIDTH-1:0] oALUChannelZ1,
55			output wire [`WIDTH-1:0] oALUChannelX2,
56			output wire [`WIDTH-1:0] oALUChannelY2,
57			output wire [`WIDTH-1:0] oALUChannelZ2,
58			`output wire oTriggerALU,`
59
60			input wire [`WIDTH-1:0] iALUResultX,
61			input wire [`WIDTH-1:0] iALUResultY,
62			input wire [`WIDTH-1:0] iALUResultZ,
63			`input wire iALUOutputReady,`
64			`input wire iBranchTaken,`
65			`input wire iBranchNotTaken,`
66
67			`ifdef DEBUG
68	76	diegovalve	input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
69			input wire [`MAX_CORES-1:0] iDebug_CoreID,
70	26	diegovalve	`endif
71			`//Data forward Signals`
72			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
73
74
75			`);`
76
77			`wire wLatchNow;`
78			`reg rInputLatchesEnabled;`
79
80			`//If ALU says jump, just pass along`
81			`assign oJumpFlag = iBranchTaken;`
82			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
83			`assign oJumpIp = oRAMWriteAddress;`
84
85			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
86			`assign oExeLatchedValues = wLatchNow;`
87			`assign oTriggerALU = wLatchNow;`
88
89			`wire wOperationIsJump;`
90			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
91
92			`//Don't allow me to write back back if the operation is a NOP`
93			`ifdef DEBUG
94			`assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&`
95			(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
96			`else
97			assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
98			`endif
99
100
101			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
102
103	72	diegovalve	`assign oALUChannelX1 = iSource1[95:64];`
104			`assign oALUChannelY1 = iSource1[63:32];`
105			`assign oALUChannelZ1 = iSource1[31:0];`
106
107			`assign oALUChannelX2 = iSource0[95:64];`
108			`assign oALUChannelY2 = iSource0[63:32];`
109			`assign oALUChannelZ2 = iSource0[31:0];`
110
111			`/*`
112	26	diegovalve	`FF32_POSEDGE_SYNCRONOUS_RESET SourceX1`
113			`(`
114			`.Clock( wLatchNow ),`
115			`.Clear( Reset ),`
116			`.D( iSource1[95:64] ),`
117			`.Q( oALUChannelX1 )`
118			`);`
119
120			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY1`
121			`(`
122			`.Clock( wLatchNow ),`
123			`.Clear( Reset ),`
124			`.D( iSource1[63:32] ),`
125			`.Q( oALUChannelY1 )`
126			`);`
127
128			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1`
129			`(`
130			`.Clock( wLatchNow ),`
131			`.Clear( Reset ),`
132			`.D( iSource1[31:0] ),`
133			`.Q( oALUChannelZ1 )`
134			`);`
135	72	diegovalve	`*/`
136			`/*`
137			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
138			`(`
139			`.Clock( Clock ),//wLatchNow ),`
140			`.Reset( Reset),`
141			`.Enable( wLatchNow ),//1'b1 ),`
142			`.D( iSource1[95:64] ),`
143			`.Q(oALUChannelX1)`
144			`);`
145			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
146			`(`
147			`.Clock( Clock ),//wLatchNow ),`
148			`.Reset( Reset),`
149			`.Enable( wLatchNow ),//1'b1 ),`
150			`.D( iSource1[63:32] ),`
151			`.Q(oALUChannelY1)`
152			`);`
153			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
154			`(`
155			`.Clock( Clock ),//wLatchNow ),`
156			`.Reset( Reset),`
157			`.Enable( wLatchNow ),//1'b1 ),`
158			`.D( iSource1[31:0] ),`
159			`.Q(oALUChannelZ1)`
160			`);`
161			`*/`
162			`/*`
163	26	diegovalve	`FF32_POSEDGE_SYNCRONOUS_RESET SourceX2`
164			`(`
165			`.Clock( wLatchNow ),`
166			`.Clear( Reset ),`
167			`.D( iSource0[95:64] ),`
168			`.Q( oALUChannelX2 )`
169			`);`
170
171			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY2`
172			`(`
173			`.Clock( wLatchNow ),`
174			`.Clear( Reset ),`
175			`.D( iSource0[63:32] ),`
176			`.Q( oALUChannelY2 )`
177			`);`
178
179			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2`
180			`(`
181			`.Clock( wLatchNow ),`
182			`.Clear( Reset ),`
183			`.D( iSource0[31:0] ),`
184			`.Q( oALUChannelZ2 )`
185			`);`
186	72	diegovalve	`*/`
187	26	diegovalve	`/*`
188	72	diegovalve	FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
189	26	diegovalve	`(`
190	72	diegovalve	`.Clock( Clock ),//wLatchNow ),`
191			`.Reset( Reset),`
192			`.Enable( wLatchNow ),//1'b1 ),`
193			`.D( iSource0[95:64] ),`
194			`.Q(oALUChannelX2)`
195	26	diegovalve	`);`
196	72	diegovalve	FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
197			`(`
198			`.Clock( Clock ),//wLatchNow ),`
199			`.Reset( Reset),`
200			`.Enable( wLatchNow ),//1'b1 ),`
201			`.D( iSource0[63:32] ),`
202			`.Q(oALUChannelY2)`
203			`);`
204			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
205			`(`
206			`.Clock( Clock ),//wLatchNow ),`
207			`.Reset( Reset),`
208			`.Enable( wLatchNow ),//1'b1 ),`
209			`.D( iSource0[31:0] ),`
210			`.Q(oALUChannelZ2)`
211			`);`
212	26	diegovalve	`*/`
213	72	diegovalve	`//Finally one more latch to store`
214			`//the iOperation and the destination`
215	26	diegovalve
216	72	diegovalve
217			`assign oALUOperation = iOperation;`
218			`//assign oRAMWriteAddress = iDestination;`
219			`/*`
220	26	diegovalve	`FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation`
221			`(`
222			`.Clock( wLatchNow ),`
223			`.Clear( Reset ),`
224			`.D( iOperation ),`
225			`.Q( oALUOperation )`
226
227			`);`
228
229
230			`FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination`
231			`(`
232			`.Clock( wLatchNow ),`
233			`.Clear( Reset ),`
234			`.D( iDestination ),`
235			`.Q( oRAMWriteAddress )`
236
237			`);`
238	72	diegovalve	`*/`
239			`/*`
240			FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
241			`(`
242			`.Clock( Clock ),//wLatchNow ),`
243			`.Reset( Reset),`
244			`.Enable( wLatchNow ),//1'b1 ),`
245			`.D( iOperation ),`
246			`.Q(oALUOperation)`
247			`);`
248			`*/`
249			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
250			`(`
251			`.Clock( Clock ),//wLatchNow ),`
252			`.Reset( Reset),`
253			`.Enable( wLatchNow ),//1'b1 ),`
254			`.D( iDestination ),`
255			`.Q(oRAMWriteAddress)`
256			`);`
257
258	26	diegovalve	`//Data forwarding`
259			`assign oLastDestination = oRAMWriteAddress;`
260
261			`reg [7:0] CurrentState;`
262			`reg [7:0] NextState;`
263
264
265			`//------------------------------------------------`
266			`always @(posedge Clock or posedge Reset)`
267			`begin`
268
269
270
271			`if (Reset)`
272			CurrentState <= `EXEU_AFTER_RESET;
273			`else`
274			`CurrentState <= NextState;`
275
276			`end`
277			`//------------------------------------------------`
278
279
280			`always @( * )`
281			`begin`
282			`case (CurrentState)`
283			`//------------------------------------------`
284			`EXEU_AFTER_RESET:
285			`begin`
286			`//ReadyForNextInstruction <= 1;`
287			`oBusy <= 0;`
288			`rInputLatchesEnabled <= 1;`
289
290
291			NextState <= `EXEU_WAIT_FOR_DECODE;
292			`end`
293			`//------------------------------------------`
294			`/**`
295			`At the same time iDecodeDone goes to 1, our Flops`
296			`will store the value, so next clock cycle we can`
297			`tell IDU to go ahead and decode the next instruction`
298			`in the pipeline.`
299			`*/`
300			`EXEU_WAIT_FOR_DECODE:
301			`begin`
302
303
304			`//ReadyForNextInstruction <= 1;`
305			`oBusy <= 0;`
306			`rInputLatchesEnabled <= 1;`
307
308
309			`if ( iDecodeDone ) //This same thing triggers the ALU`
310			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
311			`else`
312			NextState <= `EXEU_WAIT_FOR_DECODE;
313			`end`
314			`//------------------------------------------`
315			`/*`
316			`If the instruction is aritmetic then pass the parameters`
317			`the ALU, else if it store iOperation then...`
318			`*/`
319			`EXEU_WAIT_FOR_ALU_EXECUTION:
320			`begin`
321
322			`//ReadyForNextInstruction <= 0; //*`
323			`oBusy <= 1;`
324			`rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
325
326
327
328			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
329			NextState <= `EXEU_WAIT_FOR_DECODE;
330			`else`
331			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
332			`end`
333			`//------------------------------------------`
334			`EXEU_WRITE_BACK_TO_RAM:
335			`begin`
336
337			`//ReadyForNextInstruction <= 0;`
338			`oBusy <= 1;`
339			`rInputLatchesEnabled <= 1;`
340
341			`if ( iDecodeDone )`
342			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
343			`else`
344			NextState <= `EXEU_WAIT_FOR_DECODE;
345
346			`end`
347
348			`//------------------------------------------`
349			`default:`
350			`begin`
351
352			`//ReadyForNextInstruction <= 1;`
353			`oBusy <= 0;`
354			`rInputLatchesEnabled <= 1;`
355
356			NextState <= `EXEU_AFTER_RESET;
357			`end`
358			`//------------------------------------------`
359			`endcase`
360			`end`
361
362			`//-----------------------------------------------------------------------`
363			`ifdef DUMP_CODE
364			`integer ucode_file;`
365			`integer reg_log;`
366			`initial`
367			`begin`
368
369			`$display("Opening ucode dump file....\n");`
370			`ucode_file = $fopen("Code.log","w");`
371			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
372			`$display("Opening Register lof file...\n");`
373			`reg_log = $fopen("Registers.log","w");`
374
375			`end`
376
377			`endif //Ucode dump
378
379			`//-----------------------------------------------------------------------`
380			`ifdef DEBUG
381	72	diegovalve	wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
382			wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
383
384			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
385			`(`
386			`.Clock( Clock ),`
387			`.Reset( Reset),`
388			`.Enable( wLatchNow ),`
389			`.D( iSource1[95:64] ),`
390			`.Q(wALUChannelX1)`
391			`);`
392			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
393			`(`
394			`.Clock( Clock ),`
395			`.Reset( Reset),`
396			`.Enable( wLatchNow ),`
397			`.D( iSource1[63:32] ),`
398			`.Q(wALUChannelY1)`
399			`);`
400			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
401			`(`
402			`.Clock( Clock ),`
403			`.Reset( Reset),`
404			`.Enable( wLatchNow ),`
405			`.D( iSource1[31:0] ),`
406			`.Q(wALUChannelZ1)`
407			`);`
408
409
410			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
411			`(`
412			`.Clock( Clock ),`
413			`.Reset( Reset),`
414			`.Enable( wLatchNow ),`
415			`.D( iSource0[95:64] ),`
416			`.Q(wALUChannelX2)`
417			`);`
418			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
419			`(`
420			`.Clock( Clock ),`
421			`.Reset( Reset),`
422			`.Enable( wLatchNow ),`
423			`.D( iSource0[63:32] ),`
424			`.Q(wALUChannelY2)`
425			`);`
426			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
427			`(`
428			`.Clock( Clock ),`
429			`.Reset( Reset),`
430			`.Enable( wLatchNow ),`
431			`.D( iSource0[31:0] ),`
432			`.Q(wALUChannelZ2)`
433			`);`
434
435
436	82	diegovalve	always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
437	26	diegovalve	`begin`
438	76	diegovalve	`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
439	26	diegovalve	`end`
440
441	82	diegovalve	always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
442	26	diegovalve	`begin`
443			`if ( iALUOutputReady )`
444			`begin`
445
446
447			`if (iBranchTaken)`
448			`LOGME"<BT>");
449
450			`if (iBranchNotTaken )`
451			`LOGME"<BNT>");
452
453			`if (oRAMWriteEnable)`
454			`LOGME"<WE>");
455
456			`LOGME "(%dns ",$time);
457			`case ( oALUOperation )`
458			`RETURN: `LOGME"RETURN");
459			`ADD: `LOGME"ADD");
460			`SUB: `LOGME"SUB");
461			`DIV: `LOGME"DIV");
462			`MUL: `LOGME"MUL");
463			`MAG: `LOGME"MAG");
464	63	diegovalve	`JGX: `LOGME"JGX");
465			`JLX: `LOGME"JLX");
466	26	diegovalve	`JGEX: `LOGME"JGEX");
467			`JGEY: `LOGME"JGEY");
468			`JGEZ: `LOGME"JGEZ");
469			`JLEX: `LOGME"JLEX");
470			`JLEY: `LOGME"JLEY");
471			`JLEZ: `LOGME"JLEZ");
472			`JMP: `LOGME"JMP");
473			`ZERO: `LOGME"ZERO");
474			`JNEX: `LOGME"JNEX");
475			`JNEY: `LOGME"JNEY");
476			`JNEZ: `LOGME"JNEZ");
477			`JEQX: `LOGME"JEQX");
478			`JEQY: `LOGME"JEQY");
479			`JEQZ: `LOGME"JEQZ");
480			`CROSS: `LOGME"CROSS");
481			`DOT: `LOGME"DOT");
482			`SETX: `LOGME"SETX");
483			`SETY: `LOGME"SETY");
484			`SETZ: `LOGME"SETZ");
485			`NOP: `LOGME"NOP");
486			`COPY: `LOGME"COPY");
487			`INC: `LOGME"INC");
488			`DEC: `LOGME"DEC");
489			`MOD: `LOGME"MOD");
490			`FRAC: `LOGME"FRAC");
491			`NEG: `LOGME"NEG");
492			`SWIZZLE3D: `LOGME"SWIZZLE3D");
493			`MULP: `LOGME"MULP");
494			`XCHANGEX: `LOGME"XCHANGEX");
495			`IMUL: `LOGME"IMUL");
496			`UNSCALE: `LOGME"UNSCALE");
497			`INCX: `LOGME"INCX");
498			`INCY: `LOGME"INCY");
499			`INCZ: `LOGME"INCZ");
500			`DEBUG_PRINT:
501			`begin`
502			`LOGME"DEBUG_PRINT");
503
504			`end`
505			`default:`
506			`begin`
507			`LOGME"********ERROR UNKNOWN OP*******");
508			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
509			`// $stop();`
510			`end`
511			`endcase`
512
513			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
514			`oRAMWriteAddress,`
515	72	diegovalve	`wALUChannelX1,wALUChannelY1,wALUChannelZ1,`
516			`wALUChannelX2,wALUChannelY2,wALUChannelZ2`
517	26	diegovalve
518			`);`
519
520			if (oALUOperation == `RETURN)
521			`LOGME"\n\n\n");
522
523			`end`
524			`end //always`
525
526	82	diegovalve	always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
527	26	diegovalve	`begin`
528			`if ( iALUOutputReady )`
529			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
530			`end //always`
531			`endif
532
533			`endmodule`