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[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [GEO/] [Module_TreeNodeFetcher.v] - Blame information for rev 87

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define TNF_AFTER_RESET                                 0
`define TNF_IDLE                                                        1
`define TNF_REQUEST_AABBMIN                     2
`define TNF_WAIT_FOR_AABBMIN                    3
`define TNF_REQUEST_AABBMAX                     4
`define TNF_WAIT_FOR_AABBMAX                    5
 
`define TNF_REQUEST_NUMBER_OF_TRIANGLES 10
`define TNF_WAIT_FOR_NUMBER_OF_TRIANGLES 11
`define TNF_LATCH_NUMBER_OF_TRIANGLES    12
`define TNF_WAIT_NODE_READ_ACK                   13
`define TNF_REQUEST_DATA_OFFSET                  14
`define TNF_WAIT_FOR_DATA_OFFSET                         15
`define TNF_LATCH_DATA_OFFSET                            16
`define TNF_REQUEST_NODE_BROTHER_ADDRESS        17
`define TNF_WAIT_FOR_NODE_BROTHER_ADDRESS 18
`define TNF_LACTH_NODE_BROTHER_ADDRESS          19
`define TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS 20
`define TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS            21
`define TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS   22
`define TNF_RAM_WRITE_DELAY1                                                    23
`define TNF_INC1        24
`define TNF_INC2        25
`define TNF_INC3        26
 
/*
 
        To fetch node, we need to ask WBM to perform several read cycles.
        Each read cycle reads 32 bits. The first 6 read cycles requests
        consecutive addresses that represent AABBMAX and AABBMIN corners.
        These 6 values must be stored into RAM for the ucode to use.
        Next value represents the number of vertices this AABB has, or
        zero is is not a LEAF.
        Next value is the offset where of the vertex data.
*/
 
module TreeNodeFetcher
(
        input wire                                      Clock,
        input wire                                      Reset,
        input   wire[`WIDTH-1:0] iData,
        input   wire                                    iDataAvailable,
        input   wire                                    iTrigger,
        input wire[`WIDTH-1:0]   iInitialAddress,
 
        //wires that go into WBM
        output reg                                              oSetAddressWBM,
        output reg                                              oEnableWBM,
        output wire[`WIDTH-1:0]          oAddressWBM,
        //The parsed node info
        output wire                                             oNode_IsLeaf,
        output wire[`WIDTH-1:0]          oNode_DataOffset,
        output wire     [`WIDTH-1:0]     oNode_TriangleCount,    //Change to 16 bits
        //output wire [`WIDTH-1:0]      oNode_ChildCount,               //Change to 16 bits
 
        output wire [`WIDTH-1:0] oNode_Brother_Address,                  //*
        output wire [`WIDTH-1:0] oParents_Brother_Address,               //*
        //output reg [`WIDTH-1:0]               oNode_FirstChild_Address,
 
        output reg                                              oNodeReadDone,
        output reg                                              oRAMWriteEnable,
 
        `ifdef DEBUG
        input wire[`MAX_CORES-1:0]            iDebug_CoreID,
        `endif
 
        output  reg [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress
);
 
reg [4:0]                        CurrentState;
reg [4:0]                        NextState;
 
 
assign oAddressWBM = iInitialAddress;
 
reg rFFEnNumVertices;
 
//Flip Flop D
//FFD_SYNCH_RST_GENERIC FFD32_TNF
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnNumVertices ),
        .D( iData ),
        .Q( oNode_TriangleCount )
 
);
 
 
reg rFFEnBrotherAddress;
//Flip Flop D
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC
//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnBrotherAddress ),
        .D( iData ),
        .Q( oNode_Brother_Address )
 
);
 
reg rFFEnParentsBroAddr;
//Flip Flop D
FFD_POSEDGE_SYNCRONOUS_RESET  # (`WIDTH) FFD32_TNF_NC2
//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC2
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnParentsBroAddr ),
        .D( iData ),
        .Q( oParents_Brother_Address )
 
);
 
 
reg rFFEnDataOffset;
//Flip Flop D
FFD_POSEDGE_SYNCRONOUS_RESET  # (`WIDTH) FFD32_TNF2
//FFD_SYNCH_RST_GENERIC FFD32_TNF2
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnDataOffset ),
        .D( iData ),
        .Q( oNode_DataOffset )
 
);
 
 
assign oNode_IsLeaf = (oNode_TriangleCount != 32'h0);
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
    if (Reset)
                CurrentState <= `TNF_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
 
//------------------------------------
/*
        IDLE State just waiting for something
        to do...
*/
 
always @( * )
   begin
   case (CurrentState)
        //------------------------------------
        `TNF_AFTER_RESET:
        begin
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                oRAMWriteEnable <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_IDLE;
        end
        //------------------------------------
        `TNF_IDLE:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                oRAMWriteEnable <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
           if (iTrigger)
                        NextState <= `TNF_REQUEST_AABBMIN;
                else
                        NextState <= `TNF_IDLE;
 
        end
        //------------------------------------
        /*
        Here tell WBM to read from address iInitialAddress by seeting
        oSetAddressWBM = 1.
        By setting oRAMWriteEnable = 1, we are also telling WBM to
        store the the value in iInitialAddress, iInitialAddress+1,
        and iInitialAddress+2 into RAM, so the WBMAddress is going
        to increment by 3.
        */
        `TNF_REQUEST_AABBMIN:
        begin
                `ifdef DEBUG_GFSM
                if (iDebug_CoreID == `DEBUG_CORE)
                        $display("CORE %d TNF_REQUEST_AABBMIN",iDebug_CoreID);
                `endif
 
                oRAMWriteAddress        <= `CREG_AABBMIN;
                oEnableWBM      <= 1; //*
                oSetAddressWBM          <= 1; //*
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1; //*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_AABBMIN;
 
        end
        //------------------------------------
        `TNF_WAIT_FOR_AABBMIN:
        begin
                oRAMWriteAddress        <= `CREG_AABBMIN;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1;//*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_REQUEST_AABBMAX;
                else
                        NextState <= `TNF_WAIT_FOR_AABBMIN;
        end
        //------------------------------------
        `TNF_REQUEST_AABBMAX:
        begin
        `ifdef DEBUG_GFSM
                if (iDebug_CoreID == `DEBUG_CORE)
                        $display("CORE %d TNF_REQUEST_AABBMAX",iDebug_CoreID);
        `endif
                oRAMWriteAddress        <= `CREG_AABBMAX;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1;//*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_AABBMAX;
        end
        //------------------------------------
        `TNF_WAIT_FOR_AABBMAX:
        begin
                oRAMWriteAddress        <= `CREG_AABBMAX;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1;//*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_REQUEST_NUMBER_OF_TRIANGLES;
                else
                        NextState <= `TNF_WAIT_FOR_AABBMAX;
        end
        //------------------------------------
        `TNF_REQUEST_NUMBER_OF_TRIANGLES:
        begin
        `ifdef DEBUG_GFSM
                if (iDebug_CoreID == `DEBUG_CORE)
                        $display("CORE %d TNF_REQUEST_NUMBER_OF_TRIANGLES",iDebug_CoreID);
        `endif
                oRAMWriteAddress        <= `CREG_AABBMAX;
                oEnableWBM      <= 1; //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0; //* to give more time to write
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
        end
        //------------------------------------
        `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
                oRAMWriteEnable    <= 0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LATCH_NUMBER_OF_TRIANGLES;
                else
                        NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
 
        end
        //------------------------------------
        `TNF_LATCH_NUMBER_OF_TRIANGLES:
        begin
                `ifdef DEBUG_GFSM
                if (iDebug_CoreID == `DEBUG_CORE)
                        $display("CORE %d TNF_LATCH_NUMBER_OF_TRIANGLES",iDebug_CoreID);
                `endif
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;    //* 
                rFFEnNumVertices        <= 1;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
                oRAMWriteEnable         <= 0;
 
                NextState <= `TNF_REQUEST_DATA_OFFSET;
        end
        //------------------------------------
        `TNF_REQUEST_DATA_OFFSET:
        begin
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1; //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
        end
        //------------------------------------
        `TNF_WAIT_FOR_DATA_OFFSET:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1; //* 
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LATCH_DATA_OFFSET;
                else
                        NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
 
        end
        //------------------------------------
        `TNF_LATCH_DATA_OFFSET:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 1; //*
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_REQUEST_NODE_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_REQUEST_NODE_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;   //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 1;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;   //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LACTH_NODE_BROTHER_ADDRESS;
                else
                        NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_LACTH_NODE_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 1;   //*
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS:
        begin
                `ifdef DEBUG_GFSM
                if (iDebug_CoreID == `DEBUG_CORE)
                        $display("CORE %d TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS",iDebug_CoreID);
                `endif
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;   //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
                //rLastAddress                                          <= 1;
 
                NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS;
                else
                        NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      1;
 
                NextState <= `TNF_WAIT_NODE_READ_ACK;
 
        end
        //------------------------------------
        `TNF_WAIT_NODE_READ_ACK:
        begin
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 1;   //*
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if (    iTrigger == 0 )
                        NextState <= `TNF_IDLE;
                else
                        NextState <= `TNF_WAIT_NODE_READ_ACK;
        end
        //------------------------------------
        default:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_IDLE;
        end
        //------------------------------------
        endcase
end //always    
endmodule

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Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [GEO/] [Module_TreeNodeFetcher.v] - Blame information for rev 87

Line No.	Rev	Author	Line
1	29	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define TNF_AFTER_RESET 0
23			`define TNF_IDLE 1
24			`define TNF_REQUEST_AABBMIN 2
25			`define TNF_WAIT_FOR_AABBMIN 3
26			`define TNF_REQUEST_AABBMAX 4
27			`define TNF_WAIT_FOR_AABBMAX 5
28
29			`define TNF_REQUEST_NUMBER_OF_TRIANGLES 10
30			`define TNF_WAIT_FOR_NUMBER_OF_TRIANGLES 11
31			`define TNF_LATCH_NUMBER_OF_TRIANGLES 12
32			`define TNF_WAIT_NODE_READ_ACK 13
33			`define TNF_REQUEST_DATA_OFFSET 14
34			`define TNF_WAIT_FOR_DATA_OFFSET 15
35			`define TNF_LATCH_DATA_OFFSET 16
36			`define TNF_REQUEST_NODE_BROTHER_ADDRESS 17
37			`define TNF_WAIT_FOR_NODE_BROTHER_ADDRESS 18
38			`define TNF_LACTH_NODE_BROTHER_ADDRESS 19
39			`define TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS 20
40			`define TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS 21
41			`define TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS 22
42			`define TNF_RAM_WRITE_DELAY1 23
43			`define TNF_INC1 24
44			`define TNF_INC2 25
45			`define TNF_INC3 26
46
47			`/*`
48
49			`To fetch node, we need to ask WBM to perform several read cycles.`
50			`Each read cycle reads 32 bits. The first 6 read cycles requests`
51			`consecutive addresses that represent AABBMAX and AABBMIN corners.`
52			`These 6 values must be stored into RAM for the ucode to use.`
53			`Next value represents the number of vertices this AABB has, or`
54			`zero is is not a LEAF.`
55			`Next value is the offset where of the vertex data.`
56			`*/`
57
58			`module TreeNodeFetcher`
59			`(`
60			`input wire Clock,`
61			`input wire Reset,`
62			input wire[`WIDTH-1:0] iData,
63			`input wire iDataAvailable,`
64			`input wire iTrigger,`
65			input wire[`WIDTH-1:0] iInitialAddress,
66
67			`//wires that go into WBM`
68			`output reg oSetAddressWBM,`
69			`output reg oEnableWBM,`
70			output wire[`WIDTH-1:0] oAddressWBM,
71			`//The parsed node info`
72			`output wire oNode_IsLeaf,`
73			output wire[`WIDTH-1:0] oNode_DataOffset,
74			output wire [`WIDTH-1:0] oNode_TriangleCount, //Change to 16 bits
75			//output wire [`WIDTH-1:0] oNode_ChildCount, //Change to 16 bits
76
77			output wire [`WIDTH-1:0] oNode_Brother_Address, //*
78			output wire [`WIDTH-1:0] oParents_Brother_Address, //*
79			//output reg [`WIDTH-1:0] oNode_FirstChild_Address,
80
81			`output reg oNodeReadDone,`
82	82	diegovalve	`output reg oRAMWriteEnable,`
83
84			`ifdef DEBUG
85			input wire[`MAX_CORES-1:0] iDebug_CoreID,
86			`endif
87	29	diegovalve
88			output reg [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress
89			`);`
90
91			`reg [4:0] CurrentState;`
92			`reg [4:0] NextState;`
93
94
95			`assign oAddressWBM = iInitialAddress;`
96
97			`reg rFFEnNumVertices;`
98
99			`//Flip Flop D`
100			`//FFD_SYNCH_RST_GENERIC FFD32_TNF`
101			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF
102			`(`
103			`.Clock( Clock ),`
104			`.Reset( Reset ),`
105			`.Enable( rFFEnNumVertices ),`
106			`.D( iData ),`
107			`.Q( oNode_TriangleCount )`
108
109			`);`
110
111
112			`reg rFFEnBrotherAddress;`
113			`//Flip Flop D`
114			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC
115			`//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC`
116			`(`
117			`.Clock( Clock ),`
118			`.Reset( Reset ),`
119			`.Enable( rFFEnBrotherAddress ),`
120			`.D( iData ),`
121			`.Q( oNode_Brother_Address )`
122
123			`);`
124
125			`reg rFFEnParentsBroAddr;`
126			`//Flip Flop D`
127			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC2
128			`//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC2`
129			`(`
130			`.Clock( Clock ),`
131			`.Reset( Reset ),`
132			`.Enable( rFFEnParentsBroAddr ),`
133			`.D( iData ),`
134			`.Q( oParents_Brother_Address )`
135
136			`);`
137
138
139			`reg rFFEnDataOffset;`
140			`//Flip Flop D`
141			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF2
142			`//FFD_SYNCH_RST_GENERIC FFD32_TNF2`
143			`(`
144			`.Clock( Clock ),`
145			`.Reset( Reset ),`
146			`.Enable( rFFEnDataOffset ),`
147			`.D( iData ),`
148			`.Q( oNode_DataOffset )`
149
150			`);`
151
152
153			`assign oNode_IsLeaf = (oNode_TriangleCount != 32'h0);`
154
155			`//------------------------------------------------`
156			`always @(posedge Clock or posedge Reset)`
157			`begin`
158
159			`if (Reset)`
160			CurrentState <= `TNF_AFTER_RESET;
161			`else`
162			`CurrentState <= NextState;`
163
164			`end`
165
166			`//------------------------------------`
167			`/*`
168			`IDLE State just waiting for something`
169			`to do...`
170			`*/`
171
172			`always @( * )`
173			`begin`
174			`case (CurrentState)`
175			`//------------------------------------`
176			`TNF_AFTER_RESET:
177			`begin`
178
179			`oRAMWriteAddress <= 0;`
180			`oEnableWBM <= 0;`
181			`oSetAddressWBM <= 0;`
182			`oNodeReadDone <= 0;`
183			`oRAMWriteEnable <= 0;`
184			`rFFEnNumVertices <= 0;`
185			`rFFEnDataOffset <= 0;`
186			`rFFEnBrotherAddress <= 0;`
187			`rFFEnParentsBroAddr <= 0;`
188
189			NextState <= `TNF_IDLE;
190			`end`
191			`//------------------------------------`
192			`TNF_IDLE:
193			`begin`
194			`oRAMWriteAddress <= 0;`
195			`oEnableWBM <= 0;`
196			`oSetAddressWBM <= 0;`
197			`oNodeReadDone <= 0;`
198			`oRAMWriteEnable <= 0;`
199			`rFFEnNumVertices <= 0;`
200			`rFFEnDataOffset <= 0;`
201			`rFFEnBrotherAddress <= 0;`
202			`rFFEnParentsBroAddr <= 0;`
203
204			`if (iTrigger)`
205			NextState <= `TNF_REQUEST_AABBMIN;
206			`else`
207			NextState <= `TNF_IDLE;
208
209			`end`
210			`//------------------------------------`
211			`/*`
212			`Here tell WBM to read from address iInitialAddress by seeting`
213			`oSetAddressWBM = 1.`
214			`By setting oRAMWriteEnable = 1, we are also telling WBM to`
215			`store the the value in iInitialAddress, iInitialAddress+1,`
216			`and iInitialAddress+2 into RAM, so the WBMAddress is going`
217			`to increment by 3.`
218			`*/`
219			`TNF_REQUEST_AABBMIN:
220	82	diegovalve	`begin`
221			`ifdef DEBUG_GFSM
222			if (iDebug_CoreID == `DEBUG_CORE)
223			`$display("CORE %d TNF_REQUEST_AABBMIN",iDebug_CoreID);`
224			`endif
225
226	29	diegovalve	oRAMWriteAddress <= `CREG_AABBMIN;
227			`oEnableWBM <= 1; //*`
228			`oSetAddressWBM <= 1; //*`
229			`oNodeReadDone <= 0;`
230			`rFFEnNumVertices <= 0;`
231			`rFFEnDataOffset <= 0;`
232			`oRAMWriteEnable <= 1; //*`
233			`rFFEnBrotherAddress <= 0;`
234			`rFFEnParentsBroAddr <= 0;`
235
236			NextState <= `TNF_WAIT_FOR_AABBMIN;
237
238			`end`
239			`//------------------------------------`
240			`TNF_WAIT_FOR_AABBMIN:
241			`begin`
242			oRAMWriteAddress <= `CREG_AABBMIN;
243			`oEnableWBM <= 1;`
244			`oSetAddressWBM <= 0;`
245			`oNodeReadDone <= 0;`
246			`rFFEnNumVertices <= 0;`
247			`rFFEnDataOffset <= 0;`
248			`oRAMWriteEnable <= 1;//*`
249			`rFFEnBrotherAddress <= 0;`
250			`rFFEnParentsBroAddr <= 0;`
251
252			`if ( iDataAvailable )`
253			NextState <= `TNF_REQUEST_AABBMAX;
254			`else`
255			NextState <= `TNF_WAIT_FOR_AABBMIN;
256			`end`
257			`//------------------------------------`
258			`TNF_REQUEST_AABBMAX:
259	82	diegovalve	`begin`
260			`ifdef DEBUG_GFSM
261			if (iDebug_CoreID == `DEBUG_CORE)
262			`$display("CORE %d TNF_REQUEST_AABBMAX",iDebug_CoreID);`
263			`endif
264	29	diegovalve	oRAMWriteAddress <= `CREG_AABBMAX;
265			`oEnableWBM <= 1;`
266			`oSetAddressWBM <= 0;`
267			`oNodeReadDone <= 0;`
268			`rFFEnNumVertices <= 0;`
269			`rFFEnDataOffset <= 0;`
270			`oRAMWriteEnable <= 1;//*`
271			`rFFEnBrotherAddress <= 0;`
272			`rFFEnParentsBroAddr <= 0;`
273
274			NextState <= `TNF_WAIT_FOR_AABBMAX;
275			`end`
276			`//------------------------------------`
277			`TNF_WAIT_FOR_AABBMAX:
278			`begin`
279			oRAMWriteAddress <= `CREG_AABBMAX;
280			`oEnableWBM <= 1;`
281			`oSetAddressWBM <= 0;`
282			`oNodeReadDone <= 0;`
283			`rFFEnNumVertices <= 0;`
284			`rFFEnDataOffset <= 0;`
285			`oRAMWriteEnable <= 1;//*`
286			`rFFEnBrotherAddress <= 0;`
287			`rFFEnParentsBroAddr <= 0;`
288
289			`if ( iDataAvailable )`
290			NextState <= `TNF_REQUEST_NUMBER_OF_TRIANGLES;
291			`else`
292			NextState <= `TNF_WAIT_FOR_AABBMAX;
293			`end`
294			`//------------------------------------`
295			`TNF_REQUEST_NUMBER_OF_TRIANGLES:
296	82	diegovalve	`begin`
297			`ifdef DEBUG_GFSM
298			if (iDebug_CoreID == `DEBUG_CORE)
299			`$display("CORE %d TNF_REQUEST_NUMBER_OF_TRIANGLES",iDebug_CoreID);`
300			`endif
301	29	diegovalve	oRAMWriteAddress <= `CREG_AABBMAX;
302			`oEnableWBM <= 1; //*`
303			`oSetAddressWBM <= 0;`
304			`oNodeReadDone <= 0;`
305			`rFFEnNumVertices <= 0;`
306			`rFFEnDataOffset <= 0;`
307			`oRAMWriteEnable <= 0; //* to give more time to write`
308			`rFFEnBrotherAddress <= 0;`
309			`rFFEnParentsBroAddr <= 0;`
310
311			NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
312			`end`
313			`//------------------------------------`
314			`TNF_WAIT_FOR_NUMBER_OF_TRIANGLES:
315			`begin`
316			`oRAMWriteAddress <= 0;`
317			`oEnableWBM <= 1;`
318			`oSetAddressWBM <= 0;`
319			`oNodeReadDone <= 0;`
320			`rFFEnNumVertices <= 0;`
321			`rFFEnDataOffset <= 0;`
322			`rFFEnBrotherAddress <= 0;`
323			`rFFEnParentsBroAddr <= 0;`
324			`oRAMWriteEnable <= 0;`
325
326			`if ( iDataAvailable )`
327			NextState <= `TNF_LATCH_NUMBER_OF_TRIANGLES;
328			`else`
329			NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
330
331			`end`
332			`//------------------------------------`
333			`TNF_LATCH_NUMBER_OF_TRIANGLES:
334			`begin`
335	82	diegovalve	`ifdef DEBUG_GFSM
336			if (iDebug_CoreID == `DEBUG_CORE)
337			`$display("CORE %d TNF_LATCH_NUMBER_OF_TRIANGLES",iDebug_CoreID);`
338			`endif
339	29	diegovalve	`oRAMWriteAddress <= 0;`
340			`oEnableWBM <= 0;`
341			`oSetAddressWBM <= 0;`
342			`oNodeReadDone <= 0; //*`
343			`rFFEnNumVertices <= 1;`
344			`rFFEnDataOffset <= 0;`
345			`rFFEnBrotherAddress <= 0;`
346			`rFFEnParentsBroAddr <= 0;`
347			`oRAMWriteEnable <= 0;`
348
349			NextState <= `TNF_REQUEST_DATA_OFFSET;
350			`end`
351			`//------------------------------------`
352			`TNF_REQUEST_DATA_OFFSET:
353	82	diegovalve	`begin`
354
355	29	diegovalve	`oRAMWriteAddress <= 0;`
356			`oEnableWBM <= 1; //*`
357			`oSetAddressWBM <= 0;`
358			`oNodeReadDone <= 0;`
359			`rFFEnNumVertices <= 0;`
360			`rFFEnDataOffset <= 0;`
361			`oRAMWriteEnable <= 0;`
362			`rFFEnBrotherAddress <= 0;`
363			`rFFEnParentsBroAddr <= 0;`
364
365			NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
366			`end`
367			`//------------------------------------`
368			`TNF_WAIT_FOR_DATA_OFFSET:
369			`begin`
370			`oRAMWriteAddress <= 0;`
371			`oEnableWBM <= 1; //*`
372			`oSetAddressWBM <= 0;`
373			`oNodeReadDone <= 0;`
374			`rFFEnNumVertices <= 0;`
375			`rFFEnDataOffset <= 0;`
376			`oRAMWriteEnable <= 0;`
377			`rFFEnBrotherAddress <= 0;`
378			`rFFEnParentsBroAddr <= 0;`
379
380			`if ( iDataAvailable )`
381			NextState <= `TNF_LATCH_DATA_OFFSET;
382			`else`
383			NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
384
385			`end`
386			`//------------------------------------`
387			`TNF_LATCH_DATA_OFFSET:
388			`begin`
389			`oRAMWriteAddress <= 0;`
390			`oEnableWBM <= 0;`
391			`oSetAddressWBM <= 0;`
392			`oNodeReadDone <= 0;`
393			`rFFEnNumVertices <= 0;`
394			`rFFEnDataOffset <= 1; //*`
395			`oRAMWriteEnable <= 0;`
396			`rFFEnBrotherAddress <= 0;`
397			`rFFEnParentsBroAddr <= 0;`
398
399			NextState <= `TNF_REQUEST_NODE_BROTHER_ADDRESS;
400			`end`
401			`//------------------------------------`
402			`TNF_REQUEST_NODE_BROTHER_ADDRESS:
403			`begin`
404			`oRAMWriteAddress <= 0;`
405			`oEnableWBM <= 1; //*`
406			`oSetAddressWBM <= 0;`
407			`oNodeReadDone <= 0;`
408			`rFFEnNumVertices <= 0;`
409			`rFFEnDataOffset <= 1;`
410			`oRAMWriteEnable <= 0;`
411			`rFFEnBrotherAddress <= 0;`
412			`rFFEnParentsBroAddr <= 0;`
413
414			NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
415			`end`
416			`//------------------------------------`
417			`TNF_WAIT_FOR_NODE_BROTHER_ADDRESS:
418			`begin`
419			`oRAMWriteAddress <= 0;`
420			`oEnableWBM <= 1; //*`
421			`oSetAddressWBM <= 0;`
422			`oNodeReadDone <= 0;`
423			`rFFEnNumVertices <= 0;`
424			`rFFEnDataOffset <= 0;`
425			`oRAMWriteEnable <= 0;`
426			`rFFEnBrotherAddress <= 0;`
427			`rFFEnParentsBroAddr <= 0;`
428
429			`if ( iDataAvailable )`
430			NextState <= `TNF_LACTH_NODE_BROTHER_ADDRESS;
431			`else`
432			NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
433			`end`
434			`//------------------------------------`
435			`TNF_LACTH_NODE_BROTHER_ADDRESS:
436			`begin`
437			`oRAMWriteAddress <= 0;`
438			`oEnableWBM <= 0;`
439			`oSetAddressWBM <= 0;`
440			`oNodeReadDone <= 0;`
441			`rFFEnNumVertices <= 0;`
442			`rFFEnDataOffset <= 0;`
443			`oRAMWriteEnable <= 0;`
444			`rFFEnBrotherAddress <= 1; //*`
445			`rFFEnParentsBroAddr <= 0;`
446
447			NextState <= `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS;
448			`end`
449			`//------------------------------------`
450			`TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS:
451	82	diegovalve	`begin`
452			`ifdef DEBUG_GFSM
453			if (iDebug_CoreID == `DEBUG_CORE)
454			`$display("CORE %d TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS",iDebug_CoreID);`
455			`endif
456
457	29	diegovalve	`oRAMWriteAddress <= 0;`
458			`oEnableWBM <= 1; //*`
459			`oSetAddressWBM <= 0;`
460			`oNodeReadDone <= 0;`
461			`rFFEnNumVertices <= 0;`
462			`rFFEnDataOffset <= 0;`
463			`oRAMWriteEnable <= 0;`
464			`rFFEnBrotherAddress <= 0;`
465			`rFFEnParentsBroAddr <= 0;`
466			`//rLastAddress <= 1;`
467
468			NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
469			`end`
470			`//------------------------------------`
471			`TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS:
472			`begin`
473			`oRAMWriteAddress <= 0;`
474			`oEnableWBM <= 1;`
475			`oSetAddressWBM <= 0;`
476			`oNodeReadDone <= 0;`
477			`rFFEnNumVertices <= 0;`
478			`rFFEnDataOffset <= 0;`
479			`oRAMWriteEnable <= 0;`
480			`rFFEnBrotherAddress <= 0;`
481			`rFFEnParentsBroAddr <= 0;`
482
483			`if ( iDataAvailable )`
484			NextState <= `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS;
485			`else`
486			NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
487			`end`
488			`//------------------------------------`
489			`TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS:
490			`begin`
491			`oRAMWriteAddress <= 0;`
492			`oEnableWBM <= 0;`
493			`oSetAddressWBM <= 0;`
494			`oNodeReadDone <= 0;`
495			`rFFEnNumVertices <= 0;`
496			`rFFEnDataOffset <= 0;`
497			`oRAMWriteEnable <= 0;`
498			`rFFEnBrotherAddress <= 0;`
499			`rFFEnParentsBroAddr <= 1;`
500
501			NextState <= `TNF_WAIT_NODE_READ_ACK;
502
503			`end`
504			`//------------------------------------`
505			`TNF_WAIT_NODE_READ_ACK:
506			`begin`
507
508			`oRAMWriteAddress <= 0;`
509			`oEnableWBM <= 0;`
510			`oSetAddressWBM <= 0;`
511			`oNodeReadDone <= 1; //*`
512			`rFFEnNumVertices <= 0;`
513			`rFFEnDataOffset <= 0;`
514			`oRAMWriteEnable <= 0;`
515			`rFFEnBrotherAddress <= 0;`
516			`rFFEnParentsBroAddr <= 0;`
517
518			`if ( iTrigger == 0 )`
519			NextState <= `TNF_IDLE;
520			`else`
521			NextState <= `TNF_WAIT_NODE_READ_ACK;
522			`end`
523			`//------------------------------------`
524			`default:`
525			`begin`
526			`oRAMWriteAddress <= 0;`
527			`oEnableWBM <= 0;`
528			`oSetAddressWBM <= 0;`
529			`oNodeReadDone <= 0;`
530			`rFFEnNumVertices <= 0;`
531			`rFFEnDataOffset <= 0;`
532			`oRAMWriteEnable <= 0;`
533			`rFFEnBrotherAddress <= 0;`
534			`rFFEnParentsBroAddr <= 0;`
535
536			NextState <= `TNF_IDLE;
537			`end`
538			`//------------------------------------`
539			`endcase`
540			`end //always`
541			`endmodule`