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1 16 diegovalve
/**********************************************************************************
2
Theia, Ray Cast Programable graphic Processing Unit.
3
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
4
 
5
This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
9
 
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14
 
15
You should have received a copy of the GNU General Public License
16
along with this program; if not, write to the Free Software
17
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18
 
19
***********************************************************************************/
20
 
21
/**********************************************************************************
22
Description:
23
 This is the top level block for THEIA.
24
 THEIA core has 5 main logical blocks called Units.
25
 This module implements the interconections between the Units.
26
 
27
 Units:
28
  > EXE: Mananges execution logic for the SHADERS.
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  > GEO: Manages geometry data structures.
30
  > IO: Input/Output (Wishbone).
31
  > MEM: Internal memory, separate for Instructions and data.
32
  > CONTROL: Main control Finite state machine.
33
 
34
 Internal Buses:
35
        THEIA has separate instruction and data buses.
36
        THEIA avoids using tri-state buses by having separate input/output
37
        for each bus.
38
        There are 2 separate data buses since the Data memory
39
        has a Dual read channel.
40
   Please see the MEM unit chapter in the documentation for more details.
41
 
42
 External Buses:
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        External buses are managed by the IO Unit.
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        External buses follow the wishbone protocol.
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        Please see the IO unit chapter in the documentation for more details.
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**********************************************************************************/
47
 
48
`timescale 1ns / 1ps
49
`include "aDefinitions.v"
50
 
51
module THEIACORE
52
(
53
 
54
input wire                    CLK_I,    //Input clock
55
input wire                    RST_I,    //Input reset
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//Theia Interfaces
57
input wire                    MST_I,    //Master signal, THEIA enters configuration mode
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                                       //when this gets asserted (see documentation)
59
//Wish Bone Interface
60
input wire [`WB_WIDTH-1:0]    DAT_I,     //Input data bus  (Wishbone)
61
output wire [`WB_WIDTH-1:0]   DAT_O,     //Output data bus (Wishbone)
62
input wire                    ACK_I,    //Input ack
63
output wire                   ACK_O,    //Output ack
64
output wire [`WB_WIDTH-1:0]   ADR_O,     //Output address
65
input wire [`WB_WIDTH-1:0]    ADR_I,     //Input address
66
output wire                   WE_O,             //Output write enable
67
input wire                    WE_I,    //Input write enable
68
output wire                   STB_O,    //Strobe signal, see wishbone documentation
69
input wire                    STB_I,    //Strobe signal, see wishbone documentation
70
output wire                   CYC_O,    //Bus cycle signal, see wishbone documentation
71
input wire                    CYC_I,   //Bus cycle signal, see wishbone documentation
72
output wire     [1:0]             TGC_O,   //Bus cycle tag, see THEAI documentation
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input wire [1:0]              TGA_I,   //Input address tag, see THEAI documentation
74
output wire [1:0]             TGA_O,   //Output address tag, see THEAI documentation
75
input wire      [1:0]             TGC_I,   //Bus cycle tag, see THEAI documentation
76
//Control Register
77
input wire [15:0]                         CREG_I
78
 
79
);
80
 
81
//Alias this signals
82
wire Clock,Reset;
83
assign Clock = CLK_I;
84
assign Reset = RST_I;
85
 
86
wire [`DATA_ROW_WIDTH-1:0]                        w2MEM_WriteData;
87
wire [`DATA_ROW_WIDTH-1:0]                        wUCODE_RAMBus;
88
wire [`DATA_ADDRESS_WIDTH-1:0]    wDataWriteAddress;
89
wire                              w2IO__AddrIsImm;
90
wire [`DATA_ADDRESS_WIDTH-1:0]    wUCODE_RAMAddress;
91
wire [`DATA_ADDRESS_WIDTH-1:0]    w2IO__Adr_O_Pointer;
92
wire [`DATA_ADDRESS_WIDTH-1:0]    wGEO2_IO__Adr_O_Pointer;
93
wire                                                                             DataWriteEnable;
94
wire                                                                             wUCODE_RAMWriteEnable;
95
wire [2:0]                                                                RamBusOwner;
96
//Unit intercoanection wires
97
 
98
wire                                                                            wCU2__MicrocodeExecutionDone;
99
wire [`ROM_ADDRESS_WIDTH-1:0]            InitialCodeAddress;
100
wire [`ROM_ADDRESS_WIDTH-1:0]            wInstructionPointer;
101
wire [`INSTRUCTION_WIDTH-1:0]    wEncodedInstruction,wIO2_MEM__ExternalInstruction;
102
wire                                                                            wCU2__ExecuteMicroCode;
103
wire  [`ROM_ADDRESS_WIDTH-1:0]   wIO2_MEM__InstructionWriteAddr;
104
wire [95:0]                                                      wDataRead0, wDataRead1;
105
wire [`DATA_ADDRESS_WIDTH-1:0]   wDataReadAddress0,wDataReadAddress1;
106
wire [`DATA_ADDRESS_WIDTH-1:0]   wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
107
 
108
 
109
wire [`WIDTH-1:0]                                        w2IO__AddressOffset;
110
wire [`DATA_ADDRESS_WIDTH-1:0]   w2IO__DataWriteAddress;
111
wire                                                                            w2IO__Store;
112
wire                                                                            w2IO__EnableWBMaster;
113
 
114
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO2_BUSMUX__DataWriteAddress;
115
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO_2_MEM__DataReadAddress0;
116
wire [`DATA_ROW_WIDTH-1:0]               wIO2_BUSMUX__Bus;
117
wire [`WIDTH-1:0]                                        wIO2__Data;
118
wire [`WIDTH-1:0]                                        wIO2_WBM__Address;
119
wire                                                                            wIO2_BUSMUX__DataWriteEnable;
120
wire                                                                            wIO2__Done;
121
wire                                                                            wCU2_GEO__GeometryFetchEnable;
122
wire                                                                            wIFU2__MicroCodeReturnValue;
123
wire                                                                            wCU2_BCU__ACK;
124
wire                                                                            wGEO2_CU__RequestAABBIU;
125
wire                                                                            wGEO2_CU__RequestBIU;
126
wire                             wGEO2_CU__RequestTCC;
127
wire                                                                            wGEO2_CU__GeometryUnitDone;
128
wire                                                                            wGEO2_CU__Sync;
129
wire                                                                            wEXE2__uCodeDone;
130
wire                                                                            wEXE2_IFU__EXEBusy;
131
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE2_IDU_DataFordward_LastDestination;
132
wire                                                                            wALU2_EXE__BranchTaken;
133
wire                                                                            wALU2_IFU_BranchNotTaken;
134
wire                                                                            w2IO__SetAddress;
135
wire                                                                            wIDU2_IFU__IDUBusy;
136
//Control Registe wires
137
wire[15:0]                                                               wCR2_ControlRegister;
138
wire                                                                            wCR2_TextureMappingEnabled;
139
wire                             wGEO2_CU__TFFDone;
140
wire                             wCU2_GEO__TriggerTFF;
141
wire                             wIO2_MEM_InstructionWriteEnable;
142
wire                             wCU2_IO__WritePixel;
143
wire                             wGEO2_IO__AddrIsImm;
144
wire[31:0]                       wGEO2_IO__AddressOffset;
145
wire                             wGEO2_IO__EnableWBMaster;
146
wire                             wGEO2_IO__SetAddress;
147
wire[`WIDTH-1:0]                 wGEO2__CurrentPitch,wCU2_GEO_Pitch;
148
wire                             wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
149
 
150
`ifdef DEBUG
151
        wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
152
`endif
153
//--------------------------------------------------------
154
 
155
 
156
 
157
        ///////////////// TODO CHANGE FOR MUXES ////////////////////////////////
158
        assign w2MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
159
                wUCODE_RAMBus : `DATA_ROW_WIDTH'bz;
160
 
161
        assign w2MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
162
                wIO2_BUSMUX__Bus : `DATA_ROW_WIDTH'bz;
163
 
164
        assign wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
165
                wUCODE_RAMAddress : `DATA_ADDRESS_WIDTH'bz;
166
 
167
        assign wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
168
        wIO2_BUSMUX__DataWriteAddress : `DATA_ADDRESS_WIDTH'bz;
169
 
170
 
171
         MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) MUX_RA0
172
        (
173
 .Sel(RamBusOwner[1:0]),
174
 .I1(`DATA_ADDRESS_WIDTH'b0),
175
 .I2(wIO_2_MEM__DataReadAddress0),
176
 .I3(wUCODE_RAMReadAddress0),
177
 .O1(wDataReadAddress0)
178
 );
179
 
180
 
181
 
182
 
183
 
184
 
185
assign DataWriteEnable  = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE && MST_I == 1'b0) ?
186
                wUCODE_RAMWriteEnable : 1'bz;
187
 
188
assign DataWriteEnable  = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
189
                wIO2_BUSMUX__DataWriteEnable : 1'bz;
190
 
191
assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
192
 
193
//--------------------------------------------------------
194
//Control Unit Instance
195
        ControlUnit CU
196
        (
197
           .Clock(Clock),
198
                .Reset(Reset),
199
                .iControlRegister(                  wCR2_ControlRegister           ),
200
                .oRamBusOwner(                      RamBusOwner                    ),
201
                .oGFUEnable(                        wCU2_GEO__GeometryFetchEnable  ),
202
                .iTriggerAABBIURequest(             wGEO2_CU__RequestAABBIU        ),
203
                .iTriggerBIURequest(                wGEO2_CU__RequestBIU           ),
204
                .iTriggertTCCRequest(               wGEO2_CU__RequestTCC           ),
205
                .oUCodeEnable(                      wCU2__ExecuteMicroCode         ),
206
                .oUCodeInstructioPointer(           InitialCodeAddress             ),
207
                .iUCodeDone(                        wCU2__MicrocodeExecutionDone   ),
208
                .iIODone(                           wIO2__Done                     ),
209
                .oIOWritePixel(                     wCU2_IO__WritePixel            ),
210
                .iUCodeReturnValue(                 wIFU2__MicroCodeReturnValue    ),
211
                .iGEOSync(                          wGEO2_CU__Sync                 ),
212
                .iTFFDone(                          wGEO2_CU__TFFDone              ),
213
                .oTriggerTFF(                       wCU2_GEO__TriggerTFF           ),
214
                .MST_I(                             MST_I                          ),
215
                .oSetCurrentPitch(                  wCU2_GEO__SetPitch             ),
216
                .iGFUDone(                          wGEO2_CU__GeometryUnitDone     )
217
 
218
        );
219
 
220
 
221
 
222
//--------------------------------------------------------      
223
MemoryUnit MEM
224
(
225
.Clock(Clock),
226
.Reset(Reset),
227
//Data Bus
228
.iDataReadAddress1(       wDataReadAddress0        ),
229
.iDataReadAddress2(       wDataReadAddress1        ),
230
.oData1(                  wDataRead0               ),
231
.oData2(                  wDataRead1               ),
232
.iDataWriteEnable(        DataWriteEnable          ),
233
.iDataWriteAddress(       wDataWriteAddress        ),
234
.iData(                   w2MEM_WriteData          ),
235
//Instruction Bus
236
.iInstructionReadAddress(  wInstructionPointer             ),
237
.oInstruction(             wEncodedInstruction             ),
238
.iInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
239
.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr  ),
240
.iInstruction(             wIO2_MEM__ExternalInstruction   ),
241
.iControlRegister(         CREG_I                          ),
242
.oControlRegister(         wCR2_ControlRegister            )
243
 
244
);
245
 
246
////--------------------------------------------------------
247
ExecutionUnit EXE
248
(
249
 
250
.Clock( Clock),
251
.Reset( Reset ),
252
.iInitialCodeAddress(   InitialCodeAddress     ),
253
.iEncodedInstruction( wEncodedInstruction      ),
254
.oInstructionPointer(   wInstructionPointer    ),
255
.iDataRead0(            wDataRead0             ),
256
.iDataRead1(            wDataRead1             ),
257
.iTrigger(              wCU2__ExecuteMicroCode ),
258
.oDataReadAddress0( wUCODE_RAMReadAddress0 ),
259
.oDataReadAddress1( wUCODE_RAMReadAddress1 ),
260
.oDataWriteEnable(  wUCODE_RAMWriteEnable  ),
261
.oDataWriteAddress( wUCODE_RAMAddress      ),
262
.oDataBus(          wUCODE_RAMBus          ),
263
.oReturnCode(       wIFU2__MicroCodeReturnValue ),
264
.oDone(             wCU2__MicrocodeExecutionDone )
265
 
266
);
267
 
268
////--------------------------------------------------------
269
wire wGEO2__RequestingTextures;
270
wire w2IO_WriteBack_Set;
271
 
272
GeometryUnit GEO
273
(
274
                .Clock( Clock ),
275
                .Reset( Reset ),
276
                .iEnable(                     wCU2_GEO__GeometryFetchEnable       ),
277
                .iTexturingEnable(            wCR2_TextureMappingEnabled          ),
278
                //Wires from IO
279
                .iData_WBM(                                             wIO2__Data ),
280
                .iDataReady_WBM(                                        wIO2__Done ),
281
                //Wires to WBM
282
                .oAddressWBM_Imm(                               wGEO2_IO__AddressOffset                                 ),
283
                .oAddressWBM_fromMEM(         wGEO2_IO__Adr_O_Pointer             ),
284
                .oAddressWBM_IsImm(           wGEO2_IO__AddrIsImm                 ),
285
                .oEnable_WBM(                                           wGEO2_IO__EnableWBMaster                                ),
286
                .oSetAddressWBM(                                        wGEO2_IO__SetAddress                                            ),
287
                .oSetIOWriteBackAddr(         w2IO_WriteBack_Set                  ),
288
                //Wires to CU
289
                .oRequest_AABBIU(             wGEO2_CU__RequestAABBIU                ),
290
                .oRequest_BIU(                wGEO2_CU__RequestBIU                   ),
291
                .oRequest_TCC(                wGEO2_CU__RequestTCC                   ),
292
                .oTFFDone(                    wGEO2_CU__TFFDone                      ),
293
                //Wires to RAM-Bus MUX  
294
                .oRAMWriteAddress(                              w2IO__DataWriteAddress                                  ),
295
                .oRAMWriteEnable(                               w2IO__Store ),
296
                //Wires from Execution Unit
297
                .iMicrocodeExecutionDone(               wCU2__MicrocodeExecutionDone                            ),
298
                .iMicroCodeReturnValue(                 wIFU2__MicroCodeReturnValue                             ),
299
                .oSync(                                                         wGEO2_CU__Sync                                                                  ),
300
                .iTrigger_TFF(                wCU2_GEO__TriggerTFF                   ),
301
                .iBIUHit(                     wIFU2__MicroCodeReturnValue            ),
302
                .oRequestingTextures( wGEO2__RequestingTextures ),
303
                .oDone(                                                         wGEO2_CU__GeometryUnitDone                                      )
304
);
305
 
306
 
307
assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
308
//---------------------------------------------------------------------------------------------------
309
wire[`DATA_ADDRESS_WIDTH-1:0] wIO2__DataReadAddress1;
310
assign wDataReadAddress1 = (wCU2_IO__WritePixel == 0) ?  wUCODE_RAMReadAddress1 : wIO2__DataReadAddress1;
311
assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
312
assign w2IO__AddrIsImm       = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm       : 1'b1;
313
assign w2IO__AddressOffset   = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset   : 32'b0;
314
assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_PIXEL_PITCH;
315
wire w2IO_MasterCycleType;
316
assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
317
 
318
 
319
 
320
assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
321
 
322
 
323
IO_Unit IO
324
(
325
 .Clock(               Clock                            ),
326
 .Reset(               Reset                            ),
327
 .iEnable(            w2IO__EnableWBMaster              ),
328
 .iBusCyc_Type(         w2IO_MasterCycleType            ),
329
 
330
 .iStore(              w2IO__Store                      ),
331
 .iAdr_DataWriteBack(    w2IO__DataWriteAddress         ),
332
 .iAdr_O_Set(      w2IO__SetAddress                     ),
333
 .iAdr_O_Imm(       w2IO__AddressOffset                 ),
334
 .iAdr_O_Type(      w2IO__AddrIsImm                     ),
335
 .iAdr_O_Pointer(  w2IO__Adr_O_Pointer                  ),
336
 .iReadDataBus(        wDataRead0                       ),
337
 .iReadDataBus2(        wDataRead1                       ),
338
 .iDat_O_Pointer(     `OREG_PIXEL_COLOR                 ),
339
 
340
 
341
 .oDataReadAddress(    wIO_2_MEM__DataReadAddress0      ),
342
 .oDataReadAddress2(   wIO2__DataReadAddress1       ),
343
 .oDataWriteAddress(   wIO2_BUSMUX__DataWriteAddress    ),
344
 .oDataBus(               wIO2_BUSMUX__Bus                 ),
345
 .oInstructionBus(     wIO2_MEM__ExternalInstruction    ),
346
 
347
 .oDataWriteEnable(     wIO2_BUSMUX__DataWriteEnable    ),
348
 .oData(               wIO2__Data                       ),
349
 .oInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
350
 .oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
351
 .iWriteBack_Set( w2IO_WriteBack_Set ),
352
 
353
 .oDone(               wIO2__Done                       ),
354
 .MST_I( MST_I ),
355
  //Wish Bone Interface
356
.DAT_I( DAT_I ),
357
.DAT_O( DAT_O ),
358
.ACK_I( ACK_I ),
359
.ACK_O( ACK_O ),
360
.ADR_O( ADR_O ),
361
.ADR_I( ADR_I ),
362
.WE_O(  WE_O  ),
363
.WE_I(  WE_I  ),
364
.STB_O( STB_O ),
365
.STB_I( STB_I ),
366
.CYC_O( CYC_O ),
367
.TGA_I( TGA_I ),
368
.CYC_I( CYC_I ),
369
.TGC_O( TGC_O )
370
 
371
 
372
);
373
//---------------------------------------------------------------------------------------------------
374
endmodule

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