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`timescale 1ns / 1ps
`include "aDefinitions.v"
 
//---------------------------------------------------------------------------
module THEIA
(
 
input wire                    CLK_I,    //Input clock
input wire                    RST_I,    //Input reset
//Theia Interfaces
input wire                    MST_I,    //Master signal, THEIA enters configuration mode
                                       //when this gets asserted (see documentation)
//Wish Bone Interface
input wire [`WB_WIDTH-1:0]    DAT_I,     //Input data bus  (Wishbone)
output wire [`WB_WIDTH-1:0]   DAT_O,     //Output data bus (Wishbone)
input wire                    ACK_I,    //Input ack
output wire                   ACK_O,    //Output ack
output wire [`WB_WIDTH-1:0]   ADR_O,     //Output address
input wire [`WB_WIDTH-1:0]    ADR_I,     //Input address
output wire                   WE_O,             //Output write enable
input wire                    WE_I,    //Input write enable
output wire                   STB_O,    //Strobe signal, see wishbone documentation
input wire                    STB_I,    //Strobe signal, see wishbone documentation
output wire                   CYC_O,    //Bus cycle signal, see wishbone documentation
input wire                    CYC_I,   //Bus cycle signal, see wishbone documentation
output wire     [1:0]             TGC_O,   //Bus cycle tag, see THEAI documentation
input wire [1:0]              TGA_I,   //Input address tag, see THEAI documentation
output wire [1:0]             TGA_O,   //Output address tag, see THEAI documentation
input wire      [1:0]             TGC_I,   //Bus cycle tag, see THEAI documentation
input wire [`MAX_CORES-1:0]      SEL_I,  //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
input wire [`MAX_CORES-1:0]   RENDREN_I,
//Control Register
input wire [15:0]                         CREG_I,
output wire                   DONE_O
 
);
 
 
 
 
wire [`MAX_CORES-1:0] wDone;
wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
wire [`WB_WIDTH-1:0]  wDAT_O_0,wDAT_O_1,wDAT_O_2,wDAT_O_3;
wire [`WB_WIDTH-1:0]  wADR_O_0,wADR_O_1,wADR_O_2,wADR_O_3;
wire [1:0] wTGA_O_0,wTGA_O_1,wTGA_O_2,wTGA_O_3;
wire [1:0] wBusSelect;
 
//wire   wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
//wire   wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
 
wire [`MAX_CORES-1:0] wSTB_O,wWE_O,wACK_O;
 
 
wire [`MAX_CORES-1:0]   wSTB_I;
wire [`MAX_CORES-1:0]   wMST_I;
wire [`MAX_CORES-1:0]   wACK_I;
wire [`MAX_CORES-1:0]   wCYC_I;
wire [1:0]              wTGA_I[`MAX_CORES-1:0];
 
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
//assign DONE_O = wDone[0];
//assign DONE_O = wDone[0] & wDone[1];// & wDone[2];
 
//----------------------------------------------------------------      
//      assign wDone[3:1] = 3'b111;
//      assign wBusRequest[3:2] = 0;
//      assign wSTB_O[3:2] = 0;
//      assign wWE_O[3:2] = 0;
        Module_BusArbitrer ARB1
        (
        .Clock( CLK_I ),
        .Reset( RST_I ),
        .iRequest( wBusRequest ),
        .oGrant(   wBusGranted ),
        .oBusSelect( wBusSelect )
 
        );
//----------------------------------------------------------------
//The Muxes
//DAT_O Mux
MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_DAT_O
 (
 .Sel(wBusSelect),
  .I1(wDAT_O_0),
  .I2(wDAT_O_1),
  .I3(wDAT_O_2),
  .I4(wDAT_O_3),
  .O1( DAT_O )
  );
 
MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_ADR_O
 (
 .Sel(wBusSelect),
  .I1(wADR_O_0),
  .I2(wADR_O_1),
  .I3(wADR_O_2),
  .I4(wADR_O_3),
  .O1( ADR_O )
  );
 
 
 
MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_STB_O
 (
 .Sel(wBusSelect),
  .I1(wSTB_O[0]),
  .I2(wSTB_O[1]),
  .I3(wSTB_O[2]),
  .I4(wSTB_O[3]),
  .O1( STB_O )
  );
 
 
  MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_WE_O
 (
 .Sel(wBusSelect),
  .I1(wWE_O[0]),
  .I2(wWE_O[1]),
  .I3(wWE_O[2]),
  .I4(wWE_O[3]),
  .O1( WE_O )
  );
 
 
  MUXFULLPARALELL_2SEL_GENERIC # ( 2 ) MUX_TGA_O
 (
 .Sel(wBusSelect),
  .I1(wTGA_O_0),
  .I2(wTGA_O_1),
  .I3(wTGA_O_2),
  .I4(wTGA_O_3),
  .O1( TGA_O )
  );
 
 
  assign ACK_O = (wACK_O[0] | wACK_O[1] | wACK_O[2] | wACK_O[3]);
 
        assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
        assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
        assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
        assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
 
        assign wSTB_I[0] = (SEL_I[0]) ? STB_I : 0;
        assign wSTB_I[1] = (SEL_I[1]) ? STB_I : 0;
        assign wSTB_I[2] = (SEL_I[2]) ? STB_I : 0;
        assign wSTB_I[3] = (SEL_I[3]) ? STB_I : 0;
 
        assign wCYC_I[0] = (SEL_I[0]) ? CYC_I : 0;
        assign wCYC_I[1] = (SEL_I[1]) ? CYC_I : 0;
        assign wCYC_I[2] = (SEL_I[2]) ? CYC_I : 0;
        assign wCYC_I[3] = (SEL_I[3]) ? CYC_I : 0;
 
        assign wTGA_I[0] = (SEL_I[0]) ? TGA_I : 0;
        assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
        assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
        assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
 
//----------------------------------------------------------------
 
        THEIACORE THEIA_CORE0
                (
                .CLK_I( CLK_I ),
                .RST_I( RST_I ),
                .RENDREN_I( RENDREN_I[0] ),
 
                //Slave signals
                .ADR_I( ADR_I ),
                .WE_I(  WE_I  ),
                .STB_I(  wSTB_I[0] ),
                //-----------------------------------
                //This signal behaves in a very funny way...
                //
                .ACK_I( ACK_I ),
                //-----------------------------------
                .CYC_I( wCYC_I[0] ),
                .MST_I( wMST_I[0] ),
                .TGA_I( wTGA_I[0] ),
                .CREG_I( CREG_I ),
 
                //Master Signals
                .WE_O (         wWE_O[0]  ),
                .STB_O(         wSTB_O[0] ),
                .ACK_O(         wACK_O[0] ),
                .DAT_O(  wDAT_O_0 ),
                .ADR_O(  wADR_O_0 ),
                .CYC_O(  wBusRequest[0] ),
                .GNT_I(         wBusGranted[0] ),
                .TGA_O(         wTGA_O_0 ),
                `ifdef DEBUG
                .iDebug_CoreID( `MAX_CORES'd0 ),
                `endif
                //Other
                .DAT_I( DAT_I ),
                .DONE_O( wDone[0] )
 
        );
//----------------------------------------------------------------
THEIACORE THEIA_CORE1
                (
                .CLK_I( CLK_I ),
                .RST_I( RST_I ),
                .RENDREN_I( RENDREN_I[1] ),
 
                //Slave signals
                .ADR_I( ADR_I ),
                .WE_I(  WE_I  ),
                .STB_I(  wSTB_I[1] ),//ok
                .ACK_I(  ACK_I ),
                .CYC_I( wCYC_I[1] ),//ok
                .MST_I( wMST_I[1] ),//ok
                .TGA_I( wTGA_I[1] ),//ok
                .CREG_I( CREG_I ),
 
                //Master Signals
                .WE_O (         wWE_O[1]  ),
                .STB_O(         wSTB_O[1] ),
                .ACK_O(         wACK_O[1] ),
                .DAT_O(  wDAT_O_1 ),
                .ADR_O(  wADR_O_1 ),
                .CYC_O(  wBusRequest[1] ),
                .GNT_I(         wBusGranted[1] ),
                .TGA_O(         wTGA_O_1 ),
                `ifdef DEBUG
                .iDebug_CoreID( `MAX_CORES'd1 ),
                `endif
                //Other
                .DAT_I( DAT_I ),
                .DONE_O( wDone[1] )
 
        );
//----------------------------------------------------------------
THEIACORE THEIA_CORE2
                (
                .CLK_I( CLK_I ),
                .RST_I( RST_I ),
                .RENDREN_I( RENDREN_I[2] ),
 
                //Slave signals
                .ADR_I( ADR_I ),
                .WE_I(  WE_I  ),
                .STB_I(  wSTB_I[2] ),
                .ACK_I(  ACK_I ),
                .CYC_I( wCYC_I[2] ),
                .MST_I( wMST_I[2] ),
                .TGA_I( wTGA_I[2] ),
                .CREG_I( CREG_I ),
 
                //Master Signals
                .WE_O (         wWE_O[2]  ),
                .STB_O(         wSTB_O[2] ),
                .ACK_O(         wACK_O[2] ),
                .DAT_O(  wDAT_O_2 ),
                .ADR_O(  wADR_O_2 ),
                .CYC_O(  wBusRequest[2] ),
                .GNT_I(         wBusGranted[2] ),
                .TGA_O(         wTGA_O_2 ),
                `ifdef DEBUG
                .iDebug_CoreID( `MAX_CORES'd2 ),
                `endif
                //Other
                .DAT_I( DAT_I ),
                .DONE_O( wDone[2] )
 
        );
        //----------------------------------------------------------------
THEIACORE THEIA_CORE3
                (
                .CLK_I( CLK_I ),
                .RST_I( RST_I ),
                .RENDREN_I( RENDREN_I[3] ),
 
                //Slave signals
                .ADR_I( ADR_I ),
                .WE_I(  WE_I  ),
                .STB_I(  wSTB_I[3] ),
                .ACK_I(  ACK_I ),
                .CYC_I( wCYC_I[3] ),
                .MST_I( wMST_I[3] ),
                .TGA_I( wTGA_I[3] ),
                .CREG_I( CREG_I ),
 
                //Master Signals
                .WE_O (         wWE_O[3]  ),
                .STB_O(         wSTB_O[3] ),
                .ACK_O(         wACK_O[3] ),
                .DAT_O(  wDAT_O_3 ),
                .ADR_O(  wADR_O_3 ),
                .CYC_O(  wBusRequest[3] ),
                .GNT_I(         wBusGranted[3] ),
                .TGA_O(         wTGA_O_3 ),
                `ifdef DEBUG
                .iDebug_CoreID( `MAX_CORES'd3 ),
                `endif
                //Other
                .DAT_I( DAT_I ),
                .DONE_O( wDone[3] )
 
        );
//----------------------------------------------------------------
endmodule
//---------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	76	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3
4			`//---------------------------------------------------------------------------`
5			`module THEIA`
6			`(`
7	16	diegovalve
8			`input wire CLK_I, //Input clock`
9			`input wire RST_I, //Input reset`
10			`//Theia Interfaces`
11			`input wire MST_I, //Master signal, THEIA enters configuration mode`
12			`//when this gets asserted (see documentation)`
13			`//Wish Bone Interface`
14			input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
15			output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
16			`input wire ACK_I, //Input ack`
17			`output wire ACK_O, //Output ack`
18			output wire [`WB_WIDTH-1:0] ADR_O, //Output address
19			input wire [`WB_WIDTH-1:0] ADR_I, //Input address
20			`output wire WE_O, //Output write enable`
21			`input wire WE_I, //Input write enable`
22			`output wire STB_O, //Strobe signal, see wishbone documentation`
23			`input wire STB_I, //Strobe signal, see wishbone documentation`
24			`output wire CYC_O, //Bus cycle signal, see wishbone documentation`
25			`input wire CYC_I, //Bus cycle signal, see wishbone documentation`
26			`output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation`
27			`input wire [1:0] TGA_I, //Input address tag, see THEAI documentation`
28			`output wire [1:0] TGA_O, //Output address tag, see THEAI documentation`
29	76	diegovalve	`input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation`
30			input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
31			input wire [`MAX_CORES-1:0] RENDREN_I,
32	16	diegovalve	`//Control Register`
33	76	diegovalve	`input wire [15:0] CREG_I,`
34			`output wire DONE_O`
35	16	diegovalve
36	76	diegovalve	`);`
37	16	diegovalve
38
39
40	76	diegovalve
41			wire [`MAX_CORES-1:0] wDone;
42			wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
43			wire [`WB_WIDTH-1:0] wDAT_O_0,wDAT_O_1,wDAT_O_2,wDAT_O_3;
44			wire [`WB_WIDTH-1:0] wADR_O_0,wADR_O_1,wADR_O_2,wADR_O_3;
45			`wire [1:0] wTGA_O_0,wTGA_O_1,wTGA_O_2,wTGA_O_3;`
46			`wire [1:0] wBusSelect;`
47
48			`//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;`
49			`//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;`
50
51	82	diegovalve	wire [`MAX_CORES-1:0] wSTB_O,wWE_O,wACK_O;
52	76	diegovalve
53
54			wire [`MAX_CORES-1:0] wSTB_I;
55			wire [`MAX_CORES-1:0] wMST_I;
56			wire [`MAX_CORES-1:0] wACK_I;
57			wire [`MAX_CORES-1:0] wCYC_I;
58			wire [1:0] wTGA_I[`MAX_CORES-1:0];
59
60	82	diegovalve	`assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];`
61			`//assign DONE_O = wDone[0];`
62			`//assign DONE_O = wDone[0] & wDone[1];// & wDone[2];`
63	76	diegovalve
64			`//----------------------------------------------------------------`
65			`// assign wDone[3:1] = 3'b111;`
66	82	diegovalve	`// assign wBusRequest[3:2] = 0;`
67			`// assign wSTB_O[3:2] = 0;`
68			`// assign wWE_O[3:2] = 0;`
69	76	diegovalve	`Module_BusArbitrer ARB1`
70			`(`
71			`.Clock( CLK_I ),`
72			`.Reset( RST_I ),`
73			`.iRequest( wBusRequest ),`
74			`.oGrant( wBusGranted ),`
75			`.oBusSelect( wBusSelect )`
76
77			`);`
78			`//----------------------------------------------------------------`
79			`//The Muxes`
80			`//DAT_O Mux`
81			MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_DAT_O
82			`(`
83			`.Sel(wBusSelect),`
84			`.I1(wDAT_O_0),`
85			`.I2(wDAT_O_1),`
86			`.I3(wDAT_O_2),`
87			`.I4(wDAT_O_3),`
88			`.O1( DAT_O )`
89			`);`
90
91			MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_ADR_O
92			`(`
93			`.Sel(wBusSelect),`
94			`.I1(wADR_O_0),`
95			`.I2(wADR_O_1),`
96			`.I3(wADR_O_2),`
97			`.I4(wADR_O_3),`
98			`.O1( ADR_O )`
99			`);`
100
101
102
103			`MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_STB_O`
104			`(`
105			`.Sel(wBusSelect),`
106			`.I1(wSTB_O[0]),`
107			`.I2(wSTB_O[1]),`
108			`.I3(wSTB_O[2]),`
109			`.I4(wSTB_O[3]),`
110			`.O1( STB_O )`
111			`);`
112
113
114			`MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_WE_O`
115			`(`
116			`.Sel(wBusSelect),`
117			`.I1(wWE_O[0]),`
118			`.I2(wWE_O[1]),`
119			`.I3(wWE_O[2]),`
120			`.I4(wWE_O[3]),`
121			`.O1( WE_O )`
122			`);`
123
124
125			`MUXFULLPARALELL_2SEL_GENERIC # ( 2 ) MUX_TGA_O`
126			`(`
127			`.Sel(wBusSelect),`
128			`.I1(wTGA_O_0),`
129			`.I2(wTGA_O_1),`
130			`.I3(wTGA_O_2),`
131			`.I4(wTGA_O_3),`
132			`.O1( TGA_O )`
133			`);`
134
135
136	82	diegovalve	`assign ACK_O = (wACK_O[0] \| wACK_O[1] \| wACK_O[2] \| wACK_O[3]);`
137	76	diegovalve
138			`assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;`
139			`assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;`
140			`assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;`
141			`assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;`
142
143			`assign wSTB_I[0] = (SEL_I[0]) ? STB_I : 0;`
144			`assign wSTB_I[1] = (SEL_I[1]) ? STB_I : 0;`
145			`assign wSTB_I[2] = (SEL_I[2]) ? STB_I : 0;`
146			`assign wSTB_I[3] = (SEL_I[3]) ? STB_I : 0;`
147
148			`assign wCYC_I[0] = (SEL_I[0]) ? CYC_I : 0;`
149			`assign wCYC_I[1] = (SEL_I[1]) ? CYC_I : 0;`
150			`assign wCYC_I[2] = (SEL_I[2]) ? CYC_I : 0;`
151			`assign wCYC_I[3] = (SEL_I[3]) ? CYC_I : 0;`
152
153			`assign wTGA_I[0] = (SEL_I[0]) ? TGA_I : 0;`
154			`assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;`
155			`assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;`
156			`assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;`
157
158			`//----------------------------------------------------------------`
159	82	diegovalve
160	76	diegovalve	`THEIACORE THEIA_CORE0`
161			`(`
162			`.CLK_I( CLK_I ),`
163			`.RST_I( RST_I ),`
164			`.RENDREN_I( RENDREN_I[0] ),`
165
166			`//Slave signals`
167			`.ADR_I( ADR_I ),`
168			`.WE_I( WE_I ),`
169			`.STB_I( wSTB_I[0] ),`
170			`//-----------------------------------`
171			`//This signal behaves in a very funny way...`
172			`//`
173	82	diegovalve	`.ACK_I( ACK_I ),`
174	76	diegovalve	`//-----------------------------------`
175			`.CYC_I( wCYC_I[0] ),`
176			`.MST_I( wMST_I[0] ),`
177			`.TGA_I( wTGA_I[0] ),`
178			`.CREG_I( CREG_I ),`
179
180			`//Master Signals`
181			`.WE_O ( wWE_O[0] ),`
182			`.STB_O( wSTB_O[0] ),`
183	82	diegovalve	`.ACK_O( wACK_O[0] ),`
184	76	diegovalve	`.DAT_O( wDAT_O_0 ),`
185			`.ADR_O( wADR_O_0 ),`
186			`.CYC_O( wBusRequest[0] ),`
187			`.GNT_I( wBusGranted[0] ),`
188			`.TGA_O( wTGA_O_0 ),`
189			`ifdef DEBUG
190			.iDebug_CoreID( `MAX_CORES'd0 ),
191			`endif
192			`//Other`
193			`.DAT_I( DAT_I ),`
194			`.DONE_O( wDone[0] )`
195	16	diegovalve
196	76	diegovalve	`);`
197			`//----------------------------------------------------------------`
198			`THEIACORE THEIA_CORE1`
199			`(`
200			`.CLK_I( CLK_I ),`
201			`.RST_I( RST_I ),`
202			`.RENDREN_I( RENDREN_I[1] ),`
203
204			`//Slave signals`
205			`.ADR_I( ADR_I ),`
206			`.WE_I( WE_I ),`
207			`.STB_I( wSTB_I[1] ),//ok`
208	82	diegovalve	`.ACK_I( ACK_I ),`
209	76	diegovalve	`.CYC_I( wCYC_I[1] ),//ok`
210			`.MST_I( wMST_I[1] ),//ok`
211			`.TGA_I( wTGA_I[1] ),//ok`
212			`.CREG_I( CREG_I ),`
213
214			`//Master Signals`
215			`.WE_O ( wWE_O[1] ),`
216			`.STB_O( wSTB_O[1] ),`
217	82	diegovalve	`.ACK_O( wACK_O[1] ),`
218	76	diegovalve	`.DAT_O( wDAT_O_1 ),`
219			`.ADR_O( wADR_O_1 ),`
220			`.CYC_O( wBusRequest[1] ),`
221			`.GNT_I( wBusGranted[1] ),`
222			`.TGA_O( wTGA_O_1 ),`
223			`ifdef DEBUG
224			.iDebug_CoreID( `MAX_CORES'd1 ),
225			`endif
226			`//Other`
227			`.DAT_I( DAT_I ),`
228			`.DONE_O( wDone[1] )`
229	16	diegovalve
230	76	diegovalve	`);`
231			`//----------------------------------------------------------------`
232	82	diegovalve	`THEIACORE THEIA_CORE2`
233			`(`
234			`.CLK_I( CLK_I ),`
235			`.RST_I( RST_I ),`
236			`.RENDREN_I( RENDREN_I[2] ),`
237
238			`//Slave signals`
239			`.ADR_I( ADR_I ),`
240			`.WE_I( WE_I ),`
241			`.STB_I( wSTB_I[2] ),`
242			`.ACK_I( ACK_I ),`
243			`.CYC_I( wCYC_I[2] ),`
244			`.MST_I( wMST_I[2] ),`
245			`.TGA_I( wTGA_I[2] ),`
246			`.CREG_I( CREG_I ),`
247
248			`//Master Signals`
249			`.WE_O ( wWE_O[2] ),`
250			`.STB_O( wSTB_O[2] ),`
251			`.ACK_O( wACK_O[2] ),`
252			`.DAT_O( wDAT_O_2 ),`
253			`.ADR_O( wADR_O_2 ),`
254			`.CYC_O( wBusRequest[2] ),`
255			`.GNT_I( wBusGranted[2] ),`
256			`.TGA_O( wTGA_O_2 ),`
257			`ifdef DEBUG
258			.iDebug_CoreID( `MAX_CORES'd2 ),
259			`endif
260			`//Other`
261			`.DAT_I( DAT_I ),`
262			`.DONE_O( wDone[2] )`
263
264			`);`
265			`//----------------------------------------------------------------`
266			`THEIACORE THEIA_CORE3`
267			`(`
268			`.CLK_I( CLK_I ),`
269			`.RST_I( RST_I ),`
270			`.RENDREN_I( RENDREN_I[3] ),`
271
272			`//Slave signals`
273			`.ADR_I( ADR_I ),`
274			`.WE_I( WE_I ),`
275			`.STB_I( wSTB_I[3] ),`
276			`.ACK_I( ACK_I ),`
277			`.CYC_I( wCYC_I[3] ),`
278			`.MST_I( wMST_I[3] ),`
279			`.TGA_I( wTGA_I[3] ),`
280			`.CREG_I( CREG_I ),`
281
282			`//Master Signals`
283			`.WE_O ( wWE_O[3] ),`
284			`.STB_O( wSTB_O[3] ),`
285			`.ACK_O( wACK_O[3] ),`
286			`.DAT_O( wDAT_O_3 ),`
287			`.ADR_O( wADR_O_3 ),`
288			`.CYC_O( wBusRequest[3] ),`
289			`.GNT_I( wBusGranted[3] ),`
290			`.TGA_O( wTGA_O_3 ),`
291			`ifdef DEBUG
292			.iDebug_CoreID( `MAX_CORES'd3 ),
293			`endif
294			`//Other`
295			`.DAT_I( DAT_I ),`
296			`.DONE_O( wDone[3] )`
297
298			`);`
299			`//----------------------------------------------------------------`
300	76	diegovalve	`endmodule`
301			`//---------------------------------------------------------------------------`

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