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1 213 diegovalve 
`ifndef COLLATERALS_V
2 
`define COLLATERALS_V
3 
 
4 
`timescale 1ns / 1ps
5 
`include "aDefinitions.v"
6 
/**********************************************************************************
7 
Theia, Ray Cast Programable graphic Processing Unit.
8 
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
9 
 
10 
This program is free software; you can redistribute it and/or
11 
modify it under the terms of the GNU General Public License
12 
as published by the Free Software Foundation; either version 2
13 
of the License, or (at your option) any later version.
14 
 
15 
This program is distributed in the hope that it will be useful,
16 
but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 
GNU General Public License for more details.
19 
 
20 
You should have received a copy of the GNU General Public License
21 
along with this program; if not, write to the Free Software
22 
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
23 
 
24 
***********************************************************************************/
25 
 
26 
//----------------------------------------------------
27 
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
28 
(
29 
        input wire                              Clock,
30 
        input wire                              Reset,
31 
        input wire                              Enable,
32 
        input wire [SIZE-1:0]    D,
33 
        output reg [SIZE-1:0]    Q
34 
);
35 
 
36 
 
37 
always @ (posedge Clock)
38 
begin
39 
        if ( Reset )
40 
                Q <= {SIZE{1'b0}};
41 
        else
42 
        begin
43 
                if (Enable)
44 
                        Q <= D;
45 
        end
46 
 
47 
end//always
48 
 
49 
endmodule
50 
//------------------------------------------------
51 
module PULSE
52 
(
53 
input wire                              Clock,
54 
input wire                              Reset,
55 
input wire                              Enable,
56 
input wire              D,
57 
output wire          Q
58 
);
59 
 
60 
wire wDelay;
61 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD (Clock,Reset,Enable,D,wDelay);
62 
 
63 
assign Q = (Enable) ?  (D ^ wDelay) & D: 1'b0;
64 
 
65 
endmodule
66 
//------------------------------------------------
67 
module ADDER # (parameter SIZE=`WIDTH)
68 
(
69 
input wire Clock,
70 
input wire Reset,
71 
input wire iTrigger,
72 
input wire [SIZE-1:0] iA,iB,
73 
output wire [SIZE-1:0] oR,
74 
output wire            oDone
75 
);
76 
wire [SIZE-1:0] wR,wR_Delay;
77 
assign wR = iA + iB;
78 
 
79 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
80 
 
81 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
82 
assign oR = wR_Delay;
83 
 
84 
endmodule
85 
//------------------------------------------------
86 
module OR # (parameter SIZE=`WIDTH)
87 
(
88 
input wire Clock,
89 
input wire Reset,
90 
input wire iTrigger,
91 
input wire [SIZE-1:0] iA,iB,
92 
output wire [SIZE-1:0] oR,
93 
output wire            oDone
94 
);
95 
wire [SIZE-1:0] wR,wR_Delay;
96 
assign wR = iA | iB;
97 
 
98 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
99 
 
100 
 
101 
FFD_POSEDGE_SYNCRONOUS_RESET #  (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
102 
assign oR = wR_Delay;
103 
 
104 
endmodule
105 
//------------------------------------------------
106 
module AND # (parameter SIZE=`WIDTH)
107 
(
108 
input wire Clock,
109 
input wire Reset,
110 
input wire iTrigger,
111 
input wire [SIZE-1:0] iA,iB,
112 
output wire [SIZE-1:0] oR,
113 
output wire            oDone
114 
);
115 
wire [SIZE-1:0] wR,wR_Delay;
116 
assign wR = iA & iB;
117 
 
118 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
119 
 
120 
 
121 
FFD_POSEDGE_SYNCRONOUS_RESET #  (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
122 
assign oR = wR_Delay;
123 
 
124 
endmodule
125 
//------------------------------------------------
126 
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
127 
(
128 
input wire Clock, Reset,
129 
input wire [SIZE-1:0] Initial,
130 
input wire Enable,
131 
output reg [SIZE-1:0] Q
132 
);
133 
 
134 
 
135 
  always @(posedge Clock )
136 
  begin
137 
      if (Reset)
138 
        Q <= Initial;
139 
      else
140 
                begin
141 
                if (Enable)
142 
                        Q <= Q + 1;
143 
 
144 
                end
145 
  end
146 
 
147 
endmodule
148 
 
149 
//----------------------------------------------------------------------
150 
module DECODER_ONEHOT_2_BINARY
151 
(
152 
input wire [5:0] iIn,
153 
output reg[5:0] oOut
154 
);
155 
 
156 
always @ (*)
157 
begin
158 
        case (iIn)
159 
                6'b000000: oOut = 0;
160 
                6'b000001: oOut = 1;
161 
                6'b000010: oOut = 2;
162 
                6'b000100: oOut = 3;
163 
                6'b001000: oOut = 4;
164 
                6'b010000: oOut = 5;
165 
                6'b100000: oOut = 6;
166 
        default:
167 
                oOut = 0;
168 
        endcase
169 
end
170 
endmodule
171 
//----------------------------------------------------------------------
172 
 
173 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
174 
 (
175 
 input wire [SEL_WIDTH-1:0] Sel,
176 
 input wire  En,
177 
 output wire [OUTPUT_WIDTH-1:0] O
178 
 );
179 
 
180 
reg[OUTPUT_WIDTH-1:0] shift;
181 
 
182 
always @ ( * )
183 
begin
184 
        if (~En)
185 
                shift = 1;
186 
        else
187 
                shift = (1 <<   Sel);
188 
 
189 
 
190 
end
191 
 
192 
assign O = ( ~En ) ? 0 : shift ;
193 
 
194 
//assign O = En & (1 << Sel);
195 
 
196 
endmodule
197 
 
198 
//----------------------------------------------------------------------
199 
module MUXFULLPARALELL_GENERIC #(parameter  WIDTH = `WIDTH, parameter  CHANNELS = 4, parameter SELBITS = 2)
200 
(
201 
 
202 
    input wire   [(CHANNELS*WIDTH)-1:0]      in_bus,
203 
    input wire   [SELBITS-1:0]    sel,
204 
 
205 
    output wire [WIDTH-1:0]                 out
206 
    );
207 
 
208 
genvar ig;
209 
 
210 
wire    [WIDTH-1:0] input_array [0:CHANNELS-1];
211 
 
212 
assign  out = input_array[sel];
213 
 
214 
generate
215 
    for(ig=0; ig<CHANNELS; ig=ig+1)
216 
         begin: array_assignments
217 
        assign  input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
218 
    end
219 
endgenerate
220 
 
221 
 
222 
 
223 
endmodule
224 
//----------------------------------------------------------------------
225 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
226 
 (
227 
 input wire [1:0] Sel,
228 
 input wire [SIZE-1:0]I1, I2, I3,I4,
229 
 output reg [SIZE-1:0] O1
230 
 );
231 
 
232 
always @( * )
233 
 
234 
  begin
235 
 
236 
    case (Sel)
237 
 
238 
      2'b00: O1 = I1;
239 
      2'b01: O1 = I2;
240 
                2'b10: O1 = I3;
241 
                2'b11: O1 = I4;
242 
                default: O1 = SIZE;
243 
 
244 
    endcase
245 
 
246 
  end
247 
 
248 
endmodule
249 
//------------------------------------------------------------------------
250 
module MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )
251 
 (
252 
 input wire [2:0] Sel,
253 
 input wire [SIZE-1:0]I1, I2, I3,I4,I5,I6,I7,I8,
254 
 output reg [SIZE-1:0] O1
255 
 );
256 
 
257 
always @( * )
258 
 
259 
  begin
260 
 
261 
    case (Sel)
262 
 
263 
      3'b000: O1 = I1;
264 
      3'b001: O1 = I2;
265 
                3'b010: O1 = I3;
266 
                3'b011: O1 = I4;
267 
                3'b100: O1 = I5;
268 
                3'b101: O1 = I6;
269 
                3'b110: O1 = I7;
270 
                3'b111: O1 = I8;
271 
                default: O1 = SIZE;
272 
 
273 
    endcase
274 
 
275 
  end
276 
 
277 
endmodule
278 
//------------------------------------------------------------------------
279 
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
280 
( input wire Clock,
281 
  input wire Reset,
282 
  input wire[SIZE-1:0] Initial,
283 
  input wire      Enable,
284 
  output wire[SIZE-1:0] O
285 
);
286 
 
287 
reg [SIZE-1:0] tmp;
288 
 
289 
 
290 
  always @(posedge Clock)
291 
  begin
292 
  if (Reset)
293 
                tmp <= Initial;
294 
        else
295 
        begin
296 
                if (Enable)
297 
                begin
298 
                        if (tmp[SIZE-1])
299 
                        begin
300 
                                tmp <= Initial;
301 
                        end
302 
                        else
303 
                        begin
304 
                                tmp <= tmp << 1;
305 
                        end
306 
                end
307 
        end
308 
  end
309 
 
310 
 
311 
    assign O  = tmp;
312 
endmodule
313 
//------------------------------------------------
314 
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
315 
 (
316 
 input wire [2:0] Sel,
317 
 input wire [SIZE-1:0]I1, I2, I3,
318 
 output reg [SIZE-1:0] O1
319 
 );
320 
 
321 
always @( * )
322 
 
323 
  begin
324 
 
325 
    case (Sel)
326 
 
327 
      3'b001: O1 = I1;
328 
      3'b010: O1 = I2;
329 
      3'b100: O1 = I3;
330 
      default: O1 = SIZE;
331 
 
332 
    endcase
333 
 
334 
  end
335 
 
336 
endmodule
337 
//------------------------------------------------
338 
module MUXFULLPARALELL_3SEL_EN # ( parameter SIZE=`WIDTH )
339 
 (
340 
 input wire [1:0] SEL,
341 
 input wire [SIZE-1:0]I1, I2, I3,
342 
 input wire EN,
343 
 output reg [SIZE-1:0] O1
344 
 );
345 
 
346 
always @( * )
347 
 
348 
  begin
349 
        if (EN)
350 
        begin
351 
    case (SEL)
352 
 
353 
      2'b00: O1 = I1;
354 
      2'b01: O1 = I2;
355 
      2'b10: O1 = I3;
356 
      default: O1 = SIZE;
357 
 
358 
    endcase
359 
        end
360 
        else
361 
        begin
362 
                O1 = I1;
363 
        end
364 
  end
365 
 
366 
endmodule
367 
//------------------------------------------------
368 
module MUXFULLPARALELL_4SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
369 
 (
370 
 input wire [2:0] Sel,
371 
 input wire [SIZE-1:0]I1, I2, I3, I4,
372 
 output reg [SIZE-1:0] O1
373 
 );
374 
 
375 
always @( * )
376 
 
377 
  begin
378 
 
379 
    case (Sel)
380 
 
381 
      4'b0001: O1 = I1;
382 
      4'b0010: O1 = I2;
383 
      4'b0100: O1 = I3;
384 
                4'b1000: O1 = I4;
385 
      default: O1 = SIZE;
386 
 
387 
    endcase
388 
 
389 
  end
390 
 
391 
endmodule
392 
//------------------------------------------------
393 
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
394 
( input wire Clock,
395 
  input wire Reset,
396 
  input wire[SIZE-1:0] Initial,
397 
  input wire      Enable,
398 
  output wire[SIZE-1:0] O
399 
);
400 
 
401 
reg [SIZE-1:0] tmp;
402 
 
403 
 
404 
  always @(posedge Clock)
405 
  begin
406 
  if (Reset)
407 
                tmp <= Initial;
408 
        else
409 
        begin
410 
                if (Enable)
411 
                        tmp <= tmp << 1;
412 
        end
413 
  end
414 
 
415 
 
416 
    assign O  = tmp;
417 
endmodule
418 
//------------------------------------------------
419 
//------------------------------------------------
420 
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
421 
( input wire Clock,
422 
  input wire Reset,
423 
  input wire[SIZE-1:0] Initial,
424 
  input wire      Enable,
425 
  output wire[SIZE-1:0] O
426 
);
427 
 
428 
reg [SIZE-1:0] tmp;
429 
 
430 
 
431 
  always @(posedge Clock)
432 
  begin
433 
  if (Reset || tmp[SIZE-1])
434 
                tmp <= Initial;
435 
        else
436 
        begin
437 
                if (Enable)
438 
                        tmp <= tmp << 1;
439 
        end
440 
  end
441 
 
442 
 
443 
    assign O  = tmp;
444 
endmodule
445 
//-----------------------------------------------------------
446 
/*
447 
        Sorry forgot how this flop is called.
448 
        Any way Truth table is this
449 
 
450 
        Q       S       Q_next R
451 
 
452 
 
453 
        1       0        1                0
454 
        1       1       1                0
455 
        X       X       0                 1
456 
 
457 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
458 
        gets another S = 1, it keeps the output to 1.
459 
*/
460 
module FFToggleOnce_1Bit
461 
(
462 
        input wire Clock,
463 
        input wire Reset,
464 
        input wire Enable,
465 
        input wire S,
466 
        output reg Q
467 
 
468 
);
469 
 
470 
 
471 
reg Q_next;
472 
 
473 
always @ (negedge Clock)
474 
begin
475 
        Q <= Q_next;
476 
end
477 
 
478 
always @ ( posedge Clock )
479 
begin
480 
        if (Reset)
481 
                Q_next <= 0;
482 
        else if (Enable)
483 
                Q_next <= (S && !Q) || Q;
484 
        else
485 
                Q_next <= Q;
486 
end
487 
endmodule
488 
 
489 
//-----------------------------------------------------------
490 
 
491 
 
492 
module FFD32_POSEDGE
493 
(
494 
        input wire Clock,
495 
        input wire[31:0] D,
496 
        output reg[31:0] Q
497 
);
498 
 
499 
        always @ (posedge Clock)
500 
                Q <= D;
501 
 
502 
endmodule
503 
 
504 
//------------------------------------------------
505 
module MUXFULLPARALELL_96bits_2SEL
506 
 (
507 
 input wire Sel,
508 
 input wire [95:0]I1, I2,
509 
 output reg [95:0] O1
510 
 );
511 
 
512 
 
513 
 
514 
always @( * )
515 
 
516 
  begin
517 
 
518 
    case (Sel)
519 
 
520 
      1'b0: O1 = I1;
521 
      1'b1: O1 = I2;
522 
 
523 
    endcase
524 
 
525 
  end
526 
 
527 
endmodule
528 
 
529 
//------------------------------------------------
530 
module MUXFULLPARALELL_16bits_2SEL
531 
 (
532 
 input wire Sel,
533 
 input wire [15:0]I1, I2,
534 
 output reg [15:0] O1
535 
 );
536 
 
537 
 
538 
 
539 
always @( * )
540 
 
541 
  begin
542 
 
543 
    case (Sel)
544 
 
545 
      1'b0: O1 = I1;
546 
      1'b1: O1 = I2;
547 
 
548 
    endcase
549 
 
550 
  end
551 
 
552 
endmodule
553 
 
554 
//--------------------------------------------------------------
555 
 
556 
  module FFT1
557 
  (
558 
   input wire D,
559 
   input wire Clock,
560 
   input wire Reset ,
561 
   output reg Q
562 
 );
563 
 
564 
  always @ ( posedge Clock or posedge Reset )
565 
  begin
566 
 
567 
        if (Reset)
568 
        begin
569 
    Q <= 1'b0;
570 
   end
571 
        else
572 
        begin
573 
                if (D)
574 
                        Q <=  ! Q;
575 
        end
576 
 
577 
  end//always
578 
 
579 
 endmodule
580 
//--------------------------------------------------------------
581 
/*
582 
module FIFO_SYNCHRNOUS_RESET # ( parameter SIZE=`WIDTH, parameter DEPTH=16 )
583 
(
584 
input wire Clock,
585 
input wire Reset,
586 
wr_cs    , // Write chip select
587 
rd_cs    , // Read chipe select
588 
input wire            iData,
589 
input wire            iReadEnable,
590 
input wire[SIZE-1:0]  iWriteEnable,
591 
output reg[SIZE-1:0]  oData,
592 
output wire           oEmpy,
593 
output wire           oFull
594 
);
595 
 
596 
// FIFO constants
597 
parameter DATA_WIDTH = 8;
598 
parameter ADDR_WIDTH = 8;
599 
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
600 
// Port Declarations
601 
input clk ;
602 
input rst ;
603 
input wr_cs ;
604 
input rd_cs ;
605 
input rd_en ;
606 
input wr_en ;
607 
input [DATA_WIDTH-1:0] data_in ;
608 
output full ;
609 
output empty ;
610 
output [DATA_WIDTH-1:0] data_out ;
611 
 
612 
//-----------Internal variables-------------------
613 
reg [ADDR_WIDTH-1:0] wr_pointer;
614 
reg [ADDR_WIDTH-1:0] rd_pointer;
615 
reg [ADDR_WIDTH :0] status_cnt;
616 
reg [DATA_WIDTH-1:0] data_out ;
617 
wire [DATA_WIDTH-1:0] data_ram ;
618 
 
619 
//-----------Variable assignments---------------
620 
assign full = (status_cnt == (RAM_DEPTH-1));
621 
assign empty = (status_cnt == 0);
622 
 
623 
//-----------Code Start---------------------------
624 
always @ (posedge clk or posedge rst)
625 
begin : WRITE_POINTER
626 
  if (rst) begin
627 
    wr_pointer <= 0;
628 
  end else if (wr_cs && wr_en ) begin
629 
    wr_pointer <= wr_pointer + 1;
630 
  end
631 
end
632 
 
633 
always @ (posedge clk or posedge rst)
634 
begin : READ_POINTER
635 
  if (rst) begin
636 
    rd_pointer <= 0;
637 
  end else if (rd_cs && rd_en ) begin
638 
    rd_pointer <= rd_pointer + 1;
639 
  end
640 
end
641 
 
642 
always  @ (posedge clk or posedge rst)
643 
begin : READ_DATA
644 
  if (rst) begin
645 
    data_out <= 0;
646 
  end else if (rd_cs && rd_en ) begin
647 
    data_out <= data_ram;
648 
  end
649 
end
650 
 
651 
always @ (posedge clk or posedge rst)
652 
begin : STATUS_COUNTER
653 
  if (rst) begin
654 
    status_cnt <= 0;
655 
  // Read but no write.
656 
  end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
657 
                && (status_cnt != 0)) begin
658 
    status_cnt <= status_cnt - 1;
659 
  // Write but no read.
660 
  end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
661 
               && (status_cnt != RAM_DEPTH)) begin
662 
    status_cnt <= status_cnt + 1;
663 
  end
664 
end
665 
 
666 
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
667 
.address_0 (wr_pointer) , // address_0 input
668 
.data_0    (data_in)    , // data_0 bi-directional
669 
.cs_0      (wr_cs)      , // chip select
670 
.we_0      (wr_en)      , // write enable
671 
.oe_0      (1'b0)       , // output enable
672 
.address_1 (rd_pointer) , // address_q input
673 
.data_1    (data_ram)   , // data_1 bi-directional
674 
.cs_1      (rd_cs)      , // chip select
675 
.we_1      (1'b0)       , // Read enable
676 
.oe_1      (rd_en)        // output enable
677 
);
678 
 
679 
endmodule
680 
*/
681 
 
682 
 
683 
 module sync_fifo #(  parameter DATA_WIDTH = 8, parameter DEPTH = 8 )
684 
(
685 
 
686 
 input wire [DATA_WIDTH-1:0]  din,
687 
 input wire wr_en,
688 
 input wire rd_en,
689 
 output wire[DATA_WIDTH-1:0] dout,
690 
 output reg full,
691 
 output reg empty,
692 
 input wire clk,
693 
 input wire reset
694 
 
695 
);
696 
 
697 
 
698 
parameter ADDR_WIDTH = $clog2(DEPTH);
699 
 
700 
reg   [ADDR_WIDTH : 0]     rd_ptr; // note MSB is not really address
701 
reg   [ADDR_WIDTH : 0]     wr_ptr; // note MSB is not really address
702 
wire  [ADDR_WIDTH-1 : 0]  wr_loc;
703 
wire  [ADDR_WIDTH-1 : 0]  rd_loc;
704 
reg   [DATA_WIDTH-1 : 0]  mem[DEPTH-1 : 0];
705 
 
706 
 
707 
assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
708 
assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
709 
 
710 
always @(posedge clk) begin
711 
 if(reset) begin
712 
 wr_ptr <= 'h0;
713 
 rd_ptr <= 'h0;
714 
end // end if
715 
 
716 
else begin
717 
 if(wr_en & (~full))begin
718 
 wr_ptr <= wr_ptr+1;
719 
 end
720 
 if(rd_en & (~empty))
721 
 rd_ptr <= rd_ptr+1;
722 
 end //end else
723 
 
724 
end//end always
725 
 
726 
 
727 
 
728 
//empty if all the bits of rd_ptr and wr_ptr are the same.
729 
 
730 
//full if all bits except the MSB are equal and MSB differes
731 
 
732 
always @(rd_ptr or wr_ptr)begin
733 
 
734 
 //default catch-alls
735 
 
736 
 empty <= 1'b0;
737 
 
738 
 full  <= 1'b0;
739 
 
740 
 if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
741 
 
742 
 if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
743 
 
744 
 empty <= 1'b1;
745 
 
746 
 else
747 
 
748 
 full  <= 1'b1;
749 
 
750 
 end//end if
751 
 
752 
end//end always
753 
 
754 
 
755 
 
756 
always @(posedge clk) begin
757 
 
758 
 if (wr_en)
759 
 
760 
 mem[wr_loc] <= din;
761 
 
762 
end //end always
763 
 
764 
assign dout = mem[rd_loc];//rd_en ? mem[rd_loc]:'h0;
765 
 
766 
endmodule
767 
 
768 
//---------------------------------------------------------------------
769 
 
770 
/*
771 
Synchronous memory blocks have two independent address ports, allowing
772 
for operations on two unique addresses simultaneously. A read operation and a write
773 
operation can share the same port if they share the same address.
774 
In the synchronous RAM block architecture, there is no priority between the two
775 
ports. Therefore, if you write to the same location on both ports at the same time, the
776 
result is indeterminate in the device architecture.
777 
When a read and write operation occurs on the same port for
778 
the same address, the new data being written to the memory is read. When a read and
779 
write operation occurs on different ports for the same address, the old data in the
780 
memory is read. Simultaneous writes to the same location on both ports results in
781 
indeterminate behavior.
782 
 
783 
*/
784 
module RAM_DUAL_READ_DUAL_WRITE_PORT  # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
785 
(
786 
input wire [(DATA_WIDTH-1):0] data_a, data_b,
787 
input wire [(ADDR_WIDTH-1):0] addr_a, addr_b,
788 
input wire we_a, we_b, clk,
789 
output reg [(DATA_WIDTH-1):0] q_a, q_b
790 
);
791 
 
792 
 
793 
// Declare the RAM variable
794 
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
795 
        always @ (posedge clk)
796 
        begin // Port A
797 
                if (we_a)
798 
                begin
799 
                        ram[addr_a] <= data_a;
800 
                        q_a <= data_a;
801 
                end
802 
                else
803 
                        q_a <= ram[addr_a];
804 
        end
805 
 
806 
        always @ (posedge clk)
807 
        begin // Port b
808 
                if (we_b)
809 
                begin
810 
                        ram[addr_b] <= data_b;
811 
                        q_b <= data_b;
812 
                end
813 
                else
814 
                        q_b <= ram[addr_b];
815 
        end
816 
endmodule
817 
 
818 
 
819 
module RAM_QUAD_PORT  # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
820 
(
821 
input wire [(DATA_WIDTH-1):0] data_a, data_b,
822 
input wire [(ADDR_WIDTH-1):0] waddr_a, waddr_b,
823 
input wire [(ADDR_WIDTH-1):0] raddr_a, raddr_b,
824 
input wire we_a, we_b, clk,
825 
output reg [(DATA_WIDTH-1):0] q_a, q_b
826 
);
827 
 
828 
 
829 
// Declare the RAM variable
830 
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
831 
        always @ (posedge clk)
832 
        begin // Port A
833 
                if (we_a)
834 
                begin
835 
                        ram[waddr_a] <= data_a;
836 
                        q_a <= data_a;
837 
                end
838 
                else
839 
                        q_a <= ram[waddr_a];
840 
        end
841 
 
842 
        always @ (posedge clk)
843 
        begin // Port B
844 
                if (we_b)
845 
                begin
846 
                        ram[waddr_b] <= data_b;
847 
                        q_b <= data_b;
848 
                end
849 
                else
850 
                        q_b <= ram[waddr_b];
851 
        end
852 
 
853 
 
854 
endmodule
855 
//-------------------------------------------------------------------------------
856 
//----------------------------------------------------
857 
   // A four level, round-robin arbiter. This was
858 
   // orginally coded by WD Peterson in VHDL.
859 
   //----------------------------------------------------
860 
    module ROUND_ROBIN_ARBITER (
861 
      clk,
862 
      rst,
863 
                req4,
864 
      req3,
865 
      req2,
866 
     req1,
867 
     req0,
868 
          gnt4,
869 
     gnt3,
870 
     gnt2,
871 
     gnt1,
872 
     gnt0
873 
   );
874 
   // --------------Port Declaration-----------------------
875 
   input           clk;
876 
   input           rst;
877 
        input           req4;
878 
   input           req3;
879 
   input           req2;
880 
   input           req1;
881 
   input           req0;
882 
        output          gnt4;
883 
   output          gnt3;
884 
   output          gnt2;
885 
   output          gnt1;
886 
   output          gnt0;
887 
 
888 
   //--------------Internal Registers----------------------
889 
   wire    [2:0]   gnt       ;
890 
   wire            comreq    ;
891 
   wire            beg       ;
892 
   wire   [2:0]    lgnt      ;
893 
   wire            lcomreq   ;
894 
   reg             lgnt0     ;
895 
   reg             lgnt1     ;
896 
   reg             lgnt2     ;
897 
   reg             lgnt3     ;
898 
        reg             lgnt4     ;
899 
   reg             lasmask   ;
900 
   reg             lmask0    ;
901 
   reg             lmask1    ;
902 
        reg             lmask2    ;
903 
   reg             ledge     ;
904 
 
905 
   //--------------Code Starts Here-----------------------
906 
   always @ (posedge clk)
907 
   if (rst) begin
908 
     lgnt0 <= 0;
909 
     lgnt1 <= 0;
910 
     lgnt2 <= 0;
911 
     lgnt3 <= 0;
912 
          lgnt4 <= 0;
913 
   end else begin
914 
     lgnt0 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & ~req3 & ~req2 & ~req1 & req0)
915 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 & ~req4 & ~req3 & ~req2 &  req0)
916 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & ~req3 &  req0)
917 
           | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 & ~req4 & req0  )
918 
                          | (~lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req0  )
919 
           | ( lcomreq & lgnt0 );
920 
     lgnt1 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 &  req1)
921 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 & ~req4 & ~req3 & ~req2 &  req1 & ~req0)
922 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & ~req3 &  req1 & ~req0)
923 
           | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 & ~req4 &  req1 & ~req0)
924 
                          | (~lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req1 & ~req0)
925 
           | ( lcomreq &  lgnt1);
926 
     lgnt2 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 &  req2  & ~req1)
927 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 &  req2)
928 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & ~req3 &  req2  & ~req1 & ~req0)
929 
           | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 & ~req4 & req2 & ~req1 & ~req0)
930 
                          | ( lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req2 & ~req1 & ~req0)
931 
           | ( lcomreq &  lgnt2);
932 
     lgnt3 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3  & ~req2 & ~req1)
933 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 & ~req4 & req3  & ~req2)
934 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & req3)
935 
                          | (~lcomreq & ~lmask2 & ~lmask2 &  lmask1 &  lmask0 &  req3)
936 
           | ( lcomreq &  lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3  & ~req2 & ~req1 & ~req0)
937 
           | ( lcomreq & lgnt3);
938 
          lgnt4 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 &  req4 & ~req3  & ~req2 & ~req1 & ~req0)
939 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 &  req4 & ~req3  & ~req2 & ~req1 )
940 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 &  req4 & ~req3  & ~req2 )
941 
                          | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 &  req4 & ~req3 )
942 
           | ( lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req4 )
943 
           | ( lcomreq & lgnt3);
944 
   end
945 
 
946 
   //----------------------------------------------------
947 
   // lasmask state machine.
948 
   //----------------------------------------------------
949 
   assign beg = (req4 | req3 | req2 | req1 | req0) & ~lcomreq;
950 
   always @ (posedge clk)
951 
   begin
952 
     lasmask <= (beg & ~ledge & ~lasmask);
953 
     ledge   <= (beg & ~ledge &  lasmask)
954 
             |  (beg &  ledge & ~lasmask);
955 
   end
956 
 
957 
   //----------------------------------------------------
958 
   // comreq logic.
959 
   //----------------------------------------------------
960 
   assign lcomreq =
961 
                                                        ( req4 & lgnt4 )
962 
                                                 | ( req3 & lgnt3 )
963 
                   | ( req2 & lgnt2 )
964 
                   | ( req1 & lgnt1 )
965 
                   | ( req0 & lgnt0 );
966 
 
967 
   //----------------------------------------------------
968 
   // Encoder logic.
969 
   //----------------------------------------------------
970 
   assign  lgnt =  {lgnt4,(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
971 
 
972 
   //----------------------------------------------------
973 
   // lmask register.
974 
  //----------------------------------------------------
975 
  always @ (posedge clk )
976 
  if( rst ) begin
977 
         lmask2 <= 0;
978 
    lmask1 <= 0;
979 
    lmask0 <= 0;
980 
  end else if(lasmask) begin
981 
    lmask2 <= lgnt[2];
982 
    lmask1 <= lgnt[1];
983 
    lmask0 <= lgnt[0];
984 
  end else begin
985 
         lmask2 <= lmask2;
986 
    lmask1 <= lmask1;
987 
    lmask0 <= lmask0;
988 
  end
989 
 
990 
  assign comreq = lcomreq;
991 
  assign gnt    = lgnt;
992 
  //----------------------------------------------------
993 
  // Drive the outputs
994 
  //----------------------------------------------------
995 
  assign gnt4   = lgnt4;
996 
  assign gnt3   = lgnt3;
997 
  assign gnt2   = lgnt2;
998 
  assign gnt1   = lgnt1;
999 
  assign gnt0   = lgnt0;
1000 
 
1001 
  endmodule
1002 
//-------------------------------------------------------------------------------
1003 
module ROUND_ROBIN_5_ENTRIES
1004 
(
1005 
input wire Clock,
1006 
input wire Reset,
1007 
input wire iRequest0,
1008 
input wire iRequest1,
1009 
input wire iRequest2,
1010 
input wire iRequest3,
1011 
input wire iRequest4,
1012 
output wire oGrant0,
1013 
output wire oGrant1,
1014 
output wire oGrant2,
1015 
output wire oGrant3,
1016 
output wire oGrant4,
1017 
output wire oPriorityGrant
1018 
 
1019 
);
1020 
wire wMaks2,wMaks1,wMaks0;
1021 
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4;
1022 
 
1023 
assign wGrant0 =
1024 
                   (wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest0 &  ~iRequest4 )
1025 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest4 & ~iRequest3 )
1026 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest4 & ~iRequest3 & ~iRequest2 )
1027 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1028 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 );
1029 
 
1030 
 
1031 
assign wGrant1 =
1032 
                   (wMaks2 &  ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest4)
1033 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest4 & ~iRequest3 )
1034 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest4 & ~iRequest3 & ~iRequest2 )
1035 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 )
1036 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0);
1037 
 
1038 
assign wGrant2 =
1039 
                   (wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest4 )
1040 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest4 & ~iRequest3 )
1041 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 )
1042 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 )
1043 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 );
1044 
 
1045 
assign wGrant3 =
1046 
                   (wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest4 )
1047 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest3 )
1048 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 )
1049 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 )
1050 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1051 
 
1052 
assign wGrant4 =
1053 
                   ( wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest4 )
1054 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest4 & ~iRequest3 )
1055 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 )
1056 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1057 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1058 
 
1059 
 
1060 
assign oPriorityGrant = wGrant0;
1061 
 
1062 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
1063 
(       Clock, Reset, 1'b1 , wGrant0, oGrant0);
1064 
 
1065 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
1066 
(       Clock, Reset, 1'b1 , wGrant1,  oGrant1 );
1067 
 
1068 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
1069 
(       Clock, Reset, 1'b1 , wGrant2, oGrant2 );
1070 
 
1071 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
1072 
(       Clock, Reset, 1'b1 , wGrant3, oGrant3 );
1073 
 
1074 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
1075 
(       Clock, Reset, 1'b1 , wGrant4, oGrant4 );
1076 
 
1077 
 
1078 
 
1079 
 
1080 
reg [4:0]  rCurrentState, rNextState;
1081 
//Next states logic and Reset sequence
1082 
always @(posedge Clock )
1083 
  begin
1084 
 
1085 
    if (Reset )
1086 
                rCurrentState <= 0;
1087 
    else
1088 
                rCurrentState <= rNextState;
1089 
 
1090 
end
1091 
reg[2:0] rMask;
1092 
 
1093 
assign wMaks0 = rMask[0];
1094 
assign wMaks1 = rMask[1];
1095 
assign wMaks2 = rMask[2];
1096 
 
1097 
always @ ( * )
1098 
begin
1099 
        case (rCurrentState)
1100 
        //--------------------------------------
1101 
        0:
1102 
        begin
1103 
                rMask = 3'd0;
1104 
                rNextState = 1;
1105 
        end
1106 
        1:
1107 
        begin
1108 
                rMask = 3'd1;
1109 
                rNextState = 2;
1110 
        end
1111 
        2:
1112 
        begin
1113 
                rMask = 3'd2;
1114 
                rNextState = 3;
1115 
        end
1116 
        3:
1117 
        begin
1118 
                rMask = 3'd3;
1119 
                rNextState = 4;
1120 
        end
1121 
        4:
1122 
        begin
1123 
                rMask = 3'd4;
1124 
                rNextState = 0;
1125 
        end
1126 
        endcase
1127 
end
1128 
        /*
1129 
UPCOUNTER_POSEDGE # (3) UP1
1130 
(
1131 
.Clock( Clock ),
1132 
.Reset( Reset ),
1133 
.Initial( 3'b0 ),
1134 
.Enable( 1'b1 ),
1135 
.Q({wMaks2,wMaks1,wMaks0})
1136 
);
1137 
*/
1138 
 
1139 
 
1140 
endmodule
1141 
//-------------------------------------------------------------------------------
1142 
module ROUND_ROBIN_6_ENTRIES
1143 
(
1144 
input wire Clock,
1145 
input wire Reset,
1146 
input wire iRequest0,
1147 
input wire iRequest1,
1148 
input wire iRequest2,
1149 
input wire iRequest3,
1150 
input wire iRequest4,
1151 
input wire iRequest5,
1152 
output wire oGrant0,
1153 
output wire oGrant1,
1154 
output wire oGrant2,
1155 
output wire oGrant3,
1156 
output wire oGrant4,
1157 
output wire oGrant5,
1158 
output wire oPriorityGrant
1159 
 
1160 
);
1161 
wire wMaks2,wMaks1,wMaks0;
1162 
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5;
1163 
 
1164 
assign wGrant0 =
1165 
                   (wMaks2 &  ~wMaks1 &  wMaks0 & iRequest0 &  ~iRequest5 )
1166 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 )
1167 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 )
1168 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1169 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
1170 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 );
1171 
 
1172 
 
1173 
assign wGrant1 =
1174 
                   (wMaks2 &  ~wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5)
1175 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 )
1176 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 )
1177 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
1178 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 )
1179 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0);
1180 
 
1181 
assign wGrant2 =
1182 
                   (wMaks2 &  ~wMaks1 &   wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 )
1183 
                                                |( wMaks2 & ~wMaks1 &  ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 )
1184 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3)
1185 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 )
1186 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 )
1187 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 );
1188 
 
1189 
assign wGrant3 =
1190 
                                                 ( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 )
1191 
                  |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4)
1192 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest3 )
1193 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 )
1194 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 )
1195 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1196 
 
1197 
assign wGrant4 =
1198 
                   ( wMaks2 &  ~wMaks1 &  wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5)
1199 
                                                |( wMaks2 &  ~wMaks1 & ~wMaks0 &  iRequest4  )
1200 
                                                |(~wMaks2 &  wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3  )
1201 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2   )
1202 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1  )
1203 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1204 
 
1205 
assign wGrant5 =
1206 
                  ( wMaks2 &  ~wMaks1 &   wMaks0 & iRequest5 )
1207 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 )
1208 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 )
1209 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1210 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1211 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1212 
 
1213 
 
1214 
assign oPriorityGrant = wGrant0;
1215 
 
1216 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
1217 
(       Clock, Reset, 1'b1 , wGrant0, oGrant0);
1218 
 
1219 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
1220 
(       Clock, Reset, 1'b1 , wGrant1,  oGrant1 );
1221 
 
1222 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
1223 
(       Clock, Reset, 1'b1 , wGrant2, oGrant2 );
1224 
 
1225 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
1226 
(       Clock, Reset, 1'b1 , wGrant3, oGrant3 );
1227 
 
1228 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
1229 
(       Clock, Reset, 1'b1 , wGrant4, oGrant4 );
1230 
 
1231 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
1232 
(       Clock, Reset, 1'b1 , wGrant5, oGrant5 );
1233 
 
1234 
 
1235 
reg [4:0]  rCurrentState, rNextState;
1236 
//Next states logic and Reset sequence
1237 
always @(posedge Clock )
1238 
  begin
1239 
 
1240 
    if (Reset )
1241 
                rCurrentState <= 0;
1242 
    else
1243 
                rCurrentState <= rNextState;
1244 
 
1245 
end
1246 
reg[2:0] rMask;
1247 
 
1248 
assign wMaks0 = rMask[0];
1249 
assign wMaks1 = rMask[1];
1250 
assign wMaks2 = rMask[2];
1251 
 
1252 
always @ ( * )
1253 
begin
1254 
        case (rCurrentState)
1255 
        //--------------------------------------
1256 
        0:
1257 
        begin
1258 
                rMask = 3'd0;
1259 
                rNextState = 1;
1260 
        end
1261 
        1:
1262 
        begin
1263 
                rMask = 3'd1;
1264 
                rNextState = 2;
1265 
        end
1266 
        2:
1267 
        begin
1268 
                rMask = 3'd2;
1269 
                rNextState = 3;
1270 
        end
1271 
        3:
1272 
        begin
1273 
                rMask = 3'd3;
1274 
                rNextState = 4;
1275 
        end
1276 
        4:
1277 
        begin
1278 
                rMask = 3'd4;
1279 
                rNextState = 5;
1280 
        end
1281 
        5:
1282 
        begin
1283 
                rMask = 3'd5;
1284 
                rNextState = 0;
1285 
        end
1286 
        endcase
1287 
end
1288 
        /*
1289 
UPCOUNTER_POSEDGE # (3) UP1
1290 
(
1291 
.Clock( Clock ),
1292 
.Reset( Reset ),
1293 
.Initial( 3'b0 ),
1294 
.Enable( 1'b1 ),
1295 
.Q({wMaks2,wMaks1,wMaks0})
1296 
);
1297 
*/
1298 
 
1299 
 
1300 
endmodule
1301 
//-------------------------------------------------------------------------------
1302 
//-------------------------------------------------------------------------------
1303 
module ROUND_ROBIN_7_ENTRIES
1304 
(
1305 
input wire Clock,
1306 
input wire Reset,
1307 
input wire iRequest0,
1308 
input wire iRequest1,
1309 
input wire iRequest2,
1310 
input wire iRequest3,
1311 
input wire iRequest4,
1312 
input wire iRequest5,
1313 
input wire iRequest6,
1314 
output wire oGrant0,
1315 
output wire oGrant1,
1316 
output wire oGrant2,
1317 
output wire oGrant3,
1318 
output wire oGrant4,
1319 
output wire oGrant5,
1320 
output wire oGrant6,
1321 
output wire oPriorityGrant
1322 
 
1323 
);
1324 
wire wMaks2,wMaks1,wMaks0;
1325 
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5,wGrant6;
1326 
 
1327 
assign wGrant0 =
1328 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest6 )
1329 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 )
1330 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 )
1331 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
1332 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
1333 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
1334 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 );
1335 
 
1336 
 
1337 
assign wGrant1 =
1338 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6)
1339 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 )
1340 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 )
1341 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
1342 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
1343 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 )
1344 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0);
1345 
 
1346 
assign wGrant2 =
1347 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 )
1348 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 )
1349 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4)
1350 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
1351 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 )
1352 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 )
1353 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 );
1354 
 
1355 
assign wGrant3 =
1356 
                                                 ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 )
1357 
                  |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5)
1358 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4)
1359 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest3 )
1360 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 )
1361 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 )
1362 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1363 
 
1364 
assign wGrant4 =
1365 
                   ( wMaks2 &   wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6)
1366 
                                                |( wMaks2 &  ~wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
1367 
                                                |( wMaks2 &  ~wMaks1 & ~wMaks0  &  iRequest4  )
1368 
                                                |(~wMaks2 &   wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3  )
1369 
                                                |(~wMaks2 &   wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2   )
1370 
                                                |(~wMaks2 &  ~wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1  )
1371 
                                                |(~wMaks2 &  ~wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1372 
 
1373 
assign wGrant5 =
1374 
                  (  wMaks2 &  wMaks1 & ~wMaks0  &  iRequest5 & ~iRequest4 )
1375 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest5 )
1376 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 )
1377 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1378 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1379 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 )
1380 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6);
1381 
 
1382 
assign wGrant6 =
1383 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest6 )
1384 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest6 & ~iRequest5 )
1385 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 )
1386 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
1387 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1388 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1389 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1390 
 
1391 
 
1392 
assign oPriorityGrant = wGrant0;
1393 
 
1394 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
1395 
(       Clock, Reset, 1'b1 , wGrant0, oGrant0);
1396 
 
1397 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
1398 
(       Clock, Reset, 1'b1 , wGrant1,  oGrant1 );
1399 
 
1400 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
1401 
(       Clock, Reset, 1'b1 , wGrant2, oGrant2 );
1402 
 
1403 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
1404 
(       Clock, Reset, 1'b1 , wGrant3, oGrant3 );
1405 
 
1406 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
1407 
(       Clock, Reset, 1'b1 , wGrant4, oGrant4 );
1408 
 
1409 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
1410 
(       Clock, Reset, 1'b1 , wGrant5, oGrant5 );
1411 
 
1412 
 
1413 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD6
1414 
(       Clock, Reset, 1'b1 , wGrant6, oGrant6 );
1415 
 
1416 
 
1417 
reg [4:0]  rCurrentState, rNextState;
1418 
//Next states logic and Reset sequence
1419 
always @(posedge Clock )
1420 
  begin
1421 
 
1422 
    if (Reset )
1423 
                rCurrentState <= 0;
1424 
    else
1425 
                rCurrentState <= rNextState;
1426 
 
1427 
end
1428 
reg[2:0] rMask;
1429 
 
1430 
assign wMaks0 = rMask[0];
1431 
assign wMaks1 = rMask[1];
1432 
assign wMaks2 = rMask[2];
1433 
 
1434 
always @ ( * )
1435 
begin
1436 
        case (rCurrentState)
1437 
        //--------------------------------------
1438 
        0:
1439 
        begin
1440 
                rMask = 3'd0;
1441 
                rNextState = 1;
1442 
        end
1443 
        1:
1444 
        begin
1445 
                rMask = 3'd1;
1446 
                rNextState = 2;
1447 
        end
1448 
        2:
1449 
        begin
1450 
                rMask = 3'd2;
1451 
                rNextState = 3;
1452 
        end
1453 
        3:
1454 
        begin
1455 
                rMask = 3'd3;
1456 
                rNextState = 4;
1457 
        end
1458 
        4:
1459 
        begin
1460 
                rMask = 3'd4;
1461 
                rNextState = 5;
1462 
        end
1463 
        5:
1464 
        begin
1465 
                rMask = 3'd5;
1466 
                rNextState = 6;
1467 
        end
1468 
        6:
1469 
        begin
1470 
                rMask = 3'd6;
1471 
                rNextState = 0;
1472 
        end
1473 
        endcase
1474 
end
1475 
 
1476 
 
1477 
endmodule
1478 
`endif

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