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1 213 diegovalve 
`ifndef COLLATERALS_V
2 
`define COLLATERALS_V
3 
 
4 
`timescale 1ns / 1ps
5 
`include "aDefinitions.v"
6 
/**********************************************************************************
7 
Theia, Ray Cast Programable graphic Processing Unit.
8 
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
9 
 
10 
This program is free software; you can redistribute it and/or
11 
modify it under the terms of the GNU General Public License
12 
as published by the Free Software Foundation; either version 2
13 
of the License, or (at your option) any later version.
14 
 
15 
This program is distributed in the hope that it will be useful,
16 
but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 
GNU General Public License for more details.
19 
 
20 
You should have received a copy of the GNU General Public License
21 
along with this program; if not, write to the Free Software
22 
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
23 
 
24 
***********************************************************************************/
25 
 
26 
//----------------------------------------------------
27 
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
28 
(
29 
        input wire                              Clock,
30 
        input wire                              Reset,
31 
        input wire                              Enable,
32 
        input wire [SIZE-1:0]    D,
33 
        output reg [SIZE-1:0]    Q
34 
);
35 
 
36 
 
37 
always @ (posedge Clock)
38 
begin
39 
        if ( Reset )
40 
                Q <= {SIZE{1'b0}};
41 
        else
42 
        begin
43 
                if (Enable)
44 
                        Q <= D;
45 
        end
46 
 
47 
end//always
48 
 
49 
endmodule
50 230 diegovalve 
//------------------------------------------------
51 
module PULSE
52 
(
53 213 diegovalve 
input wire                              Clock,
54 
input wire                              Reset,
55 
input wire                              Enable,
56 
input wire              D,
57 230 diegovalve 
output wire          Q
58 
);
59 
 
60 
wire wDelay;
61 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD (Clock,Reset,Enable,D,wDelay);
62 
 
63 
assign Q = (Enable) ?  (D ^ wDelay) & D: 1'b0;
64 
 
65 
endmodule
66 213 diegovalve 
//------------------------------------------------
67 230 diegovalve 
module ADDER # (parameter SIZE=`WIDTH)
68 
(
69 
input wire Clock,
70 
input wire Reset,
71 
input wire iTrigger,
72 
input wire [SIZE-1:0] iA,iB,
73 
output wire [SIZE-1:0] oR,
74 
output wire            oDone
75 
);
76 
wire [SIZE-1:0] wR,wR_Delay;
77 
assign wR = iA + iB;
78 
 
79 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
80 
 
81 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
82 
assign oR = wR_Delay;
83 
 
84 
endmodule
85 
//------------------------------------------------
86 
module OR # (parameter SIZE=`WIDTH)
87 
(
88 
input wire Clock,
89 
input wire Reset,
90 
input wire iTrigger,
91 
input wire [SIZE-1:0] iA,iB,
92 
output wire [SIZE-1:0] oR,
93 
output wire            oDone
94 
);
95 
wire [SIZE-1:0] wR,wR_Delay;
96 
assign wR = iA | iB;
97 
 
98 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
99 
 
100 
 
101 
FFD_POSEDGE_SYNCRONOUS_RESET #  (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
102 
assign oR = wR_Delay;
103 
 
104 
endmodule
105 
//------------------------------------------------
106 
module AND # (parameter SIZE=`WIDTH)
107 
(
108 
input wire Clock,
109 
input wire Reset,
110 
input wire iTrigger,
111 
input wire [SIZE-1:0] iA,iB,
112 
output wire [SIZE-1:0] oR,
113 
output wire            oDone
114 
);
115 
wire [SIZE-1:0] wR,wR_Delay;
116 
assign wR = iA & iB;
117 
 
118 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
119 
 
120 
 
121 
FFD_POSEDGE_SYNCRONOUS_RESET #  (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
122 
assign oR = wR_Delay;
123 
 
124 
endmodule
125 
//------------------------------------------------
126 213 diegovalve 
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
127 
(
128 
input wire Clock, Reset,
129 230 diegovalve 
input wire [SIZE-1:0] Initial,
130 
input wire Enable,
131 213 diegovalve 
output reg [SIZE-1:0] Q
132 
);
133 
 
134 
 
135 
  always @(posedge Clock )
136 
  begin
137 
      if (Reset)
138 
        Q <= Initial;
139 230 diegovalve 
      else
140 
                begin
141 213 diegovalve 
                if (Enable)
142 230 diegovalve 
                        Q <= Q + 1;
143 
 
144 213 diegovalve 
                end
145 
  end
146 
 
147 
endmodule
148 230 diegovalve 
 
149 
//----------------------------------------------------------------------
150 
 
151 
module DECODER_ONEHOT_2_BINARY # (parameter OUTPUT_WIDTH = 6)
152 
(
153 
input wire [6:0] iIn,
154 
output reg[OUTPUT_WIDTH-1:0] oOut
155 
);
156 
 
157 
always @ (*)
158 
begin
159 
        case (iIn)
160 
                7'b0000000: oOut = 0;
161 
                7'b0000001: oOut = 1;
162 
                7'b0000010: oOut = 2;
163 
                7'b0000100: oOut = 3;
164 
                7'b0001000: oOut = 4;
165 
                7'b0010000: oOut = 5;
166 
                7'b0100000: oOut = 6;
167 
                7'b1000000: oOut = 7;
168 
        default:
169 
                oOut = 0;
170 
        endcase
171 
end
172 
endmodule
173 
 
174 
//----------------------------------------------------------------------
175 
 
176 213 diegovalve 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
177 
 (
178 
 input wire [SEL_WIDTH-1:0] Sel,
179 
 input wire  En,
180 
 output wire [OUTPUT_WIDTH-1:0] O
181 
 );
182 
 
183 230 diegovalve 
reg[OUTPUT_WIDTH-1:0] shift;
184 
 
185 
always @ ( * )
186 
begin
187 
        if (~En)
188 
                shift = 1;
189 
        else
190 
                shift = (1 <<   Sel);
191 
 
192 
 
193 
end
194 
 
195 
assign O = ( ~En ) ? 0 : shift ;
196 
 
197 
//assign O = En & (1 << Sel);
198 
 
199 
endmodule
200 
 
201 
//----------------------------------------------------------------------
202 
module MUXFULLPARALELL_GENERIC #(parameter  WIDTH = `WIDTH, parameter  CHANNELS = 4, parameter SELBITS = 2)
203 213 diegovalve 
(
204 
 
205 
    input wire   [(CHANNELS*WIDTH)-1:0]      in_bus,
206 
    input wire   [SELBITS-1:0]    sel,
207 
 
208 
    output wire [WIDTH-1:0]                 out
209 
    );
210 
 
211 
genvar ig;
212 
 
213 
wire    [WIDTH-1:0] input_array [0:CHANNELS-1];
214 
 
215 
assign  out = input_array[sel];
216 
 
217 
generate
218 230 diegovalve 
    for(ig=0; ig<CHANNELS; ig=ig+1)
219 213 diegovalve 
         begin: array_assignments
220 
        assign  input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
221 
    end
222 
endgenerate
223 
 
224 
 
225 
 
226 
endmodule
227 
//----------------------------------------------------------------------
228 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
229 
 (
230 
 input wire [1:0] Sel,
231 
 input wire [SIZE-1:0]I1, I2, I3,I4,
232 
 output reg [SIZE-1:0] O1
233 
 );
234 
 
235 
always @( * )
236 
 
237 
  begin
238 
 
239 
    case (Sel)
240 
 
241 
      2'b00: O1 = I1;
242 
      2'b01: O1 = I2;
243 230 diegovalve 
                2'b10: O1 = I3;
244 213 diegovalve 
                2'b11: O1 = I4;
245 
                default: O1 = SIZE;
246 
 
247 
    endcase
248 
 
249 
  end
250 
 
251 230 diegovalve 
endmodule
252 213 diegovalve 
//------------------------------------------------------------------------
253 
module MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )
254 
 (
255 
 input wire [2:0] Sel,
256 
 input wire [SIZE-1:0]I1, I2, I3,I4,I5,I6,I7,I8,
257 
 output reg [SIZE-1:0] O1
258 
 );
259 
 
260 
always @( * )
261 
 
262 
  begin
263 
 
264 
    case (Sel)
265 
 
266 
      3'b000: O1 = I1;
267 
      3'b001: O1 = I2;
268 230 diegovalve 
                3'b010: O1 = I3;
269 
                3'b011: O1 = I4;
270 
                3'b100: O1 = I5;
271 
                3'b101: O1 = I6;
272 
                3'b110: O1 = I7;
273 213 diegovalve 
                3'b111: O1 = I8;
274 
                default: O1 = SIZE;
275 
 
276 
    endcase
277 
 
278 
  end
279 
 
280 
endmodule
281 230 diegovalve 
//------------------------------------------------------------------------
282 213 diegovalve 
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
283 
( input wire Clock,
284 
  input wire Reset,
285 
  input wire[SIZE-1:0] Initial,
286 230 diegovalve 
  input wire      Enable,
287 213 diegovalve 
  output wire[SIZE-1:0] O
288 
);
289 
 
290 
reg [SIZE-1:0] tmp;
291 
 
292 
 
293 
  always @(posedge Clock)
294 
  begin
295 
  if (Reset)
296 
                tmp <= Initial;
297 
        else
298 
        begin
299 230 diegovalve 
                if (Enable)
300 
                begin
301 
                        if (tmp[SIZE-1])
302 213 diegovalve 
                        begin
303 230 diegovalve 
                                tmp <= Initial;
304 
                        end
305 
                        else
306 
                        begin
307 
                                tmp <= tmp << 1;
308 
                        end
309 213 diegovalve 
                end
310 
        end
311 
  end
312 
 
313 
 
314 
    assign O  = tmp;
315 
endmodule
316 
//------------------------------------------------
317 
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
318 
 (
319 
 input wire [2:0] Sel,
320 
 input wire [SIZE-1:0]I1, I2, I3,
321 
 output reg [SIZE-1:0] O1
322 
 );
323 
 
324 
always @( * )
325 
 
326 
  begin
327 
 
328 
    case (Sel)
329 
 
330 
      3'b001: O1 = I1;
331 
      3'b010: O1 = I2;
332 
      3'b100: O1 = I3;
333 
      default: O1 = SIZE;
334 
 
335 
    endcase
336 
 
337 
  end
338 
 
339 230 diegovalve 
endmodule
340 213 diegovalve 
//------------------------------------------------
341 
module MUXFULLPARALELL_3SEL_EN # ( parameter SIZE=`WIDTH )
342 
 (
343 
 input wire [1:0] SEL,
344 230 diegovalve 
 input wire [SIZE-1:0]I1, I2, I3,
345 213 diegovalve 
 input wire EN,
346 
 output reg [SIZE-1:0] O1
347 
 );
348 
 
349 
always @( * )
350 
 
351 
  begin
352 230 diegovalve 
        if (EN)
353 213 diegovalve 
        begin
354 
    case (SEL)
355 
 
356 
      2'b00: O1 = I1;
357 
      2'b01: O1 = I2;
358 
      2'b10: O1 = I3;
359 
      default: O1 = SIZE;
360 
 
361 
    endcase
362 
        end
363 230 diegovalve 
        else
364 
        begin
365 
                O1 = I1;
366 
        end
367 213 diegovalve 
  end
368 
 
369 230 diegovalve 
endmodule
370 213 diegovalve 
//------------------------------------------------
371 
module MUXFULLPARALELL_4SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
372 
 (
373 
 input wire [2:0] Sel,
374 
 input wire [SIZE-1:0]I1, I2, I3, I4,
375 
 output reg [SIZE-1:0] O1
376 
 );
377 
 
378 
always @( * )
379 
 
380 
  begin
381 
 
382 
    case (Sel)
383 
 
384 
      4'b0001: O1 = I1;
385 
      4'b0010: O1 = I2;
386 230 diegovalve 
      4'b0100: O1 = I3;
387 213 diegovalve 
                4'b1000: O1 = I4;
388 
      default: O1 = SIZE;
389 
 
390 
    endcase
391 
 
392 
  end
393 
 
394 
endmodule
395 
//------------------------------------------------
396 
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
397 
( input wire Clock,
398 
  input wire Reset,
399 
  input wire[SIZE-1:0] Initial,
400 
  input wire      Enable,
401 
  output wire[SIZE-1:0] O
402 
);
403 
 
404 
reg [SIZE-1:0] tmp;
405 
 
406 
 
407 
  always @(posedge Clock)
408 
  begin
409 
  if (Reset)
410 
                tmp <= Initial;
411 
        else
412 
        begin
413 
                if (Enable)
414 
                        tmp <= tmp << 1;
415 
        end
416 
  end
417 
 
418 
 
419 
    assign O  = tmp;
420 
endmodule
421 
//------------------------------------------------
422 
//------------------------------------------------
423 
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
424 
( input wire Clock,
425 
  input wire Reset,
426 
  input wire[SIZE-1:0] Initial,
427 
  input wire      Enable,
428 
  output wire[SIZE-1:0] O
429 
);
430 
 
431 
reg [SIZE-1:0] tmp;
432 
 
433 
 
434 
  always @(posedge Clock)
435 
  begin
436 
  if (Reset || tmp[SIZE-1])
437 
                tmp <= Initial;
438 
        else
439 
        begin
440 
                if (Enable)
441 
                        tmp <= tmp << 1;
442 
        end
443 
  end
444 
 
445 
 
446 
    assign O  = tmp;
447 
endmodule
448 
//-----------------------------------------------------------
449 
/*
450 
        Sorry forgot how this flop is called.
451 
        Any way Truth table is this
452 
 
453 
        Q       S       Q_next R
454 
 
455 
 
456 
        1       0        1                0
457 
        1       1       1                0
458 
        X       X       0                 1
459 
 
460 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
461 
        gets another S = 1, it keeps the output to 1.
462 
*/
463 
module FFToggleOnce_1Bit
464 
(
465 
        input wire Clock,
466 
        input wire Reset,
467 
        input wire Enable,
468 
        input wire S,
469 
        output reg Q
470 
 
471 
);
472 
 
473 
 
474 
reg Q_next;
475 
 
476 
always @ (negedge Clock)
477 
begin
478 
        Q <= Q_next;
479 
end
480 
 
481 
always @ ( posedge Clock )
482 
begin
483 
        if (Reset)
484 
                Q_next <= 0;
485 
        else if (Enable)
486 
                Q_next <= (S && !Q) || Q;
487 
        else
488 
                Q_next <= Q;
489 
end
490 
endmodule
491 
 
492 
//-----------------------------------------------------------
493 
 
494 
 
495 
module FFD32_POSEDGE
496 
(
497 
        input wire Clock,
498 
        input wire[31:0] D,
499 
        output reg[31:0] Q
500 
);
501 
 
502 
        always @ (posedge Clock)
503 
                Q <= D;
504 
 
505 
endmodule
506 
 
507 
//------------------------------------------------
508 
module MUXFULLPARALELL_96bits_2SEL
509 
 (
510 
 input wire Sel,
511 
 input wire [95:0]I1, I2,
512 
 output reg [95:0] O1
513 
 );
514 
 
515 
 
516 
 
517 
always @( * )
518 
 
519 
  begin
520 
 
521 
    case (Sel)
522 
 
523 
      1'b0: O1 = I1;
524 
      1'b1: O1 = I2;
525 
 
526 
    endcase
527 
 
528 
  end
529 
 
530 
endmodule
531 
 
532 
//------------------------------------------------
533 
module MUXFULLPARALELL_16bits_2SEL
534 
 (
535 
 input wire Sel,
536 
 input wire [15:0]I1, I2,
537 
 output reg [15:0] O1
538 
 );
539 
 
540 
 
541 
 
542 
always @( * )
543 
 
544 
  begin
545 
 
546 
    case (Sel)
547 
 
548 
      1'b0: O1 = I1;
549 
      1'b1: O1 = I2;
550 
 
551 
    endcase
552 
 
553 
  end
554 
 
555 
endmodule
556 
 
557 
//--------------------------------------------------------------
558 
 
559 
  module FFT1
560 
  (
561 
   input wire D,
562 
   input wire Clock,
563 
   input wire Reset ,
564 
   output reg Q
565 
 );
566 
 
567 
  always @ ( posedge Clock or posedge Reset )
568 
  begin
569 
 
570 
        if (Reset)
571 
        begin
572 
    Q <= 1'b0;
573 
   end
574 
        else
575 
        begin
576 
                if (D)
577 
                        Q <=  ! Q;
578 
        end
579 
 
580 
  end//always
581 
 
582 
 endmodule
583 
//--------------------------------------------------------------
584 
/*
585 230 diegovalve 
module FIFO_SYNCHRNOUS_RESET # ( parameter SIZE=`WIDTH, parameter DEPTH=16 )
586 213 diegovalve 
(
587 
input wire Clock,
588 
input wire Reset,
589 
wr_cs    , // Write chip select
590 
rd_cs    , // Read chipe select
591 
input wire            iData,
592 
input wire            iReadEnable,
593 
input wire[SIZE-1:0]  iWriteEnable,
594 
output reg[SIZE-1:0]  oData,
595 
output wire           oEmpy,
596 
output wire           oFull
597 
);
598 
 
599 
// FIFO constants
600 
parameter DATA_WIDTH = 8;
601 
parameter ADDR_WIDTH = 8;
602 
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
603 
// Port Declarations
604 
input clk ;
605 
input rst ;
606 
input wr_cs ;
607 
input rd_cs ;
608 
input rd_en ;
609 
input wr_en ;
610 
input [DATA_WIDTH-1:0] data_in ;
611 
output full ;
612 
output empty ;
613 
output [DATA_WIDTH-1:0] data_out ;
614 
 
615 
//-----------Internal variables-------------------
616 
reg [ADDR_WIDTH-1:0] wr_pointer;
617 
reg [ADDR_WIDTH-1:0] rd_pointer;
618 
reg [ADDR_WIDTH :0] status_cnt;
619 
reg [DATA_WIDTH-1:0] data_out ;
620 
wire [DATA_WIDTH-1:0] data_ram ;
621 
 
622 
//-----------Variable assignments---------------
623 
assign full = (status_cnt == (RAM_DEPTH-1));
624 
assign empty = (status_cnt == 0);
625 
 
626 
//-----------Code Start---------------------------
627 
always @ (posedge clk or posedge rst)
628 
begin : WRITE_POINTER
629 
  if (rst) begin
630 
    wr_pointer <= 0;
631 
  end else if (wr_cs && wr_en ) begin
632 
    wr_pointer <= wr_pointer + 1;
633 
  end
634 
end
635 
 
636 
always @ (posedge clk or posedge rst)
637 
begin : READ_POINTER
638 
  if (rst) begin
639 
    rd_pointer <= 0;
640 
  end else if (rd_cs && rd_en ) begin
641 
    rd_pointer <= rd_pointer + 1;
642 
  end
643 
end
644 
 
645 
always  @ (posedge clk or posedge rst)
646 
begin : READ_DATA
647 
  if (rst) begin
648 
    data_out <= 0;
649 
  end else if (rd_cs && rd_en ) begin
650 
    data_out <= data_ram;
651 
  end
652 
end
653 
 
654 
always @ (posedge clk or posedge rst)
655 
begin : STATUS_COUNTER
656 
  if (rst) begin
657 
    status_cnt <= 0;
658 
  // Read but no write.
659 
  end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
660 
                && (status_cnt != 0)) begin
661 
    status_cnt <= status_cnt - 1;
662 
  // Write but no read.
663 
  end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
664 
               && (status_cnt != RAM_DEPTH)) begin
665 
    status_cnt <= status_cnt + 1;
666 
  end
667 
end
668 
 
669 
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
670 
.address_0 (wr_pointer) , // address_0 input
671 
.data_0    (data_in)    , // data_0 bi-directional
672 
.cs_0      (wr_cs)      , // chip select
673 
.we_0      (wr_en)      , // write enable
674 
.oe_0      (1'b0)       , // output enable
675 
.address_1 (rd_pointer) , // address_q input
676 
.data_1    (data_ram)   , // data_1 bi-directional
677 
.cs_1      (rd_cs)      , // chip select
678 
.we_1      (1'b0)       , // Read enable
679 
.oe_1      (rd_en)        // output enable
680 
);
681 
 
682 230 diegovalve 
endmodule
683 
*/
684 
 
685 
 
686 213 diegovalve 
 module sync_fifo #(  parameter DATA_WIDTH = 8, parameter DEPTH = 8 )
687 
(
688 
 
689 
 input wire [DATA_WIDTH-1:0]  din,
690 
 input wire wr_en,
691 
 input wire rd_en,
692 
 output wire[DATA_WIDTH-1:0] dout,
693 
 output reg full,
694 
 output reg empty,
695 
 input wire clk,
696 
 input wire reset
697 
 
698 
);
699 
 
700 230 diegovalve 
 
701 
parameter ADDR_WIDTH = $clog2(DEPTH);
702 213 diegovalve 
 
703 
reg   [ADDR_WIDTH : 0]     rd_ptr; // note MSB is not really address
704 
reg   [ADDR_WIDTH : 0]     wr_ptr; // note MSB is not really address
705 
wire  [ADDR_WIDTH-1 : 0]  wr_loc;
706 
wire  [ADDR_WIDTH-1 : 0]  rd_loc;
707 
reg   [DATA_WIDTH-1 : 0]  mem[DEPTH-1 : 0];
708 
 
709 
 
710 
assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
711 
assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
712 
 
713 
always @(posedge clk) begin
714 
 if(reset) begin
715 
 wr_ptr <= 'h0;
716 
 rd_ptr <= 'h0;
717 
end // end if
718 
 
719 
else begin
720 
 if(wr_en & (~full))begin
721 
 wr_ptr <= wr_ptr+1;
722 
 end
723 
 if(rd_en & (~empty))
724 
 rd_ptr <= rd_ptr+1;
725 
 end //end else
726 
 
727 
end//end always
728 
 
729 
 
730 
 
731 
//empty if all the bits of rd_ptr and wr_ptr are the same.
732 
 
733 
//full if all bits except the MSB are equal and MSB differes
734 
 
735 
always @(rd_ptr or wr_ptr)begin
736 
 
737 
 //default catch-alls
738 
 
739 
 empty <= 1'b0;
740 
 
741 
 full  <= 1'b0;
742 
 
743 
 if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
744 
 
745 
 if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
746 
 
747 
 empty <= 1'b1;
748 
 
749 
 else
750 
 
751 
 full  <= 1'b1;
752 
 
753 
 end//end if
754 
 
755 
end//end always
756 
 
757 
 
758 
 
759 
always @(posedge clk) begin
760 
 
761 
 if (wr_en)
762 
 
763 
 mem[wr_loc] <= din;
764 
 
765 
end //end always
766 
 
767 
assign dout = mem[rd_loc];//rd_en ? mem[rd_loc]:'h0;
768 
 
769 
endmodule
770 230 diegovalve 
 
771 
//---------------------------------------------------------------------
772 
 
773 
/*
774 213 diegovalve 
Synchronous memory blocks have two independent address ports, allowing
775 
for operations on two unique addresses simultaneously. A read operation and a write
776 230 diegovalve 
operation can share the same port if they share the same address.
777 213 diegovalve 
In the synchronous RAM block architecture, there is no priority between the two
778 
ports. Therefore, if you write to the same location on both ports at the same time, the
779 230 diegovalve 
result is indeterminate in the device architecture.
780 213 diegovalve 
When a read and write operation occurs on the same port for
781 
the same address, the new data being written to the memory is read. When a read and
782 
write operation occurs on different ports for the same address, the old data in the
783 
memory is read. Simultaneous writes to the same location on both ports results in
784 230 diegovalve 
indeterminate behavior.
785 
 
786 
*/
787 213 diegovalve 
module RAM_DUAL_READ_DUAL_WRITE_PORT  # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
788 
(
789 
input wire [(DATA_WIDTH-1):0] data_a, data_b,
790 
input wire [(ADDR_WIDTH-1):0] addr_a, addr_b,
791 
input wire we_a, we_b, clk,
792 
output reg [(DATA_WIDTH-1):0] q_a, q_b
793 
);
794 
 
795 
 
796 
// Declare the RAM variable
797 
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
798 
        always @ (posedge clk)
799 
        begin // Port A
800 
                if (we_a)
801 
                begin
802 
                        ram[addr_a] <= data_a;
803 
                        q_a <= data_a;
804 
                end
805 
                else
806 
                        q_a <= ram[addr_a];
807 230 diegovalve 
        end
808 213 diegovalve 
 
809 
        always @ (posedge clk)
810 
        begin // Port b
811 
                if (we_b)
812 
                begin
813 
                        ram[addr_b] <= data_b;
814 
                        q_b <= data_b;
815 
                end
816 
                else
817 
                        q_b <= ram[addr_b];
818 
        end
819 230 diegovalve 
endmodule
820 
 
821 
 
822 213 diegovalve 
module RAM_QUAD_PORT  # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
823 
(
824 
input wire [(DATA_WIDTH-1):0] data_a, data_b,
825 230 diegovalve 
input wire [(ADDR_WIDTH-1):0] waddr_a, waddr_b,
826 213 diegovalve 
input wire [(ADDR_WIDTH-1):0] raddr_a, raddr_b,
827 
input wire we_a, we_b, clk,
828 
output reg [(DATA_WIDTH-1):0] q_a, q_b
829 
);
830 
 
831 
 
832 
// Declare the RAM variable
833 
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
834 
        always @ (posedge clk)
835 
        begin // Port A
836 230 diegovalve 
                if (we_a)
837 213 diegovalve 
                begin
838 230 diegovalve 
                        ram[waddr_a] <= data_a;
839 213 diegovalve 
                        q_a <= data_a;
840 230 diegovalve 
                end
841 213 diegovalve 
                else
842 
                        q_a <= ram[waddr_a];
843 230 diegovalve 
        end
844 213 diegovalve 
 
845 
        always @ (posedge clk)
846 
        begin // Port B
847 230 diegovalve 
                if (we_b)
848 213 diegovalve 
                begin
849 230 diegovalve 
                        ram[waddr_b] <= data_b;
850 213 diegovalve 
                        q_b <= data_b;
851 230 diegovalve 
                end
852 213 diegovalve 
                else
853 
                        q_b <= ram[waddr_b];
854 230 diegovalve 
        end
855 213 diegovalve 
 
856 230 diegovalve 
 
857 
endmodule
858 
//-------------------------------------------------------------------------------
859 213 diegovalve 
//----------------------------------------------------
860 
   // A four level, round-robin arbiter. This was
861 
   // orginally coded by WD Peterson in VHDL.
862 
   //----------------------------------------------------
863 
    module ROUND_ROBIN_ARBITER (
864 
      clk,
865 230 diegovalve 
      rst,
866 213 diegovalve 
                req4,
867 
      req3,
868 
      req2,
869 
     req1,
870 230 diegovalve 
     req0,
871 213 diegovalve 
          gnt4,
872 
     gnt3,
873 
     gnt2,
874 
     gnt1,
875 
     gnt0
876 
   );
877 
   // --------------Port Declaration-----------------------
878 
   input           clk;
879 230 diegovalve 
   input           rst;
880 213 diegovalve 
        input           req4;
881 
   input           req3;
882 
   input           req2;
883 
   input           req1;
884 230 diegovalve 
   input           req0;
885 213 diegovalve 
        output          gnt4;
886 
   output          gnt3;
887 
   output          gnt2;
888 
   output          gnt1;
889 
   output          gnt0;
890 
 
891 
   //--------------Internal Registers----------------------
892 
   wire    [2:0]   gnt       ;
893 
   wire            comreq    ;
894 
   wire            beg       ;
895 
   wire   [2:0]    lgnt      ;
896 
   wire            lcomreq   ;
897 
   reg             lgnt0     ;
898 
   reg             lgnt1     ;
899 
   reg             lgnt2     ;
900 230 diegovalve 
   reg             lgnt3     ;
901 213 diegovalve 
        reg             lgnt4     ;
902 
   reg             lasmask   ;
903 
   reg             lmask0    ;
904 230 diegovalve 
   reg             lmask1    ;
905 213 diegovalve 
        reg             lmask2    ;
906 
   reg             ledge     ;
907 
 
908 
   //--------------Code Starts Here-----------------------
909 
   always @ (posedge clk)
910 
   if (rst) begin
911 
     lgnt0 <= 0;
912 
     lgnt1 <= 0;
913 
     lgnt2 <= 0;
914 230 diegovalve 
     lgnt3 <= 0;
915 213 diegovalve 
          lgnt4 <= 0;
916 
   end else begin
917 
     lgnt0 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & ~req3 & ~req2 & ~req1 & req0)
918 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 & ~req4 & ~req3 & ~req2 &  req0)
919 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & ~req3 &  req0)
920 230 diegovalve 
           | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 & ~req4 & req0  )
921 213 diegovalve 
                          | (~lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req0  )
922 
           | ( lcomreq & lgnt0 );
923 
     lgnt1 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 &  req1)
924 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 & ~req4 & ~req3 & ~req2 &  req1 & ~req0)
925 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & ~req3 &  req1 & ~req0)
926 230 diegovalve 
           | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 & ~req4 &  req1 & ~req0)
927 213 diegovalve 
                          | (~lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req1 & ~req0)
928 
           | ( lcomreq &  lgnt1);
929 
     lgnt2 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 &  req2  & ~req1)
930 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 &  req2)
931 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & ~req3 &  req2  & ~req1 & ~req0)
932 230 diegovalve 
           | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 & ~req4 & req2 & ~req1 & ~req0)
933 213 diegovalve 
                          | ( lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req2 & ~req1 & ~req0)
934 
           | ( lcomreq &  lgnt2);
935 
     lgnt3 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3  & ~req2 & ~req1)
936 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 & ~req4 & req3  & ~req2)
937 230 diegovalve 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 & ~req4 & req3)
938 213 diegovalve 
                          | (~lcomreq & ~lmask2 & ~lmask2 &  lmask1 &  lmask0 &  req3)
939 
           | ( lcomreq &  lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3  & ~req2 & ~req1 & ~req0)
940 230 diegovalve 
           | ( lcomreq & lgnt3);
941 213 diegovalve 
          lgnt4 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 &  req4 & ~req3  & ~req2 & ~req1 & ~req0)
942 
           | (~lcomreq & ~lmask2 & ~lmask1 &  lmask0 &  req4 & ~req3  & ~req2 & ~req1 )
943 230 diegovalve 
           | (~lcomreq & ~lmask2 &  lmask1 & ~lmask0 &  req4 & ~req3  & ~req2 )
944 213 diegovalve 
                          | (~lcomreq & ~lmask2 &  lmask1 &  lmask0 &  req4 & ~req3 )
945 
           | ( lcomreq &  lmask2 & ~lmask1 & ~lmask0 &  req4 )
946 
           | ( lcomreq & lgnt3);
947 
   end
948 
 
949 
   //----------------------------------------------------
950 
   // lasmask state machine.
951 
   //----------------------------------------------------
952 
   assign beg = (req4 | req3 | req2 | req1 | req0) & ~lcomreq;
953 
   always @ (posedge clk)
954 
   begin
955 
     lasmask <= (beg & ~ledge & ~lasmask);
956 
     ledge   <= (beg & ~ledge &  lasmask)
957 
             |  (beg &  ledge & ~lasmask);
958 
   end
959 
 
960 
   //----------------------------------------------------
961 
   // comreq logic.
962 
   //----------------------------------------------------
963 230 diegovalve 
   assign lcomreq =
964 
                                                        ( req4 & lgnt4 )
965 213 diegovalve 
                                                 | ( req3 & lgnt3 )
966 
                   | ( req2 & lgnt2 )
967 
                   | ( req1 & lgnt1 )
968 
                   | ( req0 & lgnt0 );
969 
 
970 
   //----------------------------------------------------
971 
   // Encoder logic.
972 
   //----------------------------------------------------
973 
   assign  lgnt =  {lgnt4,(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
974 
 
975 
   //----------------------------------------------------
976 
   // lmask register.
977 
  //----------------------------------------------------
978 
  always @ (posedge clk )
979 230 diegovalve 
  if( rst ) begin
980 213 diegovalve 
         lmask2 <= 0;
981 
    lmask1 <= 0;
982 230 diegovalve 
    lmask0 <= 0;
983 
  end else if(lasmask) begin
984 213 diegovalve 
    lmask2 <= lgnt[2];
985 
    lmask1 <= lgnt[1];
986 
    lmask0 <= lgnt[0];
987 230 diegovalve 
  end else begin
988 213 diegovalve 
         lmask2 <= lmask2;
989 
    lmask1 <= lmask1;
990 
    lmask0 <= lmask0;
991 
  end
992 
 
993 
  assign comreq = lcomreq;
994 
  assign gnt    = lgnt;
995 
  //----------------------------------------------------
996 
  // Drive the outputs
997 230 diegovalve 
  //----------------------------------------------------
998 213 diegovalve 
  assign gnt4   = lgnt4;
999 
  assign gnt3   = lgnt3;
1000 
  assign gnt2   = lgnt2;
1001 
  assign gnt1   = lgnt1;
1002 
  assign gnt0   = lgnt0;
1003 
 
1004 230 diegovalve 
  endmodule
1005 
//-------------------------------------------------------------------------------
1006 
module ROUND_ROBIN_5_ENTRIES
1007 
(
1008 
input wire Clock,
1009 
input wire Reset,
1010 
input wire iRequest0,
1011 
input wire iRequest1,
1012 
input wire iRequest2,
1013 
input wire iRequest3,
1014 
input wire iRequest4,
1015 
output wire oGrant0,
1016 
output wire oGrant1,
1017 
output wire oGrant2,
1018 
output wire oGrant3,
1019 
output wire oGrant4,
1020 
output wire oPriorityGrant
1021 
 
1022 
);
1023 
wire wMaks2,wMaks1,wMaks0;
1024 
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4;
1025 
 
1026 
assign wGrant0 =
1027 
                   (wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest0 &  ~iRequest4 )
1028 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest4 & ~iRequest3 )
1029 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest4 & ~iRequest3 & ~iRequest2 )
1030 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1031 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 );
1032 
 
1033 
 
1034 
assign wGrant1 =
1035 
                   (wMaks2 &  ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest4)
1036 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest4 & ~iRequest3 )
1037 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest4 & ~iRequest3 & ~iRequest2 )
1038 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 )
1039 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0) ;
1040 
 
1041 
assign wGrant2 =
1042 
                   (wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest4 )
1043 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest4 & ~iRequest3 )
1044 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 )
1045 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 )
1046 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 );
1047 
 
1048 
assign wGrant3 =
1049 
                   (wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest4 )
1050 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest3 )
1051 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 )
1052 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 )
1053 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1054 
 
1055 
assign wGrant4 =
1056 
                   ( wMaks2 &  ~wMaks1 &  ~wMaks0 &  iRequest4 )
1057 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest4 & ~iRequest3 )
1058 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 )
1059 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1060 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1061 
 
1062 
 
1063 
assign oPriorityGrant = wGrant0;
1064 
wire wGrant1_Pre, wGrant2_Pre, wGrant3_Pre, wGrant4_Pre;
1065 
 
1066 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
1067 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant0, oGrant0);
1068 
 
1069 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
1070 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant1,  wGrant1_Pre );  //If priority grant comes this cycle then we are having troubles...
1071 
 
1072 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
1073 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant2, wGrant2_Pre );
1074 
 
1075 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
1076 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant3, wGrant3_Pre );
1077 
 
1078 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
1079 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant4, wGrant4_Pre );
1080 
 
1081 
 
1082 
assign oGrant1 = wGrant1_Pre & ~oPriorityGrant;
1083 
assign oGrant2 = wGrant2_Pre & ~oPriorityGrant;
1084 
assign oGrant3 = wGrant3_Pre & ~oPriorityGrant;
1085 
assign oGrant4 = wGrant4_Pre & ~oPriorityGrant;
1086 
 
1087 
reg [4:0]  rCurrentState, rNextState;
1088 213 diegovalve 
//Next states logic and Reset sequence
1089 
always @(posedge Clock )
1090 
  begin
1091 
 
1092 
    if (Reset )
1093 
                rCurrentState <= 0;
1094 
    else
1095 
                rCurrentState <= rNextState;
1096 
 
1097 230 diegovalve 
end
1098 
reg[2:0] rMask;
1099 
 
1100 
assign wMaks0 = rMask[0];
1101 
assign wMaks1 = rMask[1];
1102 
assign wMaks2 = rMask[2];
1103 
 
1104 
always @ ( * )
1105 
begin
1106 
        case (rCurrentState)
1107 
        //--------------------------------------
1108 
        0:  //Mask for grant 0
1109 
        begin
1110 
                rMask = 3'd0;
1111 
                rNextState = 1;
1112 
        end
1113 
        1: //Mask for grant 1
1114 
        begin
1115 213 diegovalve 
                rMask = 3'd1;
1116 230 diegovalve 
                rNextState = 2;
1117 
        end
1118 
        2:
1119 
        begin
1120 
                rMask = 3'd2;
1121 
                rNextState = 3;
1122 
        end
1123 
        3:
1124 
        begin
1125 
                rMask = 3'd3;
1126 
                rNextState = 4;
1127 
        end
1128 
        4:
1129 
        begin
1130 
                rMask = 3'd4;
1131 
                rNextState = 0;
1132 
        end
1133 
        endcase
1134 
end
1135 
        /*
1136 213 diegovalve 
UPCOUNTER_POSEDGE # (3) UP1
1137 
(
1138 230 diegovalve 
.Clock( Clock ),
1139 213 diegovalve 
.Reset( Reset ),
1140 230 diegovalve 
.Initial( 3'b0 ),
1141 
.Enable( 1'b1 ),
1142 213 diegovalve 
.Q({wMaks2,wMaks1,wMaks0})
1143 230 diegovalve 
);
1144 
*/
1145 
 
1146 
 
1147 
endmodule
1148 
//-------------------------------------------------------------------------------
1149 
module ROUND_ROBIN_6_ENTRIES
1150 
(
1151 
input wire Clock,
1152 
input wire Reset,
1153 
input wire iRequest0,
1154 
input wire iRequest1,
1155 
input wire iRequest2,
1156 
input wire iRequest3,
1157 
input wire iRequest4,
1158 
input wire iRequest5,
1159 
output wire oGrant0,
1160 
output wire oGrant1,
1161 
output wire oGrant2,
1162 
output wire oGrant3,
1163 
output wire oGrant4,
1164 
output wire oGrant5,
1165 
output wire oPriorityGrant
1166 
 
1167 
);
1168 
wire wMaks2,wMaks1,wMaks0;
1169 
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5;
1170 
 
1171 
assign wGrant0 =
1172 
                   (wMaks2 &  ~wMaks1 &  wMaks0 & iRequest0 &  ~iRequest5 )
1173 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 )
1174 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 )
1175 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1176 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
1177 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 );
1178 
 
1179 
 
1180 
assign wGrant1 =
1181 
                   (wMaks2 &  ~wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5)
1182 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 )
1183 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 )
1184 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
1185 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 )
1186 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0);
1187 
 
1188 
assign wGrant2 =
1189 
                   (wMaks2 &  ~wMaks1 &   wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 )
1190 
                                                |( wMaks2 & ~wMaks1 &  ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 )
1191 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4 & ~iRequest3)
1192 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 )
1193 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 )
1194 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 );
1195 
 
1196 
assign wGrant3 =
1197 
                                                 ( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 )
1198 
                  |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest5 & ~iRequest4)
1199 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest3 )
1200 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 )
1201 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 )
1202 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1203 
 
1204 
assign wGrant4 =
1205 
                   ( wMaks2 &  ~wMaks1 &  wMaks0 &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5)
1206 
                                                |( wMaks2 &  ~wMaks1 & ~wMaks0 &  iRequest4  )
1207 
                                                |(~wMaks2 &  wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3  )
1208 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2   )
1209 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1  )
1210 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1211 
 
1212 
assign wGrant5 =
1213 
                  ( wMaks2 &  ~wMaks1 &   wMaks0 & iRequest5 )
1214 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 )
1215 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 )
1216 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1217 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1218 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1219 
 
1220 
 
1221 
assign oPriorityGrant = wGrant0;
1222 
 
1223 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
1224 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant0, oGrant0);
1225 
 
1226 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
1227 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant1,  oGrant1 );
1228 
 
1229 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
1230 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant2, oGrant2 );
1231 
 
1232 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
1233 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant3, oGrant3 );
1234 
 
1235 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
1236 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant4, oGrant4 );
1237 
 
1238 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
1239 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant5, oGrant5 );
1240 
 
1241 
 
1242 
reg [4:0]  rCurrentState, rNextState;
1243 213 diegovalve 
//Next states logic and Reset sequence
1244 
always @(posedge Clock )
1245 
  begin
1246 
 
1247 
    if (Reset )
1248 
                rCurrentState <= 0;
1249 
    else
1250 
                rCurrentState <= rNextState;
1251 
 
1252 230 diegovalve 
end
1253 
reg[2:0] rMask;
1254 
 
1255 
assign wMaks0 = rMask[0];
1256 
assign wMaks1 = rMask[1];
1257 
assign wMaks2 = rMask[2];
1258 
 
1259 
always @ ( * )
1260 
begin
1261 
        case (rCurrentState)
1262 
        //--------------------------------------
1263 
        0:
1264 
        begin
1265 
                rMask = 3'd0;
1266 
                rNextState = 1;
1267 
        end
1268 
        1:
1269 
        begin
1270 
                rMask = 3'd1;
1271 
                rNextState = 2;
1272 
        end
1273 
        2:
1274 
        begin
1275 
                rMask = 3'd2;
1276 
                rNextState = 3;
1277 
        end
1278 
        3:
1279 
        begin
1280 
                rMask = 3'd3;
1281 
                rNextState = 4;
1282 
        end
1283 
        4:
1284 
        begin
1285 
                rMask = 3'd4;
1286 
                rNextState = 5;
1287 
        end
1288 
        5:
1289 
        begin
1290 
                rMask = 3'd5;
1291 
                rNextState = 0;
1292 
        end
1293 
        endcase
1294 
end
1295 
        /*
1296 213 diegovalve 
UPCOUNTER_POSEDGE # (3) UP1
1297 
(
1298 230 diegovalve 
.Clock( Clock ),
1299 213 diegovalve 
.Reset( Reset ),
1300 230 diegovalve 
.Initial( 3'b0 ),
1301 
.Enable( 1'b1 ),
1302 213 diegovalve 
.Q({wMaks2,wMaks1,wMaks0})
1303 230 diegovalve 
);
1304 
*/
1305 
 
1306 
 
1307 
endmodule
1308 
//-------------------------------------------------------------------------------
1309 
//-------------------------------------------------------------------------------
1310 
module ROUND_ROBIN_7_ENTRIES
1311 
(
1312 
input wire Clock,
1313 
input wire Reset,
1314 
input wire iRequest0,
1315 
input wire iRequest1,
1316 
input wire iRequest2,
1317 
input wire iRequest3,
1318 
input wire iRequest4,
1319 
input wire iRequest5,
1320 
input wire iRequest6,
1321 
output wire oGrant0,
1322 
output wire oGrant1,
1323 
output wire oGrant2,
1324 
output wire oGrant3,
1325 
output wire oGrant4,
1326 
output wire oGrant5,
1327 
output wire oGrant6,
1328 
output wire oPriorityGrant
1329 
 
1330 
);
1331 
wire wMaks2,wMaks1,wMaks0;
1332 
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5,wGrant6;
1333 
 
1334 
assign wGrant0 =
1335 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest6 )
1336 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 )
1337 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 )
1338 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
1339 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
1340 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
1341 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest0 );
1342 
 
1343 
 
1344 
assign wGrant1 =
1345 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6)
1346 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 )
1347 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 )
1348 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
1349 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
1350 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &   iRequest1 )
1351 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &   iRequest1 & ~iRequest0);
1352 
 
1353 
assign wGrant2 =
1354 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 )
1355 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 )
1356 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4)
1357 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
1358 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest2 )
1359 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest2 & ~iRequest1 )
1360 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest2 & ~iRequest1 & ~iRequest0 );
1361 
 
1362 
assign wGrant3 =
1363 
                                                 ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 )
1364 
                  |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5)
1365 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 &  ~iRequest6 & ~iRequest5 & ~iRequest4)
1366 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest3 )
1367 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 )
1368 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 )
1369 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1370 
 
1371 
assign wGrant4 =
1372 
                   ( wMaks2 &   wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6)
1373 
                                                |( wMaks2 &  ~wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
1374 
                                                |( wMaks2 &  ~wMaks1 & ~wMaks0  &  iRequest4  )
1375 
                                                |(~wMaks2 &   wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3  )
1376 
                                                |(~wMaks2 &   wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2   )
1377 
                                                |(~wMaks2 &  ~wMaks1 &  wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1  )
1378 
                                                |(~wMaks2 &  ~wMaks1 & ~wMaks0  &  iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1379 
 
1380 
assign wGrant5 =
1381 
                  (  wMaks2 &  wMaks1 & ~wMaks0  &  iRequest5 & ~iRequest4 )
1382 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest5 )
1383 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 )
1384 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1385 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1386 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 )
1387 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6);
1388 
 
1389 
assign wGrant6 =
1390 
                   ( wMaks2 &  wMaks1 & ~wMaks0 &  iRequest6 )
1391 
                                                |( wMaks2 & ~wMaks1 &  wMaks0 &  iRequest6 & ~iRequest5 )
1392 
                                                |( wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 )
1393 
                                                |(~wMaks2 &  wMaks1 &  wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
1394 
                                                |(~wMaks2 &  wMaks1 & ~wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
1395 
                                                |(~wMaks2 & ~wMaks1 &  wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
1396 
                                                |(~wMaks2 & ~wMaks1 & ~wMaks0 &  iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
1397 
 
1398 
 
1399 
assign oPriorityGrant = wGrant0;
1400 
 
1401 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
1402 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant0, oGrant0);
1403 
 
1404 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
1405 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant1,  oGrant1 );
1406 
 
1407 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
1408 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant2, oGrant2 );
1409 
 
1410 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
1411 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant3, oGrant3 );
1412 
 
1413 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
1414 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant4, oGrant4 );
1415 
 
1416 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
1417 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant5, oGrant5 );
1418 
 
1419 
 
1420 213 diegovalve 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD6
1421 230 diegovalve 
(       Clock, Reset, 1'b1 , wGrant6, oGrant6 );
1422 
 
1423 
 
1424 
reg [4:0]  rCurrentState, rNextState;
1425 213 diegovalve 
//Next states logic and Reset sequence
1426 
always @(posedge Clock )
1427 
  begin
1428 
 
1429 
    if (Reset )
1430 
                rCurrentState <= 0;
1431 
    else
1432 
                rCurrentState <= rNextState;
1433 
 
1434 230 diegovalve 
end
1435 
reg[2:0] rMask;
1436 
 
1437 
assign wMaks0 = rMask[0];
1438 
assign wMaks1 = rMask[1];
1439 
assign wMaks2 = rMask[2];
1440 
 
1441 
always @ ( * )
1442 
begin
1443 
        case (rCurrentState)
1444 
        //--------------------------------------
1445 
        0:
1446 
        begin
1447 
                rMask = 3'd0;
1448 
                rNextState = 1;
1449 
        end
1450 
        1:
1451 
        begin
1452 
                rMask = 3'd1;
1453 
                rNextState = 2;
1454 
        end
1455 
        2:
1456 
        begin
1457 
                rMask = 3'd2;
1458 
                rNextState = 3;
1459 
        end
1460 
        3:
1461 
        begin
1462 
                rMask = 3'd3;
1463 
                rNextState = 4;
1464 
        end
1465 
        4:
1466 
        begin
1467 
                rMask = 3'd4;
1468 
                rNextState = 5;
1469 
        end
1470 
        5:
1471 
        begin
1472 
                rMask = 3'd5;
1473 
                rNextState = 6;
1474 
        end
1475 
        6:
1476 
        begin
1477 
                rMask = 3'd6;
1478 
                rNextState = 0;
1479 
        end
1480 
        endcase
1481 
end
1482 
 
1483 
 
1484 213 diegovalve 
endmodule
1485 
`endif

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