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1 213 diegovalve
/*
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        Fixed point Multiplication Module Qm.n
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        C = (A << n) / B
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*/
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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//---------------------------------------------------------------------------
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// serial_divide_uu.v  -- Serial division module
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//
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//
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// Description: See description below (which suffices for IP core
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//                                     specification document.)
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//
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// Copyright (C) 2002 John Clayton and OPENCORES.ORG (this Verilog version)
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation;  either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//-----------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date  : Jan. 30, 2003
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// Update: Jan. 30, 2003  Copied this file from "vga_crosshair.v"
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//                        Stripped out extraneous stuff.
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// Update: Mar. 14, 2003  Added S_PP parameter, made some simple changes to
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//                        implement quotient leading zero "skip" feature.
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// Update: Mar. 24, 2003  Updated comments to improve readability.
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//
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//-----------------------------------------------------------------------------
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// Description:
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//
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// This module performs a division operation serially, producing one bit of the
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// answer per clock cycle.  The dividend and the divisor are both taken to be
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// unsigned quantities.  The divider is conceived as an integer divider (as
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// opposed to a divider for fractional quantities) but the user can configure
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// the divider to divide fractional quantities as long as the position of the
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// binary point is carefully monitored.
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//
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// The widths of the signals are configurable by parameters, as follows:
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//
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// M_PP = Bit width of the dividend
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// N_PP = Bit width of the divisor
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// R_PP = Remainder bits desired
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// S_PP = Skipped quotient bits
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//
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// The skipped quotient bits parameter provides a way to prevent the divider
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// from calculating the full M_PP+R_PP output bits, in case some of the leading
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// bits are already known to be zero.  This is the case, for example, when
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// dividing two quantities to obtain a result that is a fraction between 0 and 1
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// (as when measuring PWM signals).  In that case the integer portion of the
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// quotient is always zero, and therefore it need not be calculated.
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//
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// The divide operation is begun by providing a pulse on the divide_i input.
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// The quotient is provided (M_PP+R_PP-S_PP) clock cycles later.
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// The divide_i pulse stores the input parameters in registers, so they do
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// not need to be maintained at the inputs throughout the operation of the module.
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// If a divide_i pulse is given to the serial_divide_uu module during the time
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// when it is already working on a previous divide operation, it will abort the
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// operation it was doing, and begin working on the new one.
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//
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// The user is responsible for treating the results correctly.  The position
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// of the binary point is not given, but it is understood that the integer part
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// of the result is the M_PP most significant bits of the quotient output.
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// The remaining R_PP least significant bits are the fractional part.
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//
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// This is illustrated graphically:
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//
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//     [ M_PP bits ][    R_PP bits]
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//     [ S_PP bits    ][quotient_o]
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//
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// The quotient will consist of whatever bits are left after removing the S_PP
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// most significant bits from the (M_PP+R_PP) result bits.
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//
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// Attempting to divide by zero will simply produce a result of all ones.
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// This core is so simple, that no checking for this condition is provided.
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// If the user is concerned about a possible divide by zero condition, he should
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// compare the divisor to zero and flag that condition himself!
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//
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// The COUNT_WIDTH_PP parameter must be sized so that 2^COUNT_WIDTH_PP-1 is >=
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// M_PP+R_PP-S_PP-1.  The unit terminates the divide operation when the count
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// is equal to M_PP+R_PP-S_PP-1.
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// 
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// The HELD_OUTPUT_PP parameter causes the unit to keep its output result in
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// a register other than the one which it uses to compute the quotient.  This
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// is useful for applications where the divider is used repeatedly and the
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// previous divide result (quotient) must be stable during the computation of the
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// next divide result.  Using the additional output register does incur some
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// additional utilization of resources.
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//
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//-----------------------------------------------------------------------------
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module serial_divide_uu (
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  clk_i,
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  clk_en_i,
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  rst_i,
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  divide_i,
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  dividend_i,
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  divisor_i,
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  quotient_o,
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  done_o
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  );
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 /*
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 M_PP => 21,
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                N_PP => 21,
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                R_PP => 0,
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                S_PP => 0,
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                HELD_OUTPUT_PP => 1
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                                         */
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parameter M_PP = 21;           // Size of dividend
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parameter N_PP = 21;            // Size of divisor
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parameter R_PP = 0;            // Size of remainder
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parameter S_PP = 0;            // Skip this many bits (known leading zeros)
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parameter COUNT_WIDTH_PP = 5;  // 2^COUNT_WIDTH_PP-1 >= (M_PP+R_PP-S_PP-1)
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parameter HELD_OUTPUT_PP = 1;  // Set to 1 if stable output should be held
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                               // from previous operation, during current
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                               // operation.  Using this option will increase
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                               // the resource utilization (costs extra
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                               // d-flip-flops.)
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// I/O declarations
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input  clk_i;                           //
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input  clk_en_i;
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input  rst_i;                           // synchronous reset
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input  divide_i;                        // starts division operation
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input  [M_PP-1:0] dividend_i;           //
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input  [N_PP-1:0] divisor_i;            //
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output [M_PP+R_PP-S_PP-1:0] quotient_o; //
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output done_o;                          // indicates completion of operation
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//reg  [M_PP+R_PP-1:0] quotient_o;
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reg  done_o;
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152
// Internal signal declarations
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154
reg  [M_PP+R_PP-1:0] grand_dividend;
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reg  [M_PP+N_PP+R_PP-2:0] grand_divisor;
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reg  [M_PP+R_PP-S_PP-1:0] quotient;
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reg  [M_PP+R_PP-1:0] quotient_reg;       // Used exclusively for the held output
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reg  [COUNT_WIDTH_PP-1:0] divide_count;
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wire [M_PP+N_PP+R_PP-1:0] subtract_node; // Subtract node has extra "sign" bit
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wire [M_PP+R_PP-1:0]      quotient_node; // Shifted version of quotient
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wire [M_PP+N_PP+R_PP-2:0]  divisor_node; // Shifted version of grand divisor
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164
//--------------------------------------------------------------------------
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// Module code
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// Serial dividing module
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always @(posedge clk_i)
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begin
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  if (rst_i)
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  begin
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    grand_dividend <= 0;
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    grand_divisor <= 0;
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    divide_count <= 0;
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    quotient <= 0;
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    done_o <= 0;
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  end
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  else if (clk_en_i)
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  begin
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    done_o <= 0;
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    if (divide_i)       // Start a new division
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    begin
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      quotient <= 0;
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      divide_count <= 0;
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      // dividend placed initially so that remainder bits are zero...
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      grand_dividend <= dividend_i << R_PP;
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      // divisor placed initially for a 1 bit overlap with dividend...
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      // But adjust it back by S_PP, to account for bits that are known
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      // to be leading zeros in the quotient.
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          /* verilator lint_off WIDTH */
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      grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1);
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          /* verilator lint_on WIDTH */
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    end
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         /* verilator lint_off WIDTH */
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    else if (divide_count == M_PP+R_PP-S_PP-1)
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         /* verilator lint_on WIDTH */
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    begin
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      if (~done_o) quotient <= quotient_node;      // final shift...
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      if (~done_o) quotient_reg <= quotient_node;  // final shift (held output)
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      done_o <= 1;                                 // Indicate done, just sit
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    end
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    else                // Division in progress
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    begin
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      // If the subtraction yields a positive result, then store that result
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          /* verilator lint_off WIDTH */
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      if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;
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          /* verilator lint_on WIDTH */
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      // If the subtraction yields a positive result, then a 1 bit goes into 
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      // the quotient, via a shift register
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      quotient <= quotient_node;
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      // shift the grand divisor to the right, to cut it in half next clock cycle
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      grand_divisor <= divisor_node;
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      // Advance the counter
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      divide_count <= divide_count + 1;
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    end
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  end  // End of else if clk_en_i
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end // End of always block
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 /* verilator lint_off WIDTH */
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assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
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/* verilator lint_on WIDTH */
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assign quotient_node =
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  {quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
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assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
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assign quotient_o = (HELD_OUTPUT_PP == 0)?quotient:quotient_reg;
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endmodule
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module SignedIntegerDivision
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(
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        input wire Clock,
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        input wire Reset,
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        output wire [`WIDTH-1:0] oQuotient,
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        input wire [`LONG_WIDTH-1:0] iDividend,
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        input wire [`LONG_WIDTH-1:0] iDivisor,
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        input wire iInputReady,
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        output wire OutputReady
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);
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wire wInputReadyDelay1,wInputReadyPulse;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_DELAY1
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(
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        .Clock( Clock ),
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        .Reset( Reset ),
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        .Enable( 1'b1 ),
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        .D( iInputReady ),
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        .Q(wInputReadyDelay1)
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);
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assign wInputReadyPulse = iInputReady & ~wInputReadyDelay1;
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256
  wire [`LONG_WIDTH-1:0] wDividend,wDivisor,wScaledDividend;
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  wire [`LONG_WIDTH-1:0] wNegDividend,wNegDivisor;
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  assign wNegDividend = ~iDividend+1'b1;
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  assign wNegDivisor = ~iDivisor + 1'b1;
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261
  wire [`LONG_WIDTH-1:0] wQuotient;
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  //Assign the sign extended signed value
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  assign wDividend = (iDividend[`LONG_WIDTH-1] == 1'b1) ?    wNegDividend : iDividend;
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  assign wDivisor = (iDivisor[`LONG_WIDTH-1] == 1'b1) ?   wNegDivisor : iDivisor ;
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  wire wNegativeOutput;
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  assign wNegativeOutput = iDividend[`LONG_WIDTH-1] ^ iDivisor[`LONG_WIDTH-1];
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  wire wNegativeOutput_Latched;
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   FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_NEG
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(
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        .Clock( Clock ),
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        .Reset( Reset  ),
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        .Enable( iInputReady ),
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        .D( wNegativeOutput ),
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        .Q(wNegativeOutput_Latched)
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);
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  wire wDividerEnable;
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  UPCOUNTER_POSEDGE # (1) UP1
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(
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.Clock(Clock),
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.Reset(Reset),
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.Initial(1'b0),
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.Enable(OutputReady | iInputReady ),
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.Q(wDividerEnable)
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);
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289
 
290
  assign oQuotient = (wNegativeOutput_Latched) ? ~wQuotient[`WIDTH-1:0]+1'b1 : wQuotient[`WIDTH-1:0];
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  wire wOutputReady,wOutputReadyDelay1;
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  FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_DELAY2
294
(
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        .Clock( Clock ),
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        .Reset( Reset | iInputReady),
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        .Enable( 1'b1 ),
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        .D( wOutputReady ),
299
        .Q(wOutputReadyDelay1)
300
);
301
  assign OutputReady = (wOutputReady ^ wOutputReadyDelay1) & wDividerEnable;
302
  assign wScaledDividend = (wDividend); //<< `SCALE);
303
 
304
 serial_divide_uu # ( 64,64,0,0,6,1 ) uu_div(
305
  .clk_i(Clock),
306
  .clk_en_i(
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  //wDividerEnable | Reset),
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  1'b1),
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  .rst_i(Reset),
310
  .divide_i(wInputReadyPulse),//iInputReady),
311
  .dividend_i(wScaledDividend),
312
  .divisor_i(wDivisor),
313
  .quotient_o(wQuotient),
314
  .done_o(wOutputReady)
315
  );
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endmodule

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