OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_Logic_Station.v] - Blame information for rev 213

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 213 diegovalve
`include "aDefinitions.v"
2
 
3
 
4
/**********************************************************************************
5
Theia, Ray Cast Programable graphic Processing Unit.
6
Copyright (C) 2012  Diego Valverde (diego.valverde.g@gmail.com)
7
 
8
This program is free software; you can redistribute it and/or
9
modify it under the terms of the GNU General Public License
10
as published by the Free Software Foundation; either version 2
11
of the License, or (at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21
 
22
***********************************************************************************/
23
 
24
 
25
module LOGIC_STATION
26
(
27
   input wire Clock,
28
   input wire Reset,
29
   input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
30
   input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
31
        input wire [3:0]                                          iId,
32
        output wire [`COMMIT_PACKET_SIZE-1:0]                     oCommitData,
33
        output wire                                               oCommitResquest,
34
        input wire                                                iCommitGranted,
35
        output wire                                               oBusy
36
 
37
);
38
 
39
wire                           wExeDone;
40
wire [2:0]                     wExeDoneTmp;
41
wire                           wRS1_2_ADD_Trigger;
42
wire [`DATA_ROW_WIDTH-1:0]     wRS1_OperandA;
43
wire [`DATA_ROW_WIDTH-1:0]     wRS1_OperandB;
44
wire [`DATA_ROW_WIDTH-1:0]     wAND,wOR,wResult;
45
wire [1:0]                     wResultSelector;
46
 
47
ReservationStation_1Cycle RS
48
(
49
        .Clock(              Clock                           ),
50
        .Reset(              Reset                           ),
51
        .iIssueBus(          iIssueBus                       ),
52
        .iCommitBus(         iCommitBus                      ),
53
        .iMyId(              iId                             ),
54
        .iExecutionDone(     wExeDone                        ),
55
        .iResult(             wResult                        ),
56
        .iCommitGranted(     iCommitGranted                  ),
57
 
58
        .oSource1(          wRS1_OperandA                   ),
59
        .oSource0(          wRS1_OperandB                   ),
60
        .oBusy(              oBusy                           ),
61
        .oTrigger(           wRS1_2_ADD_Trigger              ),
62
        .oCommitRequest(     oCommitResquest                 ),
63
        .oId(              oCommitData[`COMMIT_RSID_RNG]                                ),
64
        .oWE(              oCommitData[`COMMIT_WE_RNG]                                  ),
65
        .oDestination(     oCommitData[`COMMIT_DST_RNG]                               ),
66
        .oScale(wResultSelector),
67
        .oResult(          {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]})
68
 
69
);
70
 
71
 
72
 MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
73
 (
74
 .Sel( wResultSelector ),
75
 .I1( wAND ),
76
 .I2( wOR ),
77
 .I3(`DATA_ROW_WIDTH'b0),
78
 .I4(`DATA_ROW_WIDTH'b0),
79
 .O1(wResult)
80
 );
81
 
82
assign wExeDone = wExeDoneTmp[0] & wExeDoneTmp[1] & wExeDoneTmp[2];
83
 
84
//TODO: For now I am only supporting AND, eventually you will have to use the MOD_ISSUE_SCALE_RNG
85
//to select between AND, OR, NOT, etc.
86
AND # (`WIDTH) AND_0
87
(
88
   .Clock(     Clock                   ),
89
        .Reset(     Reset                   ),
90
   .iTrigger(   wRS1_2_ADD_Trigger     ),
91
   .iA(        wRS1_OperandA[`X_RNG]   ),
92
        .iB(        wRS1_OperandB[`X_RNG]   ),
93
        .oDone(     wExeDoneTmp[0]          ),
94
   .oR(        wAND[`X_RNG]         )
95
);
96
 
97
AND # (`WIDTH) AND_1
98
(
99
   .Clock(     Clock                   ),
100
        .Reset(     Reset                   ),
101
   .iTrigger(   wRS1_2_ADD_Trigger     ),
102
   .iA(        wRS1_OperandA[`Y_RNG]   ),
103
        .iB(        wRS1_OperandB[`Y_RNG]   ),
104
        .oDone(     wExeDoneTmp[1]          ),
105
   .oR(        wAND[`Y_RNG]         )
106
);
107
 
108
AND # (`WIDTH) AND_2
109
(
110
   .Clock(     Clock                   ),
111
        .Reset(     Reset                   ),
112
   .iTrigger(   wRS1_2_ADD_Trigger     ),
113
   .iA(        wRS1_OperandA[`Z_RNG]   ),
114
        .iB(        wRS1_OperandB[`Z_RNG]   ),
115
        .oDone(     wExeDoneTmp[2]          ),
116
   .oR(        wAND[`Z_RNG]         )
117
);
118
 
119
OR # (`WIDTH) OR_0
120
(
121
   .Clock(     Clock                   ),
122
        .Reset(     Reset                   ),
123
   .iTrigger(   wRS1_2_ADD_Trigger     ),
124
   .iA(        wRS1_OperandA[`X_RNG]   ),
125
        .iB(        wRS1_OperandB[`X_RNG]   ),
126
        .oDone(     wExeDoneTmp[0]          ),
127
   .oR(        wOR[`X_RNG]         )
128
);
129
 
130
OR # (`WIDTH) OR_1
131
(
132
   .Clock(     Clock                   ),
133
        .Reset(     Reset                   ),
134
   .iTrigger(   wRS1_2_ADD_Trigger     ),
135
   .iA(        wRS1_OperandA[`Y_RNG]   ),
136
        .iB(        wRS1_OperandB[`Y_RNG]   ),
137
        .oDone(     wExeDoneTmp[1]          ),
138
   .oR(        wOR[`Y_RNG]         )
139
);
140
 
141
OR # (`WIDTH) OR_2
142
(
143
   .Clock(     Clock                   ),
144
        .Reset(     Reset                   ),
145
   .iTrigger(   wRS1_2_ADD_Trigger     ),
146
   .iA(        wRS1_OperandA[`Z_RNG]   ),
147
        .iB(        wRS1_OperandB[`Z_RNG]   ),
148
        .oDone(     wExeDoneTmp[2]          ),
149
   .oR(        wOR[`Z_RNG]         )
150
);
151
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.