OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_Logic_Station.v] - Blame information for rev 230

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 213 diegovalve
`include "aDefinitions.v"
2
 
3
 
4
/**********************************************************************************
5
Theia, Ray Cast Programable graphic Processing Unit.
6
Copyright (C) 2012  Diego Valverde (diego.valverde.g@gmail.com)
7
 
8
This program is free software; you can redistribute it and/or
9
modify it under the terms of the GNU General Public License
10
as published by the Free Software Foundation; either version 2
11
of the License, or (at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21
 
22
***********************************************************************************/
23
 
24
 
25
module LOGIC_STATION
26
(
27
   input wire Clock,
28
   input wire Reset,
29
   input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
30
   input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
31
        input wire [3:0]                                          iId,
32
        output wire [`COMMIT_PACKET_SIZE-1:0]                     oCommitData,
33
        output wire                                               oCommitResquest,
34
        input wire                                                iCommitGranted,
35
        output wire                                               oBusy
36
 
37
);
38
 
39
wire                           wExeDone;
40
wire [2:0]                     wExeDoneTmp;
41
wire                           wRS1_2_ADD_Trigger;
42
wire [`DATA_ROW_WIDTH-1:0]     wRS1_OperandA;
43
wire [`DATA_ROW_WIDTH-1:0]     wRS1_OperandB;
44
wire [`DATA_ROW_WIDTH-1:0]     wAND,wOR,wResult;
45 230 diegovalve
wire [`SCALE_SIZE-1:0]         wResultSelector_Temp;
46 213 diegovalve
wire [1:0]                     wResultSelector;
47
 
48
ReservationStation_1Cycle RS
49
(
50 230 diegovalve
        .Clock(              Clock                                                       ),
51
        .Reset(              Reset                                                       ),
52
        .iIssueBus(          iIssueBus                                                   ),
53
        .iCommitBus(         iCommitBus                                                  ),
54
        .iMyId(              iId                                                         ),
55
        .iExecutionDone(     wExeDone                                                    ),
56
        .iResult(             wResult                                                    ),
57
        .iCommitGranted(     iCommitGranted                                              ),
58
        .oSource1(          wRS1_OperandA                                                ),
59
        .oSource0(          wRS1_OperandB                                                ),
60
        .oBusy(              oBusy                                                       ),
61
        .oTrigger(           wRS1_2_ADD_Trigger                                          ),
62
        .oCommitRequest(     oCommitResquest                                             ),
63
        .oId(              oCommitData[`COMMIT_RSID_RNG]                                 ),
64
        .oWE(              oCommitData[`COMMIT_WE_RNG]                                   ),
65
        .oDestination(     oCommitData[`COMMIT_DST_RNG]                                  ),
66
        .oScale(            wResultSelector_Temp                                         ),
67
        .oResult(          {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]} )
68 213 diegovalve
 
69
);
70
 
71 230 diegovalve
assign wResultSelector = wResultSelector_Temp[1:0];
72 213 diegovalve
 
73
 MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
74
 (
75
 .Sel( wResultSelector ),
76
 .I1( wAND ),
77
 .I2( wOR ),
78
 .I3(`DATA_ROW_WIDTH'b0),
79
 .I4(`DATA_ROW_WIDTH'b0),
80
 .O1(wResult)
81
 );
82
 
83
assign wExeDone = wExeDoneTmp[0] & wExeDoneTmp[1] & wExeDoneTmp[2];
84
 
85
//TODO: For now I am only supporting AND, eventually you will have to use the MOD_ISSUE_SCALE_RNG
86
//to select between AND, OR, NOT, etc.
87
AND # (`WIDTH) AND_0
88
(
89
   .Clock(     Clock                   ),
90
        .Reset(     Reset                   ),
91
   .iTrigger(   wRS1_2_ADD_Trigger     ),
92
   .iA(        wRS1_OperandA[`X_RNG]   ),
93
        .iB(        wRS1_OperandB[`X_RNG]   ),
94
        .oDone(     wExeDoneTmp[0]          ),
95
   .oR(        wAND[`X_RNG]         )
96
);
97
 
98
AND # (`WIDTH) AND_1
99
(
100
   .Clock(     Clock                   ),
101
        .Reset(     Reset                   ),
102
   .iTrigger(   wRS1_2_ADD_Trigger     ),
103
   .iA(        wRS1_OperandA[`Y_RNG]   ),
104
        .iB(        wRS1_OperandB[`Y_RNG]   ),
105
        .oDone(     wExeDoneTmp[1]          ),
106
   .oR(        wAND[`Y_RNG]         )
107
);
108
 
109
AND # (`WIDTH) AND_2
110
(
111
   .Clock(     Clock                   ),
112
        .Reset(     Reset                   ),
113
   .iTrigger(   wRS1_2_ADD_Trigger     ),
114
   .iA(        wRS1_OperandA[`Z_RNG]   ),
115
        .iB(        wRS1_OperandB[`Z_RNG]   ),
116
        .oDone(     wExeDoneTmp[2]          ),
117
   .oR(        wAND[`Z_RNG]         )
118
);
119
 
120
OR # (`WIDTH) OR_0
121
(
122
   .Clock(     Clock                   ),
123
        .Reset(     Reset                   ),
124
   .iTrigger(   wRS1_2_ADD_Trigger     ),
125
   .iA(        wRS1_OperandA[`X_RNG]   ),
126
        .iB(        wRS1_OperandB[`X_RNG]   ),
127
        .oDone(     wExeDoneTmp[0]          ),
128
   .oR(        wOR[`X_RNG]         )
129
);
130
 
131
OR # (`WIDTH) OR_1
132
(
133
   .Clock(     Clock                   ),
134
        .Reset(     Reset                   ),
135
   .iTrigger(   wRS1_2_ADD_Trigger     ),
136
   .iA(        wRS1_OperandA[`Y_RNG]   ),
137
        .iB(        wRS1_OperandB[`Y_RNG]   ),
138
        .oDone(     wExeDoneTmp[1]          ),
139
   .oR(        wOR[`Y_RNG]         )
140
);
141
 
142
OR # (`WIDTH) OR_2
143
(
144
   .Clock(     Clock                   ),
145
        .Reset(     Reset                   ),
146
   .iTrigger(   wRS1_2_ADD_Trigger     ),
147
   .iA(        wRS1_OperandA[`Z_RNG]   ),
148
        .iB(        wRS1_OperandB[`Z_RNG]   ),
149
        .oDone(     wExeDoneTmp[2]          ),
150
   .oR(        wOR[`Z_RNG]         )
151
);
152
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.