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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_Multiply_Station.v] - Blame information for rev 220

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1 213 diegovalve
`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2012  Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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***********************************************************************************/
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module MUL_STATION
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(
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   input wire Clock,
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   input wire Reset,
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   input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
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   input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
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        input wire [3:0]                                          iId,
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        output wire [`COMMIT_PACKET_SIZE-1:0]                     oCommitData,
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        output wire                                               oCommitResquest,
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        input wire                                                iCommitGranted,
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        output wire                                               oBusy
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);
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wire                           wExeDone;
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wire [2:0]                     wExeDoneTmp;
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wire                           wRS1_2_ADD_Trigger;
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wire [`DATA_ROW_WIDTH-1:0]     wRS1_OperandA;
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wire [`DATA_ROW_WIDTH-1:0]     wRS1_OperandB;
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wire [`DATA_ROW_WIDTH-1:0]     wResult;
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wire [`SCALE_SIZE-1:0]         wScale;
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ReservationStation_1Cycle RS
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(
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        .Clock(              Clock                           ),
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        .Reset(              Reset                           ),
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        .iIssueBus(          iIssueBus                       ),
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        .iCommitBus(         iCommitBus                      ),
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        .iMyId(              iId                             ),
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        .iExecutionDone(     wExeDone                        ),
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        .iResult(             wResult                        ),
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        .iCommitGranted(     iCommitGranted                  ),
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        .oSource1(          wRS1_OperandA                   ),
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        .oSource0(          wRS1_OperandB                   ),
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        .oBusy(              oBusy                           ),
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        .oTrigger(           wRS1_2_ADD_Trigger              ),
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        .oCommitRequest(     oCommitResquest                 ),
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        .oId(              oCommitData[`COMMIT_RSID_RNG]                                ),
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        .oWE(              oCommitData[`COMMIT_WE_RNG]                                  ),
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        .oDestination(     oCommitData[`COMMIT_DST_RNG]                               ),
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        .oScale(            wScale ),
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        .oResult(          {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]})
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);
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assign wExeDone = wExeDoneTmp[0] & wExeDoneTmp[1] & wExeDoneTmp[2];
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RADIX_R_MUL_32_FULL_PARALLEL MUL0
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(
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        .Clock(     Clock                   ),
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        .Reset(     Reset                   ),
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        .A(        wRS1_OperandA[`X_RNG]   ),
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        .B(        wRS1_OperandB[`X_RNG]   ),
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        .R(        wResult[`X_RNG]         ),
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        .iUnscaled(  ~wScale[`SCALE_SRCR_EN] ),
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        .iInputReady( wRS1_2_ADD_Trigger ),
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        .OutputReady( wExeDoneTmp[0] )
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);
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RADIX_R_MUL_32_FULL_PARALLEL MUL1
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(
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        .Clock(     Clock                   ),
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        .Reset(     Reset                   ),
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        .A(        wRS1_OperandA[`Y_RNG]   ),
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        .B(        wRS1_OperandB[`Y_RNG]   ),
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        .R(        wResult[`Y_RNG]         ),
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        .iUnscaled(  ~wScale[`SCALE_SRCR_EN] ),
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        .iInputReady( wRS1_2_ADD_Trigger ),
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        .OutputReady( wExeDoneTmp[1] )
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);
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RADIX_R_MUL_32_FULL_PARALLEL MUL2
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(
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        .Clock(     Clock                   ),
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        .Reset(     Reset                   ),
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        .A(        wRS1_OperandA[`Z_RNG]   ),
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        .B(        wRS1_OperandB[`Z_RNG]   ),
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        .R(        wResult[`Z_RNG]         ),
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        .iUnscaled( ~wScale[`SCALE_SRCR_EN] ),
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        .iInputReady( wRS1_2_ADD_Trigger ),
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        .OutputReady( wExeDoneTmp[2] )
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);
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endmodule

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