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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_ReservationStation.v] - Blame information for rev 230

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`include "aDefinitions.v"
module ReservationStation
(
        input wire                                                Clock,
        input wire                                                Reset,
        input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
        input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
        input wire [3:0]                                          iMyId,
        input wire                                                iExecutionDone,
        input wire                                                iCommitGranted,
        input wire [`DATA_ROW_WIDTH-1:0]                          iResult,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource1,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource0,
        output wire [2:0]                                         oScale,
        output wire [`DATA_ADDRESS_WIDTH-1:0]                     oDestination,
        output wire [`DATA_ROW_WIDTH-1:0]                         oResult,
        output wire [2:0]                                         oWE,
        output wire [3:0]                                         oId,
        output wire                                               oBusy,
        output wire                                               oTrigger,
        output wire                                               oCommitRequest,
        output wire  [`DATA_ROW_WIDTH-1:0]                        oSrc0Latched,oSrc1Latched
 
);
 
wire                                wStall;
wire                                wLatchRequest;
wire [3:0]                          wSource1_RS;
wire [3:0]                          wSource0_RS;
//wire [3:0]                          wMyId;
wire                                wTrigger;
//wire                                wFIFO_Pop;
 
wire [`MOD_ISSUE_PACKET_SIZE-1:0]   wIssue_Latched;
wire [`DATA_ADDRESS_WIDTH-1:0]      wDestination;
wire [3:0]                          wID;
wire [2:0]                          wWE;
wire                                wCommitFifoFull;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
 
assign oScale = wScale;
//assign wFIFO_Pop = iExecutionDone;
assign oCommitRequest = iExecutionDone;
assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
//If there are no dependencies then just trigger execution
//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
assign oTrigger = ( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
 
assign wStall = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
 
wire wLatchData0FromCommitBus;
wire wLatchData1FromCommitBus;
 
 
assign wLatchData0FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
assign wLatchData1FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
 
wire wBusy;
assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
wire wCommitGrantedDelay;
 
UPCOUNTER_POSEDGE # ( 1 ) BUSY
(
        .Clock(    Clock                       ),
        .Reset(    Reset                       ),
        .Enable(   wLatchRequest |  iCommitGranted        ),
        .Initial( 1'b0   ),
        .Q(        wBusy                        )
);
 
 
 
 
 
assign oSource1 =  (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
assign oSource0 =  (wLatchData1FromCommitBus) ? (/*(wDstZero)?`DATA_ROW_WIDTH'b0:*/iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
 
 
wire [`DATA_ROW_WIDTH-1:0]                    wSrc1,wSrc0;
//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
//(     Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
 
wire [3:0] wScale;
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
(       Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
assign oSrc0Latched = wSrc0;
assign oSrc1Latched = wSrc1;
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
 
sync_fifo  # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
(
 .clk(   Clock          ),
 .reset( Reset          ),
 .din(   {wID,wWE,wDestination,iResult}     ),
 .wr_en( iExecutionDone ),
 .rd_en( iCommitGranted ),
 .dout(  {oId,oWE,oDestination,oResult}        ),
 .full(  wCommitFifoFull          )
 
);
 
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
(       Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
 
*/
endmodule
 
module ReservationStation_EX
(
        input wire                                                Clock,
        input wire                                                Reset,
        input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
        input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
        input wire [3:0]                                          iMyId,
        input wire                                                iExecutionDone,
        input wire                                                iCommitGranted,
        input wire [`DATA_ROW_WIDTH-1:0]                          iResult,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource1,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource0,
        output wire [2:0]                                         oScale,
        output wire [`DATA_ADDRESS_WIDTH-1:0]                     oDestination,
        output wire [`DATA_ROW_WIDTH-1:0]                         oResult,
        output wire [2:0]                                         oWE,
        output wire [3:0]                                         oId,
        output wire                                               oBusy,
        output wire                                               oTrigger,
        output wire                                               oCommitRequest,
        output wire  [`DATA_ROW_WIDTH-1:0]                        oSrc0Latched,oSrc1Latched
 
);
 
wire                                wStall;
wire                                wLatchRequest;
wire [3:0]                          wSource1_RS;
wire [3:0]                          wSource0_RS;
//wire [3:0]                          wMyId;
wire                                wTrigger;
//wire                                wFIFO_Pop;
 
wire [`MOD_ISSUE_PACKET_SIZE-1:0]   wIssue_Latched;
wire [`DATA_ADDRESS_WIDTH-1:0]      wDestination;
wire [3:0]                          wID;
wire [2:0]                          wWE;
wire                                wCommitFifoFull;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
 
assign oScale = wScale;
//assign wFIFO_Pop = iExecutionDone;
assign oCommitRequest = iExecutionDone;
assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
//If there are no dependencies then just trigger execution
//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
 
wire wTrigger_Pre,wTrigger_Delay,DependencyResolved_Delay;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDXXX
(       Clock, Reset, 1'b1 , wTrigger_Pre, wTrigger_Delay );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDYYY
(       Clock, Reset, 1'b1 , DependencyResolved, DependencyResolved_Delay );
 
assign wTrigger_Pre = ((wLatchRequest & ~wStall)  | DependencyResolved);//( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
 
//////////////HERE!!!!!!!!!!!!!!!!!!!!!
//assign oTrigger = wTrigger_Pre;//(DependencyResolved) ? wTrigger_Pre : wTrigger_Delay;
assign oTrigger = (DependencyResolved) ? wTrigger_Pre : (wTrigger_Delay & ~DependencyResolved_Delay);
//////////////HERE!!!!!!!!!!!!!!!!!!!!!
 
 
 
//assign wStall = (/*wLatchRequest*/(wBusy||wLatchRequest) && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
 
///assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ||
                  //((wBusy ) && (wSource1_RS != 0 || wSource0_RS != 0) ) ) ? 1'b1 : 1'b0;
wire DependencyDetected,DependencyResolved, wStall_Pre;
assign DependencyDetected = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0));
assign DependencyResolved = ( wLatchData0FromCommitBus ||  wLatchData1FromCommitBus );
 
UPCOUNTER_POSEDGE # ( 1 ) STALL
(
        .Clock(    Clock                                      ),
        .Reset(    Reset                                      ),
        .Enable(   DependencyDetected |  DependencyResolved   ),
        .Initial(  1'b0                                       ),
        .Q(        wStall_Pre                                 )
);
 
assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) || wStall_Pre);
 
 
//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
 
wire wLatchData0FromCommitBus;
wire wLatchData1FromCommitBus;
 
 
assign wLatchData0FromCommitBus = ((wSource0_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
assign wLatchData1FromCommitBus = ((wSource1_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
 
wire wBusy;
assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
wire wCommitGrantedDelay;
 
UPCOUNTER_POSEDGE # ( 1 ) BUSY
(
        .Clock(    Clock                                  ),
        .Reset(    Reset                                  ),
        .Enable(   wLatchRequest |  iCommitGranted        ),
        .Initial( 1'b0                                    ),
        .Q(        wBusy                                  )
);
 
 
 
 
 
assign oSource0 =  (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
assign oSource1 =  (wLatchData1FromCommitBus) ? (iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
 
 
wire [`DATA_ROW_WIDTH-1:0]                    wSrc1,wSrc0;
//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
//(     Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
 
wire [3:0] wScale;
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
(       Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
 
assign oSrc0Latched = (wLatchData0FromCommitBus)? oSource0 : wSrc0;
assign oSrc1Latched = (wLatchData1FromCommitBus)? oSource1 : wSrc1;
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
 
sync_fifo  # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
(
 .clk(   Clock          ),
 .reset( Reset          ),
 .din(   {wID,wWE,wDestination,iResult}     ),
 .wr_en( iExecutionDone ),
 .rd_en( iCommitGranted ),
 .dout(  {oId,oWE,oDestination,oResult}        ),
 .full(  wCommitFifoFull          )
 
);
 
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
(       Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
 
*/
endmodule
 
//-------------------------------------------------------------------------------------------------
module ReservationStation_1Cycle
(
        input wire                                                Clock,
        input wire                                                Reset,
        input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
        input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
        input wire [3:0]                                          iMyId,
        input wire                                                iExecutionDone,
        input wire                                                iCommitGranted,
        input wire [`DATA_ROW_WIDTH-1:0]                          iResult,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource1,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource0,
        output wire [`DATA_ADDRESS_WIDTH-1:0]                     oDestination,
        output wire [`DATA_ROW_WIDTH-1:0]                         oResult,
        output wire [`SCALE_SIZE-1:0]                             oScale,
        output wire [2:0]                                         oWE,
        output wire [3:0]                                         oId,
        output wire                                               oBusy,
        output wire                                               oTrigger,
        output wire                                               oCommitRequest
 
);
 
 
wire [3:0]                          wSource1_RS;
wire [3:0]                          wSource0_RS;
wire [3:0]                          wMyId;
wire                                wTrigger;
wire [`DATA_ADDRESS_WIDTH-1:0]      wDestination;
wire [3:0]                          wID;
wire [2:0]                          wWE;
wire [`DATA_ROW_WIDTH-1:0]          wSrc1,wSrc0,wResult;
//wire                                wDstZero;
wire [`DATA_ROW_WIDTH-1:0]          wSrc1_Fwd;
wire [`DATA_ROW_WIDTH-1:0]          wSrc0_Fwd;
 
wire wSrc0_Dependency_Initial, wSrc0_Dependency;
wire wSrc1_Dependency_Initial, wSrc1_Dependency;
wire wSrc0_DependencyResolved, wSrc0_DependencyLatch;
wire wSrc1_DependencyResolved, wSrc1_DependencyLatch;
wire wWaitingDependency;
wire wHandleCurrentIssue;
wire wDependencyResolved;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
wire wSrc0_DependencyLatch_Pre,wSrc1_DependencyLatch_Pre;
 
assign wHandleCurrentIssue = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
assign wSrc0_Dependency_Initial     = wHandleCurrentIssue & (iIssueBus[96] | iIssueBus[97] | iIssueBus[98] | iIssueBus[99]);
assign wSrc1_Dependency_Initial     = wHandleCurrentIssue & (iIssueBus[196] | iIssueBus[197] | iIssueBus[198] | iIssueBus[199]);
 
 
assign oTrigger =
         (~wWaitingDependency & wHandleCurrentIssue & ~wSrc0_Dependency_Initial & ~wSrc1_Dependency_Initial)
        |(wWaitingDependency  & ~wSrc1_Dependency  &  wSrc0_Dependency  & wSrc0_DependencyResolved )
        |(wWaitingDependency  &  wSrc1_Dependency &  ~wSrc0_Dependency  & wSrc1_DependencyResolved )
        |(wWaitingDependency  &  wSrc1_Dependency  &  wSrc0_Dependency  & wSrc1_DependencyResolved & wSrc0_DependencyResolved );
 
assign wDependencyResolved = wWaitingDependency & ~wSrc1_Dependency & ~wSrc0_Dependency;
 
assign wSrc0_DependencyLatch_Pre = ( wSrc0_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag0)  ) ? 1'b1 : 1'b0;
assign wSrc1_DependencyLatch_Pre = ( wSrc1_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag1)  ) ? 1'b1 : 1'b0;
 
PULSE P1 (      Clock,Reset, 1'b1, wSrc0_DependencyLatch_Pre, wSrc0_DependencyLatch);
PULSE P2 (      Clock,Reset, 1'b1, wSrc1_DependencyLatch_Pre, wSrc1_DependencyLatch);
 
wire wWaitingForCommitGranted;
UPCOUNTER_POSEDGE # ( 1 ) FFD_101
( Clock, Reset,  1'b0, (oBusy & (iCommitGranted ^ wDependencyResolved)  ), wWaitingForCommitGranted );
 
UPCOUNTER_POSEDGE # ( 1 ) FFD_10
( Clock, Reset,  1'b0, wSrc0_DependencyLatch | wDependencyResolved, wSrc0_DependencyResolved );
 
UPCOUNTER_POSEDGE # ( 1 ) FFD_11
( Clock, Reset,  1'b0, wSrc1_DependencyLatch | wDependencyResolved,  wSrc1_DependencyResolved );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP0
( Clock, Reset, wSrc1_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc1_Fwd );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP1
( Clock, Reset, wSrc0_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc0_Fwd );
 
 
//assign oBusy = wWaitingDependency;
UPCOUNTER_POSEDGE # ( 1 ) BUSY
(
        .Clock(    Clock                                                                           ),
        .Reset(    Reset                                                                           ),
        .Enable(   wSrc0_Dependency_Initial | wSrc1_Dependency_Initial |   ((wWaitingForCommitGranted|wDependencyResolved)/*WaitingDependency*/ & iCommitGranted)     ),//***
        .Initial( 1'b0                                                                             ),
        .Q(        oBusy                                                              )
);
 
wire wCommitRequest;
UPCOUNTER_POSEDGE # ( 1 ) CRQ
(
        .Clock(    Clock                                                                           ),
        .Reset(    Reset                                                                           ),
        .Enable(   oTrigger |  iCommitGranted ),
        .Initial( 1'b0                                                                             ),
        .Q(        wCommitRequest                                                              )
);
assign oCommitRequest = oTrigger | (wCommitRequest & ~iCommitGranted);
 
assign oResult      = iResult;
assign oSource1    = (wWaitingDependency) ? ((wSrc1_Dependency)? (wSrc1_Fwd):wSrc1) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
assign oSource0    = (wWaitingDependency) ? ((wSrc0_Dependency)? (wSrc0_Fwd):wSrc0) : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
 
 
UPCOUNTER_POSEDGE # ( 1 ) DEP
(
        .Clock(    Clock                                                                           ),
        .Reset(    Reset                                                                           ),
        .Enable(   wSrc0_Dependency_Initial | wSrc1_Dependency_Initial |  wDependencyResolved      ),//***
        .Initial( 1'b0                                                                             ),
        .Q(        wWaitingDependency                                                              )
);
 
UPCOUNTER_POSEDGE # ( 1 ) DEPA
(
        .Clock(    Clock                                                     ),
        .Reset(    Reset                                                     ),
        .Enable(   wSrc0_Dependency_Initial |  wSrc0_DependencyResolved      ),
        .Initial(  1'b0                                                      ),
        .Q(        wSrc0_Dependency                                          )
);
 
UPCOUNTER_POSEDGE # ( 1 ) DEPB
(
        .Clock(    Clock                                                     ),
        .Reset(    Reset                                                     ),
        .Enable(   wSrc1_Dependency_Initial |  wSrc1_DependencyResolved      ),
        .Initial(  1'b0                                                      ),
        .Q(        wSrc1_Dependency                                          )
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
(       Clock, Reset, wHandleCurrentIssue , iIssueBus, {oId,oDestination,oWE,oScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
 
endmodule
 
//-------------------------------------------------------------------------------------------------

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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_ReservationStation.v] - Blame information for rev 230

Line No.	Rev	Author	Line
1	213	diegovalve	`include "aDefinitions.v"
2			`module ReservationStation`
3			`(`
4			`input wire Clock,`
5			`input wire Reset,`
6			input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
7			input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
8			`input wire [3:0] iMyId,`
9			`input wire iExecutionDone,`
10			`input wire iCommitGranted,`
11			input wire [`DATA_ROW_WIDTH-1:0] iResult,
12			output wire [`DATA_ROW_WIDTH-1:0] oSource1,
13			output wire [`DATA_ROW_WIDTH-1:0] oSource0,
14	230	diegovalve	`output wire [2:0] oScale,`
15	213	diegovalve	output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
16			output wire [`DATA_ROW_WIDTH-1:0] oResult,
17			`output wire [2:0] oWE,`
18			`output wire [3:0] oId,`
19			`output wire oBusy,`
20			`output wire oTrigger,`
21	230	diegovalve	`output wire oCommitRequest,`
22	213	diegovalve	output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
23
24			`);`
25
26			`wire wStall;`
27			`wire wLatchRequest;`
28			`wire [3:0] wSource1_RS;`
29			`wire [3:0] wSource0_RS;`
30			`//wire [3:0] wMyId;`
31			`wire wTrigger;`
32			`//wire wFIFO_Pop;`
33
34			wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
35			wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
36			`wire [3:0] wID;`
37			`wire [2:0] wWE;`
38			`wire wCommitFifoFull;`
39			wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
40
41	230	diegovalve	`assign oScale = wScale;`
42	213	diegovalve	`//assign wFIFO_Pop = iExecutionDone;`
43			`assign oCommitRequest = iExecutionDone;`
44			assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
45			`//If there are no dependencies then just trigger execution`
46			//assign oTrigger = (wTrigger /&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)/ ) ? 1'b1 : 0;
47			`assign oTrigger = ( (wLatchRequest \| wLatchData0FromCommitBus \| wLatchData1FromCommitBus) & ~wStall);`
48
49			assign wStall = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 \|\| iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
50			`//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;`
51
52			`wire wLatchData0FromCommitBus;`
53			`wire wLatchData1FromCommitBus;`
54
55
56			assign wLatchData0FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
57			assign wLatchData1FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
58
59			`wire wBusy;`
60			`assign oBusy = wBusy \| wCommitFifoFull & ~iCommitGranted;`
61			`wire wCommitGrantedDelay;`
62
63			`UPCOUNTER_POSEDGE # ( 1 ) BUSY`
64			`(`
65			`.Clock( Clock ),`
66			`.Reset( Reset ),`
67			`.Enable( wLatchRequest \| iCommitGranted ),`
68			`.Initial( 1'b0 ),`
69			`.Q( wBusy )`
70			`);`
71
72
73
74
75
76			assign oSource1 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
77			assign oSource0 = (wLatchData1FromCommitBus) ? (/(wDstZero)?`DATA_ROW_WIDTH'b0:/iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
78			`assign wTrigger = ( wLatchRequest \| wLatchData0FromCommitBus \| wLatchData1FromCommitBus);`
79
80
81			wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
82			//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
83			`//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );`
84
85			`wire [3:0] wScale;`
86			FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
87	230	diegovalve	`( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );`
88
89			`assign oSrc0Latched = wSrc0;`
90	213	diegovalve	`assign oSrc1Latched = wSrc1;`
91
92			assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
93			assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
94
95			sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
96			`(`
97			`.clk( Clock ),`
98			`.reset( Reset ),`
99			`.din( {wID,wWE,wDestination,iResult} ),`
100			`.wr_en( iExecutionDone ),`
101			`.rd_en( iCommitGranted ),`
102			`.dout( {oId,oWE,oDestination,oResult} ),`
103			`.full( wCommitFifoFull )`
104
105			`);`
106
107			`/*`
108			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger`
109			`( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );`
110
111			`*/`
112	230	diegovalve	`endmodule`
113
114			`module ReservationStation_EX`
115			`(`
116			`input wire Clock,`
117			`input wire Reset,`
118			input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
119			input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
120			`input wire [3:0] iMyId,`
121			`input wire iExecutionDone,`
122			`input wire iCommitGranted,`
123			input wire [`DATA_ROW_WIDTH-1:0] iResult,
124			output wire [`DATA_ROW_WIDTH-1:0] oSource1,
125			output wire [`DATA_ROW_WIDTH-1:0] oSource0,
126			`output wire [2:0] oScale,`
127			output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
128			output wire [`DATA_ROW_WIDTH-1:0] oResult,
129			`output wire [2:0] oWE,`
130			`output wire [3:0] oId,`
131			`output wire oBusy,`
132			`output wire oTrigger,`
133			`output wire oCommitRequest,`
134			output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
135
136			`);`
137
138			`wire wStall;`
139			`wire wLatchRequest;`
140			`wire [3:0] wSource1_RS;`
141			`wire [3:0] wSource0_RS;`
142			`//wire [3:0] wMyId;`
143			`wire wTrigger;`
144			`//wire wFIFO_Pop;`
145
146			wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
147			wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
148			`wire [3:0] wID;`
149			`wire [2:0] wWE;`
150			`wire wCommitFifoFull;`
151			wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
152
153			`assign oScale = wScale;`
154			`//assign wFIFO_Pop = iExecutionDone;`
155			`assign oCommitRequest = iExecutionDone;`
156			assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
157			`//If there are no dependencies then just trigger execution`
158			//assign oTrigger = (wTrigger /&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)/ ) ? 1'b1 : 0;
159
160			`wire wTrigger_Pre,wTrigger_Delay,DependencyResolved_Delay;`
161
162			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDXXX`
163			`( Clock, Reset, 1'b1 , wTrigger_Pre, wTrigger_Delay );`
164
165			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDYYY`
166			`( Clock, Reset, 1'b1 , DependencyResolved, DependencyResolved_Delay );`
167
168			`assign wTrigger_Pre = ((wLatchRequest & ~wStall) \| DependencyResolved);//( (wLatchRequest \| wLatchData0FromCommitBus \| wLatchData1FromCommitBus) & ~wStall);`
169
170			`//////////////HERE!!!!!!!!!!!!!!!!!!!!!`
171			`//assign oTrigger = wTrigger_Pre;//(DependencyResolved) ? wTrigger_Pre : wTrigger_Delay;`
172			`assign oTrigger = (DependencyResolved) ? wTrigger_Pre : (wTrigger_Delay & ~DependencyResolved_Delay);`
173			`//////////////HERE!!!!!!!!!!!!!!!!!!!!!`
174
175
176
177			//assign wStall = (/wLatchRequest/(wBusy\|\|wLatchRequest) && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 \|\| iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
178
179			///assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 \|\| iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) \|\|
180			`//((wBusy ) && (wSource1_RS != 0 \|\| wSource0_RS != 0) ) ) ? 1'b1 : 1'b0;`
181			`wire DependencyDetected,DependencyResolved, wStall_Pre;`
182			assign DependencyDetected = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 \|\| iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0));
183			`assign DependencyResolved = ( wLatchData0FromCommitBus \|\| wLatchData1FromCommitBus );`
184
185			`UPCOUNTER_POSEDGE # ( 1 ) STALL`
186			`(`
187			`.Clock( Clock ),`
188			`.Reset( Reset ),`
189			`.Enable( DependencyDetected \| DependencyResolved ),`
190			`.Initial( 1'b0 ),`
191			`.Q( wStall_Pre )`
192			`);`
193
194			assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 \|\| iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) \|\| wStall_Pre);
195
196
197			`//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;`
198
199			`wire wLatchData0FromCommitBus;`
200			`wire wLatchData1FromCommitBus;`
201
202
203			assign wLatchData0FromCommitBus = ((wSource0_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
204			assign wLatchData1FromCommitBus = ((wSource1_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
205
206			`wire wBusy;`
207			`assign oBusy = wBusy \| wCommitFifoFull & ~iCommitGranted;`
208			`wire wCommitGrantedDelay;`
209
210			`UPCOUNTER_POSEDGE # ( 1 ) BUSY`
211			`(`
212			`.Clock( Clock ),`
213			`.Reset( Reset ),`
214			`.Enable( wLatchRequest \| iCommitGranted ),`
215			`.Initial( 1'b0 ),`
216			`.Q( wBusy )`
217			`);`
218
219
220
221
222
223			assign oSource0 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
224			assign oSource1 = (wLatchData1FromCommitBus) ? (iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
225			`assign wTrigger = ( wLatchRequest \| wLatchData0FromCommitBus \| wLatchData1FromCommitBus);`
226
227
228			wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
229			//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
230			`//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );`
231
232			`wire [3:0] wScale;`
233			FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
234			`( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );`
235
236
237			`assign oSrc0Latched = (wLatchData0FromCommitBus)? oSource0 : wSrc0;`
238			`assign oSrc1Latched = (wLatchData1FromCommitBus)? oSource1 : wSrc1;`
239
240			assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
241			assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
242
243			sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
244			`(`
245			`.clk( Clock ),`
246			`.reset( Reset ),`
247			`.din( {wID,wWE,wDestination,iResult} ),`
248			`.wr_en( iExecutionDone ),`
249			`.rd_en( iCommitGranted ),`
250			`.dout( {oId,oWE,oDestination,oResult} ),`
251			`.full( wCommitFifoFull )`
252
253			`);`
254
255			`/*`
256			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger`
257			`( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );`
258
259			`*/`
260	213	diegovalve	`endmodule`
261
262			`//-------------------------------------------------------------------------------------------------`
263			`module ReservationStation_1Cycle`
264			`(`
265			`input wire Clock,`
266			`input wire Reset,`
267			input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
268			input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
269			`input wire [3:0] iMyId,`
270			`input wire iExecutionDone,`
271			`input wire iCommitGranted,`
272			input wire [`DATA_ROW_WIDTH-1:0] iResult,
273			output wire [`DATA_ROW_WIDTH-1:0] oSource1,
274			output wire [`DATA_ROW_WIDTH-1:0] oSource0,
275			output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
276			output wire [`DATA_ROW_WIDTH-1:0] oResult,
277			output wire [`SCALE_SIZE-1:0] oScale,
278			`output wire [2:0] oWE,`
279			`output wire [3:0] oId,`
280			`output wire oBusy,`
281			`output wire oTrigger,`
282			`output wire oCommitRequest`
283
284			`);`
285
286
287			`wire [3:0] wSource1_RS;`
288			`wire [3:0] wSource0_RS;`
289			`wire [3:0] wMyId;`
290			`wire wTrigger;`
291			wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
292			`wire [3:0] wID;`
293			`wire [2:0] wWE;`
294			wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0,wResult;
295			`//wire wDstZero;`
296			wire [`DATA_ROW_WIDTH-1:0] wSrc1_Fwd;
297			wire [`DATA_ROW_WIDTH-1:0] wSrc0_Fwd;
298
299			`wire wSrc0_Dependency_Initial, wSrc0_Dependency;`
300			`wire wSrc1_Dependency_Initial, wSrc1_Dependency;`
301			`wire wSrc0_DependencyResolved, wSrc0_DependencyLatch;`
302			`wire wSrc1_DependencyResolved, wSrc1_DependencyLatch;`
303			`wire wWaitingDependency;`
304			`wire wHandleCurrentIssue;`
305			`wire wDependencyResolved;`
306			wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
307			`wire wSrc0_DependencyLatch_Pre,wSrc1_DependencyLatch_Pre;`
308
309			assign wHandleCurrentIssue = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
310			`assign wSrc0_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[96] \| iIssueBus[97] \| iIssueBus[98] \| iIssueBus[99]);`
311			`assign wSrc1_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[196] \| iIssueBus[197] \| iIssueBus[198] \| iIssueBus[199]);`
312
313
314			`assign oTrigger =`
315			`(~wWaitingDependency & wHandleCurrentIssue & ~wSrc0_Dependency_Initial & ~wSrc1_Dependency_Initial)`
316			`\|(wWaitingDependency & ~wSrc1_Dependency & wSrc0_Dependency & wSrc0_DependencyResolved )`
317			`\|(wWaitingDependency & wSrc1_Dependency & ~wSrc0_Dependency & wSrc1_DependencyResolved )`
318			`\|(wWaitingDependency & wSrc1_Dependency & wSrc0_Dependency & wSrc1_DependencyResolved & wSrc0_DependencyResolved );`
319
320			`assign wDependencyResolved = wWaitingDependency & ~wSrc1_Dependency & ~wSrc0_Dependency;`
321
322			assign wSrc0_DependencyLatch_Pre = ( wSrc0_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag0) ) ? 1'b1 : 1'b0;
323			assign wSrc1_DependencyLatch_Pre = ( wSrc1_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag1) ) ? 1'b1 : 1'b0;
324
325			`PULSE P1 ( Clock,Reset, 1'b1, wSrc0_DependencyLatch_Pre, wSrc0_DependencyLatch);`
326			`PULSE P2 ( Clock,Reset, 1'b1, wSrc1_DependencyLatch_Pre, wSrc1_DependencyLatch);`
327
328			`wire wWaitingForCommitGranted;`
329			`UPCOUNTER_POSEDGE # ( 1 ) FFD_101`
330			`( Clock, Reset, 1'b0, (oBusy & (iCommitGranted ^ wDependencyResolved) ), wWaitingForCommitGranted );`
331
332			`UPCOUNTER_POSEDGE # ( 1 ) FFD_10`
333			`( Clock, Reset, 1'b0, wSrc0_DependencyLatch \| wDependencyResolved, wSrc0_DependencyResolved );`
334
335			`UPCOUNTER_POSEDGE # ( 1 ) FFD_11`
336			`( Clock, Reset, 1'b0, wSrc1_DependencyLatch \| wDependencyResolved, wSrc1_DependencyResolved );`
337
338			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP0
339			( Clock, Reset, wSrc1_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc1_Fwd );
340
341			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP1
342			( Clock, Reset, wSrc0_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc0_Fwd );
343
344
345			`//assign oBusy = wWaitingDependency;`
346			`UPCOUNTER_POSEDGE # ( 1 ) BUSY`
347			`(`
348			`.Clock( Clock ),`
349			`.Reset( Reset ),`
350			`.Enable( wSrc0_Dependency_Initial \| wSrc1_Dependency_Initial \| ((wWaitingForCommitGranted\|wDependencyResolved)/WaitingDependency/ & iCommitGranted) ),//***`
351			`.Initial( 1'b0 ),`
352			`.Q( oBusy )`
353			`);`
354
355			`wire wCommitRequest;`
356			`UPCOUNTER_POSEDGE # ( 1 ) CRQ`
357			`(`
358			`.Clock( Clock ),`
359			`.Reset( Reset ),`
360			`.Enable( oTrigger \| iCommitGranted ),`
361			`.Initial( 1'b0 ),`
362			`.Q( wCommitRequest )`
363			`);`
364			`assign oCommitRequest = oTrigger \| (wCommitRequest & ~iCommitGranted);`
365
366			`assign oResult = iResult;`
367			assign oSource1 = (wWaitingDependency) ? ((wSrc1_Dependency)? (wSrc1_Fwd):wSrc1) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
368			assign oSource0 = (wWaitingDependency) ? ((wSrc0_Dependency)? (wSrc0_Fwd):wSrc0) : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
369
370
371			`UPCOUNTER_POSEDGE # ( 1 ) DEP`
372			`(`
373			`.Clock( Clock ),`
374			`.Reset( Reset ),`
375			`.Enable( wSrc0_Dependency_Initial \| wSrc1_Dependency_Initial \| wDependencyResolved ),//***`
376			`.Initial( 1'b0 ),`
377			`.Q( wWaitingDependency )`
378			`);`
379
380			`UPCOUNTER_POSEDGE # ( 1 ) DEPA`
381			`(`
382			`.Clock( Clock ),`
383			`.Reset( Reset ),`
384			`.Enable( wSrc0_Dependency_Initial \| wSrc0_DependencyResolved ),`
385			`.Initial( 1'b0 ),`
386			`.Q( wSrc0_Dependency )`
387			`);`
388
389			`UPCOUNTER_POSEDGE # ( 1 ) DEPB`
390			`(`
391			`.Clock( Clock ),`
392			`.Reset( Reset ),`
393			`.Enable( wSrc1_Dependency_Initial \| wSrc1_DependencyResolved ),`
394			`.Initial( 1'b0 ),`
395			`.Q( wSrc1_Dependency )`
396			`);`
397
398
399			FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
400			`( Clock, Reset, wHandleCurrentIssue , iIssueBus, {oId,oDestination,oWE,oScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );`
401
402			assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
403			assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
404
405			`endmodule`
406
407			`//-------------------------------------------------------------------------------------------------`