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diegovalve |
`timescale 1ns / 1ps
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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//--------------------------------------------------------
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module THEIA
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(
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input wire Clock,
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input wire Reset,
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input wire iEnable,
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input wire [31:0] iMemReadData,
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input wire iMemDataAvailable,
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output wire [31:0] oMemReadAddress,
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output wire oMEM_ReadRequest
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);
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wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteAddress;
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wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteData;
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wire [`MAX_CORES-1:0] wMCU_2_VP_InstructionWriteEnable;
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wire [`MCU_TAG_SIZE-1:0] wMCU_2_VP_Tag;
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wire wMCU_2_VP_STB;
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wire wMCU_2_VP_Cyc;
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wire wMCU_2_VP_Mst;
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wire [`MAX_CORES-1:0] wVP_2_MCU_ACK;
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wire wVP_Slave_ACK;
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wire [`MCU_REQUEST_SIZE-1:0] wCP_2MCU_BlockCopyCommand;
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wire[`CBC_BUS_WIDTH-1:0] wCP_VP__ControlCommandBus;
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wire wMCU_2_CP__FIFOEmpty;
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wire wOMem_WE[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
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//////////////////////////////////////////////
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//
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// The control processor
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//
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//////////////////////////////////////////////
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ControlProcessor CP
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.oControlBus( wCP_VP__ControlCommandBus ),
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.iMCUFifoEmpty( wMCU_2_CP__FIFOEmpty ),
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.oCopyBlockCommand( wCP_2MCU_BlockCopyCommand )
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);
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//////////////////////////////////////////////
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//
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// The control processor
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//
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//////////////////////////////////////////////
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assign wVP_Slave_ACK = wVP_2_MCU_ACK[0] | wVP_2_MCU_ACK[1] | wVP_2_MCU_ACK[2] | wVP_2_MCU_ACK[3];
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MemoryController #(`MAX_CORES) MCU
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iRequest( wCP_2MCU_BlockCopyCommand ),
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.oMEM_ReadAddress( oMemReadAddress ),
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.oMEM_ReadRequest( oMEM_ReadRequest ),
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.oFifoEmpty( wMCU_2_CP__FIFOEmpty ),
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.iMEM_ReadData( iMemReadData ),
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.iMEM_DataAvailable( iMemDataAvailable ),
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.DAT_O( wMCU_2_VP_InstructionWriteData ),
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.ADR_O( wMCU_2_VP_InstructionWriteAddress ),
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.STB_O( wMCU_2_VP_STB ),
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.WE_O( wMCU_2_VP_InstructionWriteEnable ),
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.TAG_O( wMCU_2_VP_Tag ),
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.CYC_O( wMCU_2_VP_Cyc ),
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.MST_O( wMCU_2_VP_Mst ),
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.ACK_I( wVP_Slave_ACK )
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);
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//////////////////////////////////////////////
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//
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// The vector processors
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//
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//////////////////////////////////////////////
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genvar i;
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generate
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for (i = 0; i < `MAX_CORES; i = i +1)
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begin : VPX
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VectorProcessor VP
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iEnable( iEnable ),
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.iVPID( i+1 ),
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.iCpCommand( wCP_VP__ControlCommandBus ),
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.MCU_STB_I( wMCU_2_VP_STB ),
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.MCU_WE_I( wMCU_2_VP_InstructionWriteEnable[i] ),
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.MCU_DAT_I( wMCU_2_VP_InstructionWriteData ),
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.MCU_ADR_I( wMCU_2_VP_InstructionWriteAddress ),
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.MCU_TAG_I( wMCU_2_VP_Tag ),
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.MCU_ACK_O( wVP_2_MCU_ACK[i] ),
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.MCU_MST_I( wMCU_2_VP_Mst ),
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.MCU_CYC_I( wMCU_2_VP_Cyc ),
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.OMEM_WE( wOMem_WE[i] ),
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.OMEM_ADDR( wOMEM_Address[i] ),
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.OMEM_DATA( wOMEM_Dat[i] )
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);
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, `OMEM_SIZE ) OMEM
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(
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.Clock( Clock ),
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.iWriteEnable( wOMem_WE[i] ),
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.iWriteAddress( wOMEM_Address[i] ),
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.iDataIn( wOMEM_Dat[i] ),
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.iReadAddress0( wOMEM_Address[i] )
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//.oDataOut0( wOMEM_Dat[i] )
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);
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end // for
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endgenerate
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endmodule
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