| 1 |
213 |
diegovalve |
|
| 2 |
|
|
`include "aDefinitions.v"
|
| 3 |
|
|
|
| 4 |
|
|
/**********************************************************************************
|
| 5 |
|
|
Theia, Ray Cast Programable graphic Processing Unit.
|
| 6 |
|
|
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
|
| 7 |
|
|
|
| 8 |
|
|
This program is free software; you can redistribute it and/or
|
| 9 |
|
|
modify it under the terms of the GNU General Public License
|
| 10 |
|
|
as published by the Free Software Foundation; either version 2
|
| 11 |
|
|
of the License, or (at your option) any later version.
|
| 12 |
|
|
|
| 13 |
|
|
This program is distributed in the hope that it will be useful,
|
| 14 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 15 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 16 |
|
|
GNU General Public License for more details.
|
| 17 |
|
|
|
| 18 |
|
|
You should have received a copy of the GNU General Public License
|
| 19 |
|
|
along with this program; if not, write to the Free Software
|
| 20 |
|
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 21 |
|
|
|
| 22 |
|
|
***********************************************************************************/
|
| 23 |
|
|
|
| 24 |
|
|
module Unit_Execution
|
| 25 |
|
|
(
|
| 26 |
|
|
input wire Clock,
|
| 27 |
|
|
input wire Reset,
|
| 28 |
|
|
input wire iEnable,
|
| 29 |
|
|
input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
|
| 30 |
|
|
input wire iInstructionMem_WriteEnable,
|
| 31 |
|
|
input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
|
| 32 |
|
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
|
| 33 |
|
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
|
| 34 |
|
|
output wire oOMEMWriteEnable
|
| 35 |
|
|
|
| 36 |
|
|
);
|
| 37 |
|
|
|
| 38 |
|
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
|
| 39 |
|
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP1;
|
| 40 |
|
|
wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction0;
|
| 41 |
|
|
wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction1;
|
| 42 |
|
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr0;
|
| 43 |
|
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr1;
|
| 44 |
|
|
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
|
| 45 |
|
|
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
|
| 46 |
|
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
|
| 47 |
|
|
wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus,wModIssue;
|
| 48 |
|
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
|
| 49 |
|
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
|
| 50 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
|
| 51 |
|
|
wire [`MOD_COMMIT_PACKET_SIZE-1:0] wModCommitBus;
|
| 52 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder0;
|
| 53 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder1;
|
| 54 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Div;
|
| 55 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Mul;
|
| 56 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Sqrt;
|
| 57 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Logic;
|
| 58 |
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_IO;
|
| 59 |
|
|
wire wZeroFlag;
|
| 60 |
|
|
wire wSignFlag;
|
| 61 |
|
|
wire [`DATA_ADDRESS_WIDTH-1:0] wFrameOffset,wIndexRegister;
|
| 62 |
|
|
wire [`WIDTH-1:0] wThreadControl;
|
| 63 |
|
|
|
| 64 |
|
|
// The Register File
|
| 65 |
|
|
RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
|
| 66 |
|
|
(
|
| 67 |
|
|
.Clock( Clock ),
|
| 68 |
|
|
.Reset( Reset ),
|
| 69 |
|
|
.iWriteEnable( wCommitBus[`COMMIT_WE_RNG] ),
|
| 70 |
|
|
.iReadAddress0( wII_2_RF_Addr0 ),
|
| 71 |
|
|
.iReadAddress1( wII_2_RF_Addr1 ),
|
| 72 |
|
|
.iWriteAddress( wCommitBus[`COMMIT_DST_RNG] ),
|
| 73 |
|
|
.oFrameOffset( wFrameOffset ),
|
| 74 |
|
|
.oIndexRegister( wIndexRegister ),
|
| 75 |
|
|
.oThreadControlRegister( wThreadControl ),
|
| 76 |
|
|
.iData( wCommitBus[`COMMIT_DATA_RNG] ),
|
| 77 |
|
|
.oData0( wRF_2_II_Data0 ),
|
| 78 |
|
|
.oData1( wRF_2_II_Data1 )
|
| 79 |
|
|
);
|
| 80 |
|
|
|
| 81 |
|
|
|
| 82 |
|
|
|
| 83 |
|
|
|
| 84 |
|
|
//Code bank 0
|
| 85 |
|
|
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
|
| 86 |
|
|
(
|
| 87 |
|
|
.Clock( Clock ),
|
| 88 |
|
|
.iWriteEnable( iInstructionMem_WriteEnable ),
|
| 89 |
|
|
.iReadAddress0( wII0_IP0 ),
|
| 90 |
|
|
.iReadAddress1( wII1_IP0 ),
|
| 91 |
|
|
.iWriteAddress( iInstructionMem_WriteAddress ),
|
| 92 |
|
|
.iDataIn( iInstructionMem_WriteData ),
|
| 93 |
|
|
.oDataOut0( wInstrThread0 ),
|
| 94 |
|
|
.oDataOut1( wInstrThread1 )
|
| 95 |
|
|
);
|
| 96 |
|
|
|
| 97 |
|
|
|
| 98 |
|
|
//**********************************************
|
| 99 |
|
|
parameter MaxThreads = 3;
|
| 100 |
|
|
wire [MaxThreads-1:0] wDelay;
|
| 101 |
|
|
|
| 102 |
|
|
|
| 103 |
|
|
UPCOUNTER_POSEDGE # (MaxThreads) UP111
|
| 104 |
|
|
(
|
| 105 |
|
|
.Clock( Clock), .Reset( Reset),
|
| 106 |
|
|
.Initial(0),
|
| 107 |
|
|
.Enable(1'b1),
|
| 108 |
|
|
.Q(wDelay)
|
| 109 |
|
|
);
|
| 110 |
|
|
|
| 111 |
|
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII0_IP0,wII0_IP1;
|
| 112 |
|
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII1_IP0,wII1_IP1;
|
| 113 |
|
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII0_RF_Addr0,wII0_RF_Addr1;
|
| 114 |
|
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII1_RF_Addr0,wII1_RF_Addr1;
|
| 115 |
|
|
wire [`ISSUE_PACKET_SIZE-1:0] wII0_IBus,wII1_IBus;
|
| 116 |
|
|
|
| 117 |
|
|
|
| 118 |
|
|
assign wII_2_RF_Addr0 = (wCurrentActiveThread[0]) ? wII0_RF_Addr0 : wII1_RF_Addr0;
|
| 119 |
|
|
|
| 120 |
|
|
assign wII_2_RF_Addr1 = (wCurrentActiveThread[0]) ? wII0_RF_Addr1 : wII1_RF_Addr1;
|
| 121 |
|
|
|
| 122 |
|
|
assign wIssueBus = (wCurrentActiveThread[0]) ? wII0_IBus: wII1_IBus;
|
| 123 |
|
|
|
| 124 |
|
|
|
| 125 |
|
|
wire [`MAX_THREADS-1:0] wCurrentActiveThread,wCurrentActiveThread_Pre,wCurrentActiveThread_Pre2;
|
| 126 |
|
|
|
| 127 |
|
|
CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
|
| 128 |
|
|
(
|
| 129 |
|
|
.Clock( Clock ),
|
| 130 |
|
|
.Reset( Reset ),
|
| 131 |
|
|
.Initial(`MAX_THREADS'b1),
|
| 132 |
|
|
.Enable( wDelay[0] /*& wDelay[1]*/ & wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
|
| 133 |
|
|
.O( wCurrentActiveThread_Pre )
|
| 134 |
|
|
);
|
| 135 |
|
|
|
| 136 |
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
|
| 137 |
|
|
( Clock, Reset, 1'b1 , wCurrentActiveThread_Pre , wCurrentActiveThread_Pre2 );
|
| 138 |
|
|
|
| 139 |
|
|
assign wCurrentActiveThread = (wThreadControl[`SPR_TCONTROL0_MT_ENABLED]) ? wCurrentActiveThread_Pre2 : `MAX_THREADS'b1;
|
| 140 |
|
|
|
| 141 |
|
|
|
| 142 |
|
|
//**********************************************
|
| 143 |
|
|
wire [`INSTRUCTION_WIDTH-1:0] wInstrThread0;
|
| 144 |
|
|
//When the thread is inactive I want to keep this input just the way it was,
|
| 145 |
|
|
//sort of "time freezing"...
|
| 146 |
|
|
|
| 147 |
|
|
|
| 148 |
|
|
|
| 149 |
|
|
InstructionIssue II0
|
| 150 |
|
|
(
|
| 151 |
|
|
.Clock( Clock ),
|
| 152 |
|
|
.Reset( Reset ),
|
| 153 |
|
|
.iEnable( wCurrentActiveThread[0] & iEnable),
|
| 154 |
|
|
.iFrameOffset( wFrameOffset ),
|
| 155 |
|
|
/* New Apr 06*/.iCodeOffset( `INSTRUCTION_ADDR_WIDTH'b0 ),
|
| 156 |
|
|
.iMtEnabled(wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
|
| 157 |
|
|
.iIndexRegister( wIndexRegister ),
|
| 158 |
|
|
.iInstruction0( wInstrThread0 ),
|
| 159 |
|
|
// .iInstruction1( wIM_2_II_Instruction1 ),
|
| 160 |
|
|
.iSourceData0( wRF_2_II_Data0 ),
|
| 161 |
|
|
.iSourceData1( wRF_2_II_Data1 ),
|
| 162 |
|
|
.iRStationBusy( wRS_2_II_Busy ),
|
| 163 |
|
|
.iResultBcast( wCommitBus ),
|
| 164 |
|
|
.iSignFlag( wSignFlag ),
|
| 165 |
|
|
.iZeroFlag( wZeroFlag ),
|
| 166 |
|
|
.iIgnoreResultBcast( wResultBCastDst[7] & wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
|
| 167 |
|
|
.oSourceAddress0( wII0_RF_Addr0 ),//wII_2_RF_Addr0 ),
|
| 168 |
|
|
.oSourceAddress1( wII0_RF_Addr1 ),//wII_2_RF_Addr1 ),
|
| 169 |
|
|
.oIssueBcast( wII0_IBus ),//wIssueBus ),
|
| 170 |
|
|
.oIP0( wII0_IP0 )//wII_2_IM_IP0 ),
|
| 171 |
|
|
//.oIP1( wII0_IP1 )//wII_2_IM_IP1 )
|
| 172 |
|
|
|
| 173 |
|
|
);
|
| 174 |
|
|
|
| 175 |
|
|
|
| 176 |
|
|
|
| 177 |
|
|
wire [`INSTRUCTION_WIDTH-1:0] wInstrThread1;
|
| 178 |
|
|
//When the thread is inactive I want to keep this input just the way it was,
|
| 179 |
|
|
//sort of "time freezing"...
|
| 180 |
|
|
|
| 181 |
|
|
//Add the offset to the thread instructions... 1 16 bit adder wasted :(
|
| 182 |
|
|
//assign wInstrThread1 = wInstrThread1_Pre;
|
| 183 |
|
|
|
| 184 |
|
|
wire [`DATA_ADDRESS_WIDTH-1:0] wResultBCastDst;
|
| 185 |
|
|
assign wResultBCastDst = wCommitBus[`COMMIT_DST_RNG];
|
| 186 |
|
|
|
| 187 |
|
|
|
| 188 |
|
|
InstructionIssue II1
|
| 189 |
|
|
(
|
| 190 |
|
|
.Clock( Clock ),
|
| 191 |
|
|
.Reset( Reset || ~wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
|
| 192 |
|
|
.iEnable( wCurrentActiveThread[1] & iEnable ),
|
| 193 |
|
|
.iFrameOffset( wFrameOffset ),
|
| 194 |
|
|
.iCodeOffset( wThreadControl[`SPR_TCONTROL0_T0_INST_OFFSET_RNG] ),
|
| 195 |
|
|
.iMtEnabled( wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
|
| 196 |
|
|
.iIndexRegister( wIndexRegister ),
|
| 197 |
|
|
.iInstruction0( wInstrThread1 ),
|
| 198 |
|
|
.iSourceData0( wRF_2_II_Data0 ),
|
| 199 |
|
|
.iSourceData1( wRF_2_II_Data1 ),
|
| 200 |
|
|
.iRStationBusy( wRS_2_II_Busy ),
|
| 201 |
|
|
.iResultBcast( wCommitBus ),
|
| 202 |
|
|
.iSignFlag( wSignFlag ),
|
| 203 |
|
|
.iZeroFlag( wZeroFlag ),
|
| 204 |
|
|
|
| 205 |
|
|
.iIgnoreResultBcast( ~wResultBCastDst[7] ),
|
| 206 |
|
|
.oSourceAddress0( wII1_RF_Addr0 ),
|
| 207 |
|
|
.oSourceAddress1( wII1_RF_Addr1 ),
|
| 208 |
|
|
.oIssueBcast( wII1_IBus ),
|
| 209 |
|
|
.oIP0( wII1_IP0 )
|
| 210 |
|
|
//.oIP1( wII1_IP1 )
|
| 211 |
|
|
|
| 212 |
|
|
);
|
| 213 |
|
|
|
| 214 |
|
|
|
| 215 |
|
|
|
| 216 |
|
|
OperandModifiers SMU
|
| 217 |
|
|
(
|
| 218 |
|
|
.Clock( Clock ),
|
| 219 |
|
|
.Reset( Reset ),
|
| 220 |
|
|
.iIssueBus( wIssueBus ),
|
| 221 |
|
|
.iCommitBus( wCommitBus ),
|
| 222 |
|
|
.oModIssue( wModIssue ),
|
| 223 |
|
|
.oCommitBus( wModCommitBus )
|
| 224 |
|
|
|
| 225 |
|
|
);
|
| 226 |
|
|
|
| 227 |
|
|
assign wSignFlag = wCommitBus[`COMMIT_SIGN_X] & wCommitBus[`COMMIT_SIGN_Y] & wCommitBus[`COMMIT_SIGN_Z];
|
| 228 |
|
|
assign wZeroFlag = (wCommitBus[`COMMIT_DATA_RNG] == `DATA_ROW_WIDTH'b0) ? 1'b1 : 1'b0;
|
| 229 |
|
|
|
| 230 |
|
|
|
| 231 |
|
|
ADDER_STATION ADD_STA0
|
| 232 |
|
|
(
|
| 233 |
|
|
.Clock( Clock ),
|
| 234 |
|
|
.Reset( Reset ),
|
| 235 |
|
|
.iId( `RS_ADD0 ),
|
| 236 |
|
|
.iIssueBus( wModIssue ),
|
| 237 |
|
|
.iCommitBus( wModCommitBus ),
|
| 238 |
|
|
.oCommitData( wCommitData_Adder0 ),
|
| 239 |
|
|
.oCommitResquest( wStationCommitRequest[0] ),
|
| 240 |
|
|
.iCommitGranted( wStationCommitGrant[0] ),
|
| 241 |
|
|
.oBusy( wRS_2_II_Busy[ 0 ] )
|
| 242 |
|
|
|
| 243 |
|
|
);
|
| 244 |
|
|
|
| 245 |
|
|
ADDER_STATION ADD_STA1
|
| 246 |
|
|
(
|
| 247 |
|
|
.Clock( Clock ),
|
| 248 |
|
|
.Reset( Reset ),
|
| 249 |
|
|
.iId( `RS_ADD1 ),
|
| 250 |
|
|
.iIssueBus( wModIssue ),
|
| 251 |
|
|
.iCommitBus( wModCommitBus ),
|
| 252 |
|
|
.oCommitData( wCommitData_Adder1 ),
|
| 253 |
|
|
.oCommitResquest( wStationCommitRequest[1] ),
|
| 254 |
|
|
.iCommitGranted( wStationCommitGrant[1] ),
|
| 255 |
|
|
.oBusy( wRS_2_II_Busy[ 1 ] )
|
| 256 |
|
|
|
| 257 |
|
|
);
|
| 258 |
|
|
|
| 259 |
|
|
|
| 260 |
|
|
DIVISION_STATION DIV_STA
|
| 261 |
|
|
(
|
| 262 |
|
|
.Clock( Clock ),
|
| 263 |
|
|
.Reset( Reset ),
|
| 264 |
|
|
.iId( `RS_DIV ),
|
| 265 |
|
|
.iIssueBus( wModIssue ),
|
| 266 |
|
|
.iCommitBus( wModCommitBus ),
|
| 267 |
|
|
.oCommitData( wCommitData_Div ),
|
| 268 |
|
|
.oCommitResquest( wStationCommitRequest[2] ),
|
| 269 |
|
|
.iCommitGranted( wStationCommitGrant[2] ),
|
| 270 |
|
|
.oBusy( wRS_2_II_Busy[2] )
|
| 271 |
|
|
|
| 272 |
|
|
);
|
| 273 |
|
|
|
| 274 |
|
|
|
| 275 |
|
|
MUL_STATION MUL_STA
|
| 276 |
|
|
(
|
| 277 |
|
|
.Clock( Clock ),
|
| 278 |
|
|
.Reset( Reset ),
|
| 279 |
|
|
.iId( `RS_MUL ),
|
| 280 |
|
|
.iIssueBus( wModIssue ),
|
| 281 |
|
|
.iCommitBus( wModCommitBus ),
|
| 282 |
|
|
.oCommitData( wCommitData_Mul ),
|
| 283 |
|
|
.oCommitResquest( wStationCommitRequest[3] ),
|
| 284 |
|
|
.iCommitGranted( wStationCommitGrant[3] ),
|
| 285 |
|
|
.oBusy( wRS_2_II_Busy[3] )
|
| 286 |
|
|
|
| 287 |
|
|
);
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
SQRT_STATION SQRT_STA
|
| 291 |
|
|
(
|
| 292 |
|
|
.Clock( Clock ),
|
| 293 |
|
|
.Reset( Reset ),
|
| 294 |
|
|
.iId( `RS_SQRT ),
|
| 295 |
|
|
.iIssueBus( wModIssue ),
|
| 296 |
|
|
.iCommitBus( wModCommitBus ),
|
| 297 |
|
|
.oCommitData( wCommitData_Sqrt ),
|
| 298 |
|
|
.oCommitResquest( wStationCommitRequest[4] ),
|
| 299 |
|
|
.iCommitGranted( wStationCommitGrant[4] ),
|
| 300 |
|
|
.oBusy( wRS_2_II_Busy[4] )
|
| 301 |
|
|
|
| 302 |
|
|
);
|
| 303 |
|
|
|
| 304 |
|
|
|
| 305 |
|
|
|
| 306 |
|
|
LOGIC_STATION LOGIC_STA
|
| 307 |
|
|
(
|
| 308 |
|
|
.Clock( Clock ),
|
| 309 |
|
|
.Reset( Reset ),
|
| 310 |
|
|
.iId( `RS_LOGIC ),
|
| 311 |
|
|
.iIssueBus( wModIssue ),
|
| 312 |
|
|
.iCommitBus( wModCommitBus ),
|
| 313 |
|
|
.oCommitData( wCommitData_Logic ),
|
| 314 |
|
|
.oCommitResquest( wStationCommitRequest[5] ),
|
| 315 |
|
|
.iCommitGranted( wStationCommitGrant[5] ),
|
| 316 |
|
|
.oBusy( wRS_2_II_Busy[5] )
|
| 317 |
|
|
|
| 318 |
|
|
);
|
| 319 |
|
|
|
| 320 |
|
|
IO_STATION IO_STA
|
| 321 |
|
|
(
|
| 322 |
|
|
.Clock( Clock ),
|
| 323 |
|
|
.Reset( Reset ),
|
| 324 |
|
|
.iId( `RS_IO ),
|
| 325 |
|
|
.iIssueBus( wModIssue ),
|
| 326 |
|
|
.iCommitBus( wModCommitBus ),
|
| 327 |
|
|
.oCommitData( wCommitData_IO ),
|
| 328 |
|
|
.oCommitResquest( wStationCommitRequest[6] ),
|
| 329 |
|
|
.iCommitGranted( wStationCommitGrant[6] ),
|
| 330 |
|
|
.oBusy( wRS_2_II_Busy[6] ),
|
| 331 |
|
|
.oOMEMWriteAddress( oOMEMWriteAddress ),
|
| 332 |
|
|
.oOMEMWriteData( oOMEMWriteData ),
|
| 333 |
|
|
.oOMEMWriteEnable( oOMEMWriteEnable )
|
| 334 |
|
|
|
| 335 |
|
|
);
|
| 336 |
|
|
|
| 337 |
|
|
ROUND_ROBIN_7_ENTRIES ARB
|
| 338 |
|
|
//ROUND_ROBIN_6_ENTRIES ARB
|
| 339 |
|
|
(
|
| 340 |
|
|
.Clock( Clock ),
|
| 341 |
|
|
.Reset( Reset ),
|
| 342 |
|
|
.iRequest0( wStationCommitRequest[0] ),
|
| 343 |
|
|
.iRequest1( wStationCommitRequest[1] ),
|
| 344 |
|
|
.iRequest2( wStationCommitRequest[2] ),
|
| 345 |
|
|
.iRequest3( wStationCommitRequest[3] ),
|
| 346 |
|
|
.iRequest4( wStationCommitRequest[4] ),
|
| 347 |
|
|
.iRequest5( wStationCommitRequest[5] ),
|
| 348 |
|
|
.iRequest6( wStationCommitRequest[6] ),
|
| 349 |
|
|
.oGrant0( wStationCommitGrant[0] ),
|
| 350 |
|
|
.oGrant1( wStationCommitGrant[1] ),
|
| 351 |
|
|
.oGrant2( wStationCommitGrant[2] ),
|
| 352 |
|
|
.oGrant3( wStationCommitGrant[3] ),
|
| 353 |
|
|
.oGrant4( wStationCommitGrant[4] ),
|
| 354 |
|
|
.oGrant5( wStationCommitGrant[5] ),
|
| 355 |
|
|
.oGrant6( wStationCommitGrant[6] )
|
| 356 |
|
|
|
| 357 |
|
|
);
|
| 358 |
|
|
|
| 359 |
|
|
|
| 360 |
|
|
wire[3:0] wBusSelector;
|
| 361 |
|
|
DECODER_ONEHOT_2_BINARY DECODER
|
| 362 |
|
|
(
|
| 363 |
|
|
.iIn( wStationCommitGrant ),
|
| 364 |
|
|
.oOut( wBusSelector )
|
| 365 |
|
|
);
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX
|
| 369 |
|
|
(
|
| 370 |
|
|
.Sel(wBusSelector),
|
| 371 |
|
|
.I1(`COMMIT_PACKET_SIZE'b0),
|
| 372 |
|
|
.I2(wCommitData_Adder0),
|
| 373 |
|
|
.I3(wCommitData_Adder1),
|
| 374 |
|
|
.I4(wCommitData_Div),
|
| 375 |
|
|
.I5(wCommitData_Mul),
|
| 376 |
|
|
.I6(wCommitData_Sqrt),
|
| 377 |
|
|
.I7(wCommitData_Logic),
|
| 378 |
|
|
.O1(wCommitBus)
|
| 379 |
|
|
);
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
endmodule
|
