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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
//------------------------------------------------
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
        (
        input wire Clock,
        input wire Clear,
        input wire [SIZE-1:0] D,
        output reg [SIZE-1:0] Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 0;
      else
        Q = D;
    end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Enable,
        input wire [SIZE-1:0]    D,
        output reg [SIZE-1:0]    Q
);
 
 
always @ (posedge Clock)
begin
        if ( Reset )
                Q <= `WIDTH'b0;
        else
        begin
                if (Enable)
                        Q <= D;
        end
 
end//always
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
 
  always @(posedge Clock )
  begin
      if (Reset)
        Q = Initial;
      else
                begin
                if (Enable)
                        Q = Q + 1;
 
                end
  end
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 (
 input wire [1:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
 (
 input wire [2:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      3'b001: O1 = I1;
      3'b010: O1 = I2;
                3'b100: O1 = I3;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
//------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset || tmp[SIZE-1])
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//-----------------------------------------------------------
/*
        Sorry forgot how this flop is called.
        Any way Truth table is this
 
        Q       S       Q_next R
 
 
        1       0        1                0
        1       1       1                0
        X       X       0                 1
 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
        gets another S = 1, it keeps the output to 1.
*/
module FFToggleOnce_1Bit
(
        input wire Clock,
        input wire Reset,
        input wire Enable,
        input wire S,
        output reg Q
 
);
 
 
reg Q_next;
 
always @ (negedge Clock)
begin
        Q <= Q_next;
end
 
always @ ( posedge Clock )
begin
        if (Reset)
                Q_next <= 0;
        else if (Enable)
                Q_next <= (S && !Q) || Q;
        else
                Q_next <= Q;
end
endmodule
 
//--------------------------------------------------------------
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//-----------------------------------------------------------
 
/*
module UpCounterXXX_16
(
input wire Clock, Reset,
input wire [15:0] Initial,
output reg [15:0] Q
);
 
 
  always @(posedge Clock )
    begin
      if (Reset)
        Q = Initial;
      else
        Q = Q + 1'b1;
      end
 
endmodule
*/
//-----------------------------------------------------------
module UpCounter_16E
(
input wire Clock,
input wire Reset,
input wire [15:0] Initial,
input wire Enable,
output wire [15:0] Q
);
        reg [15:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 1'b1;
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_32
(
input wire Clock,
input wire Reset,
input wire [31:0] Initial,
input wire Enable,
output wire [31:0] Q
);
        reg [31:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
                begin
         Temp = Initial;
                end
      else
                begin
                        if (Enable)
                        begin
                                Temp =  Temp + 1'b1;
                        end
                end
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_3
(
input wire Clock,
input wire Reset,
input wire [2:0] Initial,
input wire Enable,
output wire [2:0] Q
);
        reg [2:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 3'b1;
  end
        assign Q = Temp;
 
endmodule
 
 
module FFD32_POSEDGE
(
        input wire Clock,
        input wire[31:0] D,
        output reg[31:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
 
//------------------------------------------------
/*
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
        output reg[`INSTRUCTION_OP_LENGTH-1:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = `INSTRUCTION_OP_LENGTH'b0;
      else
        Q = D;
    end
endmodule
//------------------------------------------------
 
module FF32_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[31:0] D,
        output reg[31:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 32'b0;
      else
        Q = D;
    end
endmodule
//------------------------------------------------
 
module FF16_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[15:0] D,
        output reg[15:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 16'b0;
      else
        Q = D;
    end
endmodule
*/
//------------------------------------------------
module MUXFULLPARALELL_96bits_2SEL
 (
 input wire Sel,
 input wire [95:0]I1, I2,
 output reg [95:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
 
module MUXFULLPARALELL_16bits_2SEL_X
 (
 input wire [1:0] Sel,
 input wire [15:0]I1, I2, I3,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                default: O1 = 16'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
 (
 input wire Sel,
 input wire [15:0]I1, I2,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
 
//------------------------------------------------
/*
module MUXFULLPARALELL_1Bit_1SEL
 (
 input wire Sel,
 input wire I1, I2,
 output reg O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD_OPCODE_POSEDGE
(
        input wire Clock,
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
        output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD16_POSEDGE
(
        input wire Clock,
        input wire[15:0] D,
        output reg[15:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
*/
//--------------------------------------------------------------
 
  module FFT1
  (
   input wire D,
   input wire Clock,
   input wire Reset ,
   output reg Q
 );
 
  always @ ( posedge Clock or posedge Reset )
  begin
 
        if (Reset)
        begin
    Q <= 1'b0;
   end
        else
        begin
                if (D)
                        Q <=  ! Q;
        end
 
  end//always
 
 endmodule
//--------------------------------------------------------------

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[/] [theia_gpu/] [branches/] [gpu_16_cores/] [rtl/] [Collaterals/] [Collaterals.v] - Blame information for rev 70

Line No.	Rev	Author	Line
1	36	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`//------------------------------------------------`
23			module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
24			`(`
25			`input wire Clock,`
26			`input wire Clear,`
27			`input wire [SIZE-1:0] D,`
28			`output reg [SIZE-1:0] Q`
29			`);`
30
31			`always @(posedge Clock or posedge Clear)`
32			`begin`
33			`if (Clear)`
34			`Q = 0;`
35			`else`
36			`Q = D;`
37			`end`
38			`endmodule`
39			`//----------------------------------------------------`
40			module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
41			`(`
42			`input wire Clock,`
43			`input wire Reset,`
44			`input wire Enable,`
45			`input wire [SIZE-1:0] D,`
46			`output reg [SIZE-1:0] Q`
47			`);`
48
49
50			`always @ (posedge Clock)`
51			`begin`
52			`if ( Reset )`
53			Q <= `WIDTH'b0;
54			`else`
55			`begin`
56			`if (Enable)`
57			`Q <= D;`
58			`end`
59
60			`end//always`
61
62			`endmodule`
63			`//------------------------------------------------`
64			module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
65			`(`
66			`input wire Clock, Reset,`
67			`input wire [SIZE-1:0] Initial,`
68			`input wire Enable,`
69			`output reg [SIZE-1:0] Q`
70			`);`
71
72
73			`always @(posedge Clock )`
74			`begin`
75			`if (Reset)`
76			`Q = Initial;`
77			`else`
78			`begin`
79			`if (Enable)`
80			`Q = Q + 1;`
81
82			`end`
83			`end`
84
85			`endmodule`
86	70	diegovalve
87	36	diegovalve	`//------------------------------------------------`
88			module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
89			`(`
90			`input wire [1:0] Sel,`
91			`input wire [SIZE-1:0]I1, I2, I3,`
92			`output reg [SIZE-1:0] O1`
93			`);`
94
95			`always @( * )`
96
97			`begin`
98
99			`case (Sel)`
100
101			`2'b00: O1 = I1;`
102			`2'b01: O1 = I2;`
103			`2'b10: O1 = I3;`
104			`default: O1 = SIZE-1'b0;`
105
106			`endcase`
107
108			`end`
109
110			`endmodule`
111
112			`//------------------------------------------------`
113			module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
114			`(`
115			`input wire [2:0] Sel,`
116			`input wire [SIZE-1:0]I1, I2, I3,`
117			`output reg [SIZE-1:0] O1`
118			`);`
119
120			`always @( * )`
121
122			`begin`
123
124			`case (Sel)`
125
126			`3'b001: O1 = I1;`
127			`3'b010: O1 = I2;`
128			`3'b100: O1 = I3;`
129			`default: O1 = SIZE-1'b0;`
130
131			`endcase`
132
133			`end`
134
135			`endmodule`
136			`//------------------------------------------------`
137			module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
138			`( input wire Clock,`
139			`input wire Reset,`
140			`input wire[SIZE-1:0] Initial,`
141			`input wire Enable,`
142			`output wire[SIZE-1:0] O`
143			`);`
144
145			`reg [SIZE-1:0] tmp;`
146
147
148			`always @(posedge Clock)`
149			`begin`
150			`if (Reset)`
151			`tmp <= Initial;`
152			`else`
153			`begin`
154			`if (Enable)`
155			`tmp <= tmp << 1;`
156			`end`
157			`end`
158
159
160			`assign O = tmp;`
161			`endmodule`
162			`//------------------------------------------------`
163			`//------------------------------------------------`
164			module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
165			`( input wire Clock,`
166			`input wire Reset,`
167			`input wire[SIZE-1:0] Initial,`
168			`input wire Enable,`
169			`output wire[SIZE-1:0] O`
170			`);`
171
172			`reg [SIZE-1:0] tmp;`
173
174
175			`always @(posedge Clock)`
176			`begin`
177			`if (Reset \|\| tmp[SIZE-1])`
178			`tmp <= Initial;`
179			`else`
180			`begin`
181			`if (Enable)`
182			`tmp <= tmp << 1;`
183			`end`
184			`end`
185
186
187			`assign O = tmp;`
188			`endmodule`
189			`//-----------------------------------------------------------`
190			`/*`
191			`Sorry forgot how this flop is called.`
192			`Any way Truth table is this`
193
194			`Q S Q_next R`
195
196
197			`1 0 1 0`
198			`1 1 1 0`
199			`X X 0 1`
200
201			`The idea is that it toggles from 0 to 1 when S = 1, but if it`
202			`gets another S = 1, it keeps the output to 1.`
203			`*/`
204			`module FFToggleOnce_1Bit`
205			`(`
206			`input wire Clock,`
207			`input wire Reset,`
208			`input wire Enable,`
209			`input wire S,`
210			`output reg Q`
211
212			`);`
213
214
215			`reg Q_next;`
216
217			`always @ (negedge Clock)`
218			`begin`
219			`Q <= Q_next;`
220			`end`
221
222			`always @ ( posedge Clock )`
223			`begin`
224			`if (Reset)`
225			`Q_next <= 0;`
226			`else if (Enable)`
227			`Q_next <= (S && !Q) \|\| Q;`
228			`else`
229			`Q_next <= Q;`
230			`end`
231			`endmodule`
232
233			`//--------------------------------------------------------------`
234			`//**********************OLD MODS*************************//`
235			`//**********************OLD MODS*************************//`
236			`//**********************OLD MODS*************************//`
237			`//**********************OLD MODS*************************//`
238			`//-----------------------------------------------------------`
239
240			`/*`
241			`module UpCounterXXX_16`
242			`(`
243			`input wire Clock, Reset,`
244			`input wire [15:0] Initial,`
245			`output reg [15:0] Q`
246			`);`
247
248
249			`always @(posedge Clock )`
250			`begin`
251			`if (Reset)`
252			`Q = Initial;`
253			`else`
254			`Q = Q + 1'b1;`
255			`end`
256
257			`endmodule`
258			`*/`
259			`//-----------------------------------------------------------`
260			`module UpCounter_16E`
261			`(`
262			`input wire Clock,`
263			`input wire Reset,`
264			`input wire [15:0] Initial,`
265			`input wire Enable,`
266			`output wire [15:0] Q`
267			`);`
268			`reg [15:0] Temp;`
269
270
271			`always @(posedge Clock or posedge Reset)`
272			`begin`
273			`if (Reset)`
274			`Temp = Initial;`
275			`else`
276			`if (Enable)`
277			`Temp = Temp + 1'b1;`
278			`end`
279			`assign Q = Temp;`
280
281			`endmodule`
282			`//-----------------------------------------------------------`
283			`module UpCounter_32`
284			`(`
285			`input wire Clock,`
286			`input wire Reset,`
287			`input wire [31:0] Initial,`
288			`input wire Enable,`
289			`output wire [31:0] Q`
290			`);`
291			`reg [31:0] Temp;`
292
293
294			`always @(posedge Clock or posedge Reset)`
295			`begin`
296			`if (Reset)`
297			`begin`
298			`Temp = Initial;`
299			`end`
300			`else`
301			`begin`
302			`if (Enable)`
303			`begin`
304			`Temp = Temp + 1'b1;`
305			`end`
306			`end`
307			`end`
308			`assign Q = Temp;`
309
310			`endmodule`
311			`//-----------------------------------------------------------`
312			`module UpCounter_3`
313			`(`
314			`input wire Clock,`
315			`input wire Reset,`
316			`input wire [2:0] Initial,`
317			`input wire Enable,`
318			`output wire [2:0] Q`
319			`);`
320			`reg [2:0] Temp;`
321
322
323			`always @(posedge Clock or posedge Reset)`
324			`begin`
325			`if (Reset)`
326			`Temp = Initial;`
327			`else`
328			`if (Enable)`
329			`Temp = Temp + 3'b1;`
330			`end`
331			`assign Q = Temp;`
332
333			`endmodule`
334
335
336			`module FFD32_POSEDGE`
337			`(`
338			`input wire Clock,`
339			`input wire[31:0] D,`
340			`output reg[31:0] Q`
341			`);`
342
343			`always @ (posedge Clock)`
344			`Q <= D;`
345
346			`endmodule`
347
348			`//------------------------------------------------`
349	70	diegovalve	`/*`
350	36	diegovalve	`module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET`
351			`(`
352			`input wire Clock,`
353			`input wire Clear,`
354			input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
355			output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
356			`);`
357
358			`always @(posedge Clock or posedge Clear)`
359			`begin`
360			`if (Clear)`
361			Q = `INSTRUCTION_OP_LENGTH'b0;
362			`else`
363			`Q = D;`
364			`end`
365			`endmodule`
366			`//------------------------------------------------`
367	70	diegovalve
368	36	diegovalve	`module FF32_POSEDGE_SYNCRONOUS_RESET`
369			`(`
370			`input wire Clock,`
371			`input wire Clear,`
372			`input wire[31:0] D,`
373			`output reg[31:0] Q`
374			`);`
375
376			`always @(posedge Clock or posedge Clear)`
377			`begin`
378			`if (Clear)`
379			`Q = 32'b0;`
380			`else`
381			`Q = D;`
382			`end`
383			`endmodule`
384			`//------------------------------------------------`
385	63	diegovalve
386	36	diegovalve	`module FF16_POSEDGE_SYNCRONOUS_RESET`
387			`(`
388			`input wire Clock,`
389			`input wire Clear,`
390			`input wire[15:0] D,`
391			`output reg[15:0] Q`
392			`);`
393
394			`always @(posedge Clock or posedge Clear)`
395			`begin`
396			`if (Clear)`
397			`Q = 16'b0;`
398			`else`
399			`Q = D;`
400			`end`
401			`endmodule`
402	70	diegovalve	`*/`
403	36	diegovalve	`//------------------------------------------------`
404			`module MUXFULLPARALELL_96bits_2SEL`
405			`(`
406			`input wire Sel,`
407			`input wire [95:0]I1, I2,`
408			`output reg [95:0] O1`
409			`);`
410
411
412
413			`always @( * )`
414
415			`begin`
416
417			`case (Sel)`
418
419			`1'b0: O1 = I1;`
420			`1'b1: O1 = I2;`
421
422			`endcase`
423
424			`end`
425
426			`endmodule`
427			`//------------------------------------------------`
428
429			`module MUXFULLPARALELL_16bits_2SEL_X`
430			`(`
431			`input wire [1:0] Sel,`
432			`input wire [15:0]I1, I2, I3,`
433			`output reg [15:0] O1`
434			`);`
435
436
437
438			`always @( * )`
439
440			`begin`
441
442			`case (Sel)`
443
444			`2'b00: O1 = I1;`
445			`2'b01: O1 = I2;`
446			`2'b10: O1 = I3;`
447			`default: O1 = 16'b0;`
448
449			`endcase`
450
451			`end`
452
453			`endmodule`
454			`//------------------------------------------------`
455			`module MUXFULLPARALELL_16bits_2SEL`
456			`(`
457			`input wire Sel,`
458			`input wire [15:0]I1, I2,`
459			`output reg [15:0] O1`
460			`);`
461
462
463
464			`always @( * )`
465
466			`begin`
467
468			`case (Sel)`
469
470			`1'b0: O1 = I1;`
471			`1'b1: O1 = I2;`
472
473			`endcase`
474
475			`end`
476
477			`endmodule`
478
479
480			`//------------------------------------------------`
481	63	diegovalve	`/*`
482	36	diegovalve	`module MUXFULLPARALELL_1Bit_1SEL`
483			`(`
484			`input wire Sel,`
485			`input wire I1, I2,`
486			`output reg O1`
487			`);`
488
489
490
491			`always @( * )`
492
493			`begin`
494
495			`case (Sel)`
496
497			`1'b0: O1 = I1;`
498			`1'b1: O1 = I2;`
499
500			`endcase`
501
502			`end`
503
504			`endmodule`
505	63	diegovalve	`*/`
506	36	diegovalve	`//--------------------------------------------------------------`
507	63	diegovalve	`/*`
508	36	diegovalve	`module FFD_OPCODE_POSEDGE`
509			`(`
510			`input wire Clock,`
511			input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
512			output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
513			`);`
514
515			`always @ (posedge Clock)`
516			`Q <= D;`
517
518			`endmodule`
519	63	diegovalve	`*/`
520	36	diegovalve	`//--------------------------------------------------------------`
521	63	diegovalve	`/*`
522	36	diegovalve	`module FFD16_POSEDGE`
523			`(`
524			`input wire Clock,`
525			`input wire[15:0] D,`
526			`output reg[15:0] Q`
527			`);`
528
529			`always @ (posedge Clock)`
530			`Q <= D;`
531
532			`endmodule`
533	63	diegovalve	`*/`
534	36	diegovalve	`//--------------------------------------------------------------`
535
536			`module FFT1`
537			`(`
538			`input wire D,`
539			`input wire Clock,`
540			`input wire Reset ,`
541			`output reg Q`
542			`);`
543
544			`always @ ( posedge Clock or posedge Reset )`
545			`begin`
546
547			`if (Reset)`
548			`begin`
549			`Q <= 1'b0;`
550			`end`
551			`else`
552			`begin`
553			`if (D)`
554			`Q <= ! Q;`
555			`end`
556
557			`end//always`
558
559			`endmodule`
560			`//--------------------------------------------------------------`