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URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

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1 16 diegovalve
/**********************************************************************************
2
Theia, Ray Cast Programable graphic Processing Unit.
3
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
4
 
5
This program is free software; you can redistribute it and/or
6
modify it under the terms of the GNU General Public License
7
as published by the Free Software Foundation; either version 2
8
of the License, or (at your option) any later version.
9
 
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14
 
15
You should have received a copy of the GNU General Public License
16
along with this program; if not, write to the Free Software
17
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18
 
19
***********************************************************************************/
20
 
21
/**********************************************************************************
22
Description:
23
 This is the top level block for THEIA.
24
 THEIA core has 5 main logical blocks called Units.
25
 This module implements the interconections between the Units.
26
 
27
 Units:
28
  > EXE: Mananges execution logic for the SHADERS.
29
  > GEO: Manages geometry data structures.
30
  > IO: Input/Output (Wishbone).
31
  > MEM: Internal memory, separate for Instructions and data.
32
  > CONTROL: Main control Finite state machine.
33
 
34
 Internal Buses:
35
        THEIA has separate instruction and data buses.
36
        THEIA avoids using tri-state buses by having separate input/output
37
        for each bus.
38
        There are 2 separate data buses since the Data memory
39
        has a Dual read channel.
40
   Please see the MEM unit chapter in the documentation for more details.
41
 
42
 External Buses:
43
        External buses are managed by the IO Unit.
44
        External buses follow the wishbone protocol.
45
        Please see the IO unit chapter in the documentation for more details.
46
**********************************************************************************/
47
 
48
`timescale 1ns / 1ps
49
`include "aDefinitions.v"
50
 
51
module THEIACORE
52
(
53
 
54
input wire                    CLK_I,    //Input clock
55
input wire                    RST_I,    //Input reset
56
//Theia Interfaces
57
input wire                    MST_I,    //Master signal, THEIA enters configuration mode
58
                                       //when this gets asserted (see documentation)
59
//Wish Bone Interface
60
input wire [`WB_WIDTH-1:0]    DAT_I,     //Input data bus  (Wishbone)
61
output wire [`WB_WIDTH-1:0]   DAT_O,     //Output data bus (Wishbone)
62
input wire                    ACK_I,    //Input ack
63
output wire                   ACK_O,    //Output ack
64
output wire [`WB_WIDTH-1:0]   ADR_O,     //Output address
65
input wire [`WB_WIDTH-1:0]    ADR_I,     //Input address
66
output wire                   WE_O,             //Output write enable
67
input wire                    WE_I,    //Input write enable
68
output wire                   STB_O,    //Strobe signal, see wishbone documentation
69
input wire                    STB_I,    //Strobe signal, see wishbone documentation
70
output wire                   CYC_O,    //Bus cycle signal, see wishbone documentation
71
input wire                    CYC_I,   //Bus cycle signal, see wishbone documentation
72
output wire     [1:0]             TGC_O,   //Bus cycle tag, see THEAI documentation
73
input wire [1:0]              TGA_I,   //Input address tag, see THEAI documentation
74
output wire [1:0]             TGA_O,   //Output address tag, see THEAI documentation
75
input wire      [1:0]             TGC_I,   //Bus cycle tag, see THEAI documentation
76
//Control Register
77
input wire [15:0]                         CREG_I
78
 
79
);
80
 
81
//Alias this signals
82
wire Clock,Reset;
83
assign Clock = CLK_I;
84
assign Reset = RST_I;
85
 
86 75 diegovalve
wire [`DATA_ROW_WIDTH-1:0]                        wEXE_2__MEM_WriteData;
87 16 diegovalve
wire [`DATA_ROW_WIDTH-1:0]                        wUCODE_RAMBus;
88 75 diegovalve
wire [`DATA_ADDRESS_WIDTH-1:0]    wEXE_2__MEM_wDataWriteAddress;
89 16 diegovalve
wire                              w2IO__AddrIsImm;
90
wire [`DATA_ADDRESS_WIDTH-1:0]    wUCODE_RAMAddress;
91
wire [`DATA_ADDRESS_WIDTH-1:0]    w2IO__Adr_O_Pointer;
92
wire [`DATA_ADDRESS_WIDTH-1:0]    wGEO2_IO__Adr_O_Pointer;
93 75 diegovalve
wire                                                                             wEXE_2__DataWriteEnable;
94 16 diegovalve
wire                                                                             wUCODE_RAMWriteEnable;
95
wire [2:0]                                                                RamBusOwner;
96
//Unit intercoanection wires
97
 
98
wire                                                                            wCU2__MicrocodeExecutionDone;
99
wire [`ROM_ADDRESS_WIDTH-1:0]            InitialCodeAddress;
100 60 diegovalve
wire [`ROM_ADDRESS_WIDTH-1:0]            wInstructionPointer1,wInstructionPointer2;
101
wire [`INSTRUCTION_WIDTH-1:0]    wEncodedInstruction1,wEncodedInstruction2,wIO2_MEM__ExternalInstruction;
102 16 diegovalve
wire                                                                            wCU2__ExecuteMicroCode;
103
wire  [`ROM_ADDRESS_WIDTH-1:0]   wIO2_MEM__InstructionWriteAddr;
104 75 diegovalve
wire [95:0]                                                      wMEM_2__EXE_DataRead0, wMEM_2__EXE_DataRead1,wMEM_2__IO_DataRead0, wMEM_2__IO_DataRead1;
105
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE_2__MEM_DataReadAddress0,wEXE_2__MEM_DataReadAddress1;
106 16 diegovalve
wire [`DATA_ADDRESS_WIDTH-1:0]   wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
107
 
108
 
109
wire [`WIDTH-1:0]                                        w2IO__AddressOffset;
110
wire [`DATA_ADDRESS_WIDTH-1:0]   w2IO__DataWriteAddress;
111
wire                                                                            w2IO__Store;
112
wire                                                                            w2IO__EnableWBMaster;
113
 
114 75 diegovalve
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO2_MEM__DataWriteAddress;
115 16 diegovalve
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO_2_MEM__DataReadAddress0;
116 75 diegovalve
wire [`DATA_ROW_WIDTH-1:0]               wIO2_MEM__Bus;
117
wire [`WIDTH-1:0]                                        wIO2_MEM__Data;
118 16 diegovalve
wire [`WIDTH-1:0]                                        wIO2_WBM__Address;
119 75 diegovalve
wire                                                                            wIO2_MEM__DataWriteEnable;
120 16 diegovalve
wire                                                                            wIO2__Done;
121
wire                                                                            wCU2_GEO__GeometryFetchEnable;
122
wire                                                                            wIFU2__MicroCodeReturnValue;
123
wire                                                                            wCU2_BCU__ACK;
124
wire                                                                            wGEO2_CU__RequestAABBIU;
125
wire                                                                            wGEO2_CU__RequestBIU;
126
wire                             wGEO2_CU__RequestTCC;
127
wire                                                                            wGEO2_CU__GeometryUnitDone;
128
wire                                                                            wGEO2_CU__Sync;
129
wire                                                                            wEXE2__uCodeDone;
130
wire                                                                            wEXE2_IFU__EXEBusy;
131
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE2_IDU_DataFordward_LastDestination;
132
wire                                                                            wALU2_EXE__BranchTaken;
133
wire                                                                            wALU2_IFU_BranchNotTaken;
134
wire                                                                            w2IO__SetAddress;
135
wire                                                                            wIDU2_IFU__IDUBusy;
136
//Control Registe wires
137
wire[15:0]                                                               wCR2_ControlRegister;
138
wire                                                                            wCR2_TextureMappingEnabled;
139
wire                             wGEO2_CU__TFFDone;
140
wire                             wCU2_GEO__TriggerTFF;
141
wire                             wIO2_MEM_InstructionWriteEnable;
142
wire                             wCU2_IO__WritePixel;
143
wire                             wGEO2_IO__AddrIsImm;
144
wire[31:0]                       wGEO2_IO__AddressOffset;
145
wire                             wGEO2_IO__EnableWBMaster;
146
wire                             wGEO2_IO__SetAddress;
147
wire[`WIDTH-1:0]                 wGEO2__CurrentPitch,wCU2_GEO_Pitch;
148
wire                             wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
149 75 diegovalve
wire wCU2_FlipMemEnabled;
150
wire w2MEM_FlipMemory;
151 16 diegovalve
 
152
`ifdef DEBUG
153
        wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
154
`endif
155
//--------------------------------------------------------
156
 
157
 
158 75 diegovalve
/*
159 16 diegovalve
        ///////////////// TODO CHANGE FOR MUXES ////////////////////////////////
160 75 diegovalve
        assign wEXE_2__MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
161 16 diegovalve
                wUCODE_RAMBus : `DATA_ROW_WIDTH'bz;
162
 
163 75 diegovalve
        assign wEXE_2__MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
164
                wIO2_MEM__Bus : `DATA_ROW_WIDTH'bz;
165 16 diegovalve
 
166 75 diegovalve
        assign wEXE_2__MEM_wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
167 16 diegovalve
                wUCODE_RAMAddress : `DATA_ADDRESS_WIDTH'bz;
168
 
169 75 diegovalve
        assign wEXE_2__MEM_wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
170
        wIO2_MEM__DataWriteAddress : `DATA_ADDRESS_WIDTH'bz;
171 16 diegovalve
 
172
 
173
         MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) MUX_RA0
174
        (
175
 .Sel(RamBusOwner[1:0]),
176
 .I1(`DATA_ADDRESS_WIDTH'b0),
177
 .I2(wIO_2_MEM__DataReadAddress0),
178
 .I3(wUCODE_RAMReadAddress0),
179 75 diegovalve
 .O1(wEXE_2__MEM_DataReadAddress0)
180 16 diegovalve
 );
181
 
182
 
183
 
184
 
185
 
186
 
187 75 diegovalve
assign wEXE_2__DataWriteEnable  = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE && MST_I == 1'b0) ?
188 16 diegovalve
                wUCODE_RAMWriteEnable : 1'bz;
189
 
190 75 diegovalve
assign wEXE_2__DataWriteEnable  = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
191
                wIO2_MEM__DataWriteEnable : 1'bz;
192
*/
193 16 diegovalve
assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
194 75 diegovalve
wire wCU2_FlipMem;
195 16 diegovalve
//--------------------------------------------------------
196
//Control Unit Instance
197
        ControlUnit CU
198
        (
199
           .Clock(Clock),
200
                .Reset(Reset),
201 75 diegovalve
                .oFlipMemEnabled(                   wCU2_FlipMemEnabled            ),
202
                .oFlipMem(                          wCU2_FlipMem                   ),
203 16 diegovalve
                .iControlRegister(                  wCR2_ControlRegister           ),
204
                .oRamBusOwner(                      RamBusOwner                    ),
205
                .oGFUEnable(                        wCU2_GEO__GeometryFetchEnable  ),
206
                .iTriggerAABBIURequest(             wGEO2_CU__RequestAABBIU        ),
207
                .iTriggerBIURequest(                wGEO2_CU__RequestBIU           ),
208
                .iTriggertTCCRequest(               wGEO2_CU__RequestTCC           ),
209
                .oUCodeEnable(                      wCU2__ExecuteMicroCode         ),
210 60 diegovalve
                .oCodeInstructioPointer(           InitialCodeAddress             ),
211 16 diegovalve
                .iUCodeDone(                        wCU2__MicrocodeExecutionDone   ),
212
                .iIODone(                           wIO2__Done                     ),
213
                .oIOWritePixel(                     wCU2_IO__WritePixel            ),
214
                .iUCodeReturnValue(                 wIFU2__MicroCodeReturnValue    ),
215
                .iGEOSync(                          wGEO2_CU__Sync                 ),
216
                .iTFFDone(                          wGEO2_CU__TFFDone              ),
217
                .oTriggerTFF(                       wCU2_GEO__TriggerTFF           ),
218
                .MST_I(                             MST_I                          ),
219
                .oSetCurrentPitch(                  wCU2_GEO__SetPitch             ),
220
                .iGFUDone(                          wGEO2_CU__GeometryUnitDone     )
221
 
222
        );
223
 
224
 
225 75 diegovalve
 
226 16 diegovalve
 
227
//--------------------------------------------------------      
228 75 diegovalve
 
229
//assign w2MEM_FlipMemory =  (wCU2__ExecuteMicroCode | wCU2_FlipMem ) & wCU2_FlipMemEnabled;
230
assign w2MEM_FlipMemory =  wCU2_FlipMem  & wCU2_FlipMemEnabled;
231 16 diegovalve
MemoryUnit MEM
232
(
233
.Clock(Clock),
234
.Reset(Reset),
235 75 diegovalve
 
236
.iFlipMemory( w2MEM_FlipMemory ),
237
 
238
//Data Bus to/from EXE
239
.iDataReadAddress1_EXE(       wEXE_2__MEM_DataReadAddress0        ),
240
.iDataReadAddress2_EXE(       wEXE_2__MEM_DataReadAddress1        ),
241
.oData1_EXE(                  wMEM_2__EXE_DataRead0               ),
242
.oData2_EXE(                  wMEM_2__EXE_DataRead1               ),
243
.iDataWriteEnable_EXE(        wEXE_2__DataWriteEnable          ),
244
.iDataWriteAddress_EXE(       wEXE_2__MEM_wDataWriteAddress        ),
245
.iData_EXE(                   wEXE_2__MEM_WriteData          ),
246
 
247
//Data Bus to/from IO
248
 
249
.iDataReadAddress1_IO(       wIO_2_MEM__DataReadAddress0        ),
250
.iDataReadAddress2_IO(       wIO_2_MEM__DataReadAddress1        ),
251
.oData1_IO(                  wMEM_2__IO_DataRead0               ),
252
.oData2_IO(                  wMEM_2__IO_DataRead1               ),
253
.iDataWriteEnable_IO(        wIO2_MEM__DataWriteEnable          ),
254
.iDataWriteAddress_IO(       wIO2_MEM__DataWriteAddress        ),
255
.iData_IO(                   wIO2_MEM__Bus          ),
256
 
257
 
258 16 diegovalve
//Instruction Bus
259 60 diegovalve
.iInstructionReadAddress1(  wInstructionPointer1             ),
260
.iInstructionReadAddress2(  wInstructionPointer2             ),
261
.oInstruction1(             wEncodedInstruction1             ),
262
.oInstruction2(             wEncodedInstruction2             ),
263 16 diegovalve
.iInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
264
.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr  ),
265
.iInstruction(             wIO2_MEM__ExternalInstruction   ),
266
.iControlRegister(         CREG_I                          ),
267
.oControlRegister(         wCR2_ControlRegister            )
268
 
269
);
270
 
271
////--------------------------------------------------------
272 75 diegovalve
 
273
 
274 16 diegovalve
ExecutionUnit EXE
275
(
276
 
277
.Clock( Clock),
278
.Reset( Reset ),
279 75 diegovalve
.iInitialCodeAddress(    InitialCodeAddress     ),
280
.iInstruction1(          wEncodedInstruction1      ),
281
.iInstruction2(          wEncodedInstruction2      ),
282 60 diegovalve
.oInstructionPointer1(   wInstructionPointer1    ),
283
.oInstructionPointer2(   wInstructionPointer2    ),
284 75 diegovalve
.iDataRead0(             wMEM_2__EXE_DataRead0             ),
285
.iDataRead1(             wMEM_2__EXE_DataRead1             ),
286
.iTrigger(               wCU2__ExecuteMicroCode ),
287
.oDataReadAddress0( wEXE_2__MEM_DataReadAddress0 ),
288
.oDataReadAddress1( wEXE_2__MEM_DataReadAddress1 ),
289
.oDataWriteEnable(  wEXE_2__DataWriteEnable  ),
290
.oDataWriteAddress( wEXE_2__MEM_wDataWriteAddress      ),
291
.oDataBus(          wEXE_2__MEM_WriteData          ),
292 16 diegovalve
.oReturnCode(       wIFU2__MicroCodeReturnValue ),
293
.oDone(             wCU2__MicrocodeExecutionDone )
294
 
295
);
296
 
297
////--------------------------------------------------------
298
wire wGEO2__RequestingTextures;
299
wire w2IO_WriteBack_Set;
300
 
301
GeometryUnit GEO
302
(
303
                .Clock( Clock ),
304
                .Reset( Reset ),
305
                .iEnable(                     wCU2_GEO__GeometryFetchEnable       ),
306
                .iTexturingEnable(            wCR2_TextureMappingEnabled          ),
307
                //Wires from IO
308 75 diegovalve
                .iData_WBM(                                             wIO2_MEM__Data ),
309 16 diegovalve
                .iDataReady_WBM(                                        wIO2__Done ),
310
                //Wires to WBM
311
                .oAddressWBM_Imm(                               wGEO2_IO__AddressOffset                                 ),
312
                .oAddressWBM_fromMEM(         wGEO2_IO__Adr_O_Pointer             ),
313
                .oAddressWBM_IsImm(           wGEO2_IO__AddrIsImm                 ),
314
                .oEnable_WBM(                                           wGEO2_IO__EnableWBMaster                                ),
315
                .oSetAddressWBM(                                        wGEO2_IO__SetAddress                                            ),
316
                .oSetIOWriteBackAddr(         w2IO_WriteBack_Set                  ),
317
                //Wires to CU
318
                .oRequest_AABBIU(             wGEO2_CU__RequestAABBIU                ),
319
                .oRequest_BIU(                wGEO2_CU__RequestBIU                   ),
320
                .oRequest_TCC(                wGEO2_CU__RequestTCC                   ),
321
                .oTFFDone(                    wGEO2_CU__TFFDone                      ),
322
                //Wires to RAM-Bus MUX  
323
                .oRAMWriteAddress(                              w2IO__DataWriteAddress                                  ),
324
                .oRAMWriteEnable(                               w2IO__Store ),
325
                //Wires from Execution Unit
326
                .iMicrocodeExecutionDone(               wCU2__MicrocodeExecutionDone                            ),
327
                .iMicroCodeReturnValue(                 wIFU2__MicroCodeReturnValue                             ),
328
                .oSync(                                                         wGEO2_CU__Sync                                                                  ),
329
                .iTrigger_TFF(                wCU2_GEO__TriggerTFF                   ),
330
                .iBIUHit(                     wIFU2__MicroCodeReturnValue            ),
331
                .oRequestingTextures( wGEO2__RequestingTextures ),
332
                .oDone(                                                         wGEO2_CU__GeometryUnitDone                                      )
333
);
334
 
335
 
336
assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
337
//---------------------------------------------------------------------------------------------------
338 75 diegovalve
wire[`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress1;
339
assign wEXE_2__MEM_DataReadAddress1 = (wCU2_IO__WritePixel == 0) ?  wUCODE_RAMReadAddress1 : wIO_2_MEM__DataReadAddress1;
340 16 diegovalve
assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
341
assign w2IO__AddrIsImm       = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm       : 1'b1;
342
assign w2IO__AddressOffset   = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset   : 32'b0;
343
assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_PIXEL_PITCH;
344
wire w2IO_MasterCycleType;
345
assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
346
 
347
 
348
 
349
assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
350
 
351
 
352
IO_Unit IO
353
(
354
 .Clock(               Clock                            ),
355
 .Reset(               Reset                            ),
356
 .iEnable(            w2IO__EnableWBMaster              ),
357
 .iBusCyc_Type(         w2IO_MasterCycleType            ),
358
 
359
 .iStore(              w2IO__Store                      ),
360
 .iAdr_DataWriteBack(    w2IO__DataWriteAddress         ),
361
 .iAdr_O_Set(      w2IO__SetAddress                     ),
362
 .iAdr_O_Imm(       w2IO__AddressOffset                 ),
363
 .iAdr_O_Type(      w2IO__AddrIsImm                     ),
364
 .iAdr_O_Pointer(  w2IO__Adr_O_Pointer                  ),
365 75 diegovalve
 .iReadDataBus(        wMEM_2__IO_DataRead0                       ),
366
 .iReadDataBus2(        wMEM_2__IO_DataRead1                       ),
367 16 diegovalve
 .iDat_O_Pointer(     `OREG_PIXEL_COLOR                 ),
368
 
369
 
370
 .oDataReadAddress(    wIO_2_MEM__DataReadAddress0      ),
371 75 diegovalve
 .oDataReadAddress2(   wIO_2_MEM__DataReadAddress1       ),
372
 .oDataWriteAddress(   wIO2_MEM__DataWriteAddress    ),
373
 .oDataBus(               wIO2_MEM__Bus                 ),
374 16 diegovalve
 .oInstructionBus(     wIO2_MEM__ExternalInstruction    ),
375
 
376 75 diegovalve
 .oDataWriteEnable(         wIO2_MEM__DataWriteEnable    ),
377
 .oData(                    wIO2_MEM__Data                       ),
378
 .oInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
379 16 diegovalve
 .oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
380
 .iWriteBack_Set( w2IO_WriteBack_Set ),
381
 
382
 .oDone(               wIO2__Done                       ),
383
 .MST_I( MST_I ),
384
  //Wish Bone Interface
385
.DAT_I( DAT_I ),
386
.DAT_O( DAT_O ),
387
.ACK_I( ACK_I ),
388
.ACK_O( ACK_O ),
389
.ADR_O( ADR_O ),
390
.ADR_I( ADR_I ),
391
.WE_O(  WE_O  ),
392
.WE_I(  WE_I  ),
393
.STB_O( STB_O ),
394
.STB_I( STB_I ),
395
.CYC_O( CYC_O ),
396
.TGA_I( TGA_I ),
397
.CYC_I( CYC_I ),
398
.TGC_O( TGC_O )
399
 
400
 
401
);
402
//---------------------------------------------------------------------------------------------------
403
endmodule

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