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[/] [theia_gpu/] [branches/] [gpu_4_cores/] [examples/] [shaders/] [example1/] [Example3.shdr] - Blame information for rev 127

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Line No. Rev Author Line
1 68 diegovalve
ENTRYPOINT_ADRR_USERCONSTANTS:
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       SETX C1 32'h06666   //0.2
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       SETY C1 32'h1CCCC   //0.9
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       RETURN RT_TRUE
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ENTRYPOINT_ADRR_PIXELSHADER:
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       MAG  R1 CREG_TEXTURE_COLOR
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       JLX  BLACK R1 C1
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       JGEY BLACK R1 C1
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WHITE:
12 123 diegovalve
       SETX R2 32'h20000
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       SWIZZLE3D R2 SWIZZLE_XXX
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          OMWRITE  OREG_PIXEL_COLOR CREG_CURRENT_OUTPUT_PIXEL R2
15 68 diegovalve
       RETURN RT_TRUE
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BLACK:
17 123 diegovalve
       ZERO R2 VOID VOID
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          OMWRITE  OREG_PIXEL_COLOR CREG_CURRENT_OUTPUT_PIXEL R2
19 68 diegovalve
       RETURN  RT_TRUE
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