| 1 |
124 |
diegovalve |
`timescale 1ns / 1ps
|
| 2 |
|
|
`include "aDefinitions.v"
|
| 3 |
|
|
|
| 4 |
|
|
|
| 5 |
|
|
|
| 6 |
|
|
/**********************************************************************************
|
| 7 |
|
|
Theia, Ray Cast Programable graphic Processing Unit.
|
| 8 |
|
|
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
|
| 9 |
|
|
|
| 10 |
|
|
This program is free software; you can redistribute it and/or
|
| 11 |
|
|
modify it under the terms of the GNU General Public License
|
| 12 |
|
|
as published by the Free Software Foundation; either version 2
|
| 13 |
|
|
of the License, or (at your option) any later version.
|
| 14 |
|
|
|
| 15 |
|
|
This program is distributed in the hope that it will be useful,
|
| 16 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 17 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 18 |
|
|
GNU General Public License for more details.
|
| 19 |
|
|
|
| 20 |
|
|
You should have received a copy of the GNU General Public License
|
| 21 |
|
|
along with this program; if not, write to the Free Software
|
| 22 |
|
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 23 |
|
|
|
| 24 |
|
|
***********************************************************************************/
|
| 25 |
|
|
|
| 26 |
|
|
|
| 27 |
|
|
/*******************************************************************************
|
| 28 |
|
|
Module Description:
|
| 29 |
|
|
|
| 30 |
|
|
WIP
|
| 31 |
|
|
|
| 32 |
|
|
*******************************************************************************/
|
| 33 |
|
|
|
| 34 |
|
|
|
| 35 |
|
|
|
| 36 |
|
|
`define MAX_VERTEX_IN_FRAME 8'd7 // WAS 8'd6
|
| 37 |
|
|
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
|
| 38 |
|
|
`define TAG_DATA_ADDRESS_TYPE 2'b10
|
| 39 |
|
|
`define SELECT_INST_MEM 3'b00
|
| 40 |
|
|
`define SELECT_SCENE_MEM 3'b01
|
| 41 |
|
|
`define SELECT_GEO_MEM 3'b10
|
| 42 |
|
|
`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
|
| 43 |
|
|
|
| 44 |
|
|
`define HOST_IDLE 0
|
| 45 |
|
|
`define HOST_WRITE_INSTRUCTION 1
|
| 46 |
|
|
`define HOST_WAIT_INSTRUCTION 2
|
| 47 |
|
|
`define HOST_WRITE_SCENE_PARAMS 3
|
| 48 |
|
|
`define HOST_WAIT_SCENE_PARAMS 4
|
| 49 |
|
|
`define HOST_PREPARE_CORE_CONFIG 5
|
| 50 |
|
|
`define HOST_UNICAST_CORE_CONFIG 6
|
| 51 |
|
|
`define HOST_WAIT_CORE_CONFIG 7
|
| 52 |
|
|
`define HOST_PREPARE_NEXT_CORE_CONFIG 8
|
| 53 |
|
|
`define HOST_WAIT_DATA_READ_CONFIRMATION 10
|
| 54 |
|
|
`define HOST_BROADCAST_NEXT_VERTEX 11
|
| 55 |
|
|
`define HOST_WAIT_FOR_VERTEX 12
|
| 56 |
|
|
`define HOST_INITIAL_SCENE_PARAMS_STAGE 13
|
| 57 |
|
|
`define HOST_PREPARE_FOR_GEO_REQUESTS 14
|
| 58 |
|
|
`define HOST_ACK_GEO_REQUEST 15
|
| 59 |
|
|
`define HOST_GET_PRIMITIVE_COUNT 16
|
| 60 |
|
|
`define HOST_LAST_PRIMITIVE_REACHED 17
|
| 61 |
|
|
`define HOST_GPU_EXECUTION_DONE 18
|
| 62 |
|
|
|
| 63 |
|
|
//---------------------------------------------------------------
|
| 64 |
|
|
module Module_Host
|
| 65 |
|
|
(
|
| 66 |
|
|
input wire Clock,
|
| 67 |
|
|
input wire Reset,
|
| 68 |
|
|
input wire iEnable,
|
| 69 |
|
|
input wire iHostDataReadConfirmed,
|
| 70 |
|
|
input wire [`WB_WIDTH-1:0] iMemorySize,
|
| 71 |
|
|
input wire [`WB_WIDTH-1:0] iPrimitiveCount,
|
| 72 |
|
|
|
| 73 |
|
|
//To Memory
|
| 74 |
|
|
output wire [`WB_WIDTH-1:0] oReadAddress,
|
| 75 |
|
|
input wire [`WB_WIDTH-1:0] iReadData,
|
| 76 |
|
|
input wire iGPUCommitedResults,
|
| 77 |
|
|
|
| 78 |
|
|
//To Hub/Switch
|
| 79 |
|
|
output wire [`MAX_CORES-1:0] oCoreSelectMask,
|
| 80 |
|
|
output reg [2:0] oMemSelect,
|
| 81 |
|
|
output wire [`WB_WIDTH-1:0] DAT_O,
|
| 82 |
|
|
output wire [`WB_WIDTH-1:0] ADR_O,
|
| 83 |
|
|
output reg[1:0] TGA_O,
|
| 84 |
|
|
output reg[`MAX_CORES-1:0] RENDREN_O,
|
| 85 |
|
|
output wire CYC_O,
|
| 86 |
|
|
output wire STB_O,
|
| 87 |
|
|
output reg MST_O,
|
| 88 |
|
|
output wire WE_O,
|
| 89 |
|
|
input wire GRDY_I, //This means all the cores are done rading the primitive we send
|
| 90 |
|
|
output reg GACK_O, //We set this to ACK that the cored read the primitive
|
| 91 |
|
|
output wire STDONE_O,
|
| 92 |
|
|
output reg oHostDataAvailable,
|
| 93 |
|
|
input wire iGPUDone,
|
| 94 |
|
|
input wire ACK_I
|
| 95 |
|
|
);
|
| 96 |
|
|
//---------------------------------------------------------------
|
| 97 |
|
|
wire wLastPrimitive;
|
| 98 |
|
|
assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
|
| 99 |
|
|
assign STDONE_O = wLastPrimitive;
|
| 100 |
|
|
|
| 101 |
|
|
wire wWBMDone;
|
| 102 |
|
|
reg rWBMEnable,rWBMReset,rCoreBroadCast;
|
| 103 |
|
|
reg [`WB_WIDTH-1:0] rInitiaReadAddr;
|
| 104 |
|
|
wire [`MAX_CORES-1:0] wCoreSelect;
|
| 105 |
|
|
wire wLastValidReadAddress;
|
| 106 |
|
|
wire [`WB_WIDTH-1:0] wWriteAddress;
|
| 107 |
|
|
wire [7:0] wVertexCount;
|
| 108 |
|
|
reg [`WB_WIDTH-1:0] rInitialWriteAddress;
|
| 109 |
|
|
reg rSetWriteAddr;
|
| 110 |
|
|
reg rIncCoreSelect,rResetVertexCount;
|
| 111 |
|
|
//--------------------------------------------------------
|
| 112 |
|
|
|
| 113 |
|
|
assign WE_O = MST_O;
|
| 114 |
|
|
|
| 115 |
|
|
assign oCoreSelectMask =
|
| 116 |
|
|
(rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
|
| 117 |
|
|
|
| 118 |
|
|
assign wLastValidReadAddress =
|
| 119 |
|
|
(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
|
| 120 |
|
|
|
| 121 |
|
|
wire wLastParameter;
|
| 122 |
|
|
assign wLastParameter = (oReadAddress >= 32'h12) ? 1'b1 : 1'b0;
|
| 123 |
|
|
//--------------------------------------------------------
|
| 124 |
|
|
UPCOUNTER_POSEDGE # (`WB_WIDTH ) UPWADDR
|
| 125 |
|
|
(
|
| 126 |
|
|
.Clock( Clock ),
|
| 127 |
|
|
.Reset( Reset | rSetWriteAddr ),
|
| 128 |
|
|
.Enable( iEnable & wWBMDone ),
|
| 129 |
|
|
.Initial( rInitialWriteAddress ),
|
| 130 |
|
|
.Q( wWriteAddress )
|
| 131 |
|
|
);
|
| 132 |
|
|
|
| 133 |
|
|
|
| 134 |
|
|
UPCOUNTER_POSEDGE # (8 ) PRIMCOUNT
|
| 135 |
|
|
(
|
| 136 |
|
|
.Clock( Clock ),
|
| 137 |
|
|
.Reset( Reset | rResetVertexCount ),
|
| 138 |
|
|
.Enable( iEnable & wWBMDone ),
|
| 139 |
|
|
.Initial( 8'b1 ), //WAS 0
|
| 140 |
|
|
.Q( wVertexCount )
|
| 141 |
|
|
);
|
| 142 |
|
|
//--------------------------------------------------------
|
| 143 |
|
|
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
|
| 144 |
|
|
(
|
| 145 |
|
|
.Clock( Clock ),
|
| 146 |
|
|
.Reset( Reset ),
|
| 147 |
|
|
.Initial( `MAX_CORES'b1 ),
|
| 148 |
|
|
.Enable( rIncCoreSelect ),
|
| 149 |
|
|
.O( wCoreSelect )
|
| 150 |
|
|
);
|
| 151 |
|
|
//--------------------------------------------------------
|
| 152 |
|
|
wire wShortCycle;
|
| 153 |
|
|
//For instruction we send 2 packets per cycle
|
| 154 |
|
|
//for the other we send 3 packets per cycle
|
| 155 |
|
|
assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
|
| 156 |
|
|
|
| 157 |
|
|
WBMaster WBM
|
| 158 |
|
|
(
|
| 159 |
|
|
.Clock( Clock ),
|
| 160 |
|
|
.Reset( Reset | rWBMReset ),
|
| 161 |
|
|
.iEnable( rWBMEnable ),
|
| 162 |
|
|
.iInitialReadAddr( rInitiaReadAddr ),
|
| 163 |
|
|
.iWriteAddr( wWriteAddress ),
|
| 164 |
|
|
.oReadAddress( oReadAddress ),
|
| 165 |
|
|
.iReadData( iReadData ),
|
| 166 |
|
|
.iShortFlow( wShortCycle ),
|
| 167 |
|
|
|
| 168 |
|
|
|
| 169 |
|
|
.STB_O( STB_O ),
|
| 170 |
|
|
.ACK_I( ACK_I ),
|
| 171 |
|
|
.CYC_O( CYC_O ),
|
| 172 |
|
|
.DAT_O( DAT_O ),
|
| 173 |
|
|
.ADR_O( ADR_O ),
|
| 174 |
|
|
.oDone( wWBMDone )
|
| 175 |
|
|
);
|
| 176 |
|
|
|
| 177 |
|
|
//--------------------------------------------------------
|
| 178 |
|
|
// Current State Logic //
|
| 179 |
|
|
reg [7:0] rHostCurrentState,rHostNextState;
|
| 180 |
|
|
always @(posedge Clock or posedge Reset)
|
| 181 |
|
|
begin
|
| 182 |
|
|
if( Reset!=1 )
|
| 183 |
|
|
rHostCurrentState <= rHostNextState;
|
| 184 |
|
|
else
|
| 185 |
|
|
rHostCurrentState <= `HOST_IDLE;
|
| 186 |
|
|
end
|
| 187 |
|
|
//--------------------------------------------------------
|
| 188 |
|
|
|
| 189 |
|
|
wire wLastVertexInFrame;
|
| 190 |
|
|
assign wLastVertexInFrame =
|
| 191 |
|
|
(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
|
| 192 |
|
|
|
| 193 |
|
|
// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
|
| 194 |
|
|
|
| 195 |
|
|
reg [31:0] StartTime;
|
| 196 |
|
|
|
| 197 |
|
|
// Host Finite State Machine //
|
| 198 |
|
|
always @( * )
|
| 199 |
|
|
begin
|
| 200 |
|
|
|
| 201 |
|
|
case (rHostCurrentState)
|
| 202 |
|
|
//----------------------------------------
|
| 203 |
|
|
//Wait for reset sequence to complete,
|
| 204 |
|
|
//Or until we are enabled
|
| 205 |
|
|
`HOST_IDLE:
|
| 206 |
|
|
begin
|
| 207 |
|
|
rWBMEnable <= 0;
|
| 208 |
|
|
rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
|
| 209 |
|
|
rWBMReset <= 0;
|
| 210 |
|
|
oMemSelect <= 0;
|
| 211 |
|
|
TGA_O <= 0;
|
| 212 |
|
|
MST_O <= 0;
|
| 213 |
|
|
rInitialWriteAddress <= 0;
|
| 214 |
|
|
rSetWriteAddr <= 0;
|
| 215 |
|
|
rCoreBroadCast <= 0;
|
| 216 |
|
|
rIncCoreSelect <= 0;
|
| 217 |
|
|
RENDREN_O <= 0;
|
| 218 |
|
|
rResetVertexCount <= 0;
|
| 219 |
|
|
GACK_O <= 0;
|
| 220 |
|
|
//STDONE_O <= 0;
|
| 221 |
|
|
oHostDataAvailable <= 0;
|
| 222 |
|
|
|
| 223 |
|
|
if ( ~Reset & iEnable )
|
| 224 |
|
|
rHostNextState <= `HOST_WRITE_INSTRUCTION;
|
| 225 |
|
|
else
|
| 226 |
|
|
rHostNextState <= `HOST_IDLE;
|
| 227 |
|
|
end
|
| 228 |
|
|
//----------------------------------------
|
| 229 |
|
|
//Broadcast the instructions to all the cores
|
| 230 |
|
|
`HOST_WRITE_INSTRUCTION:
|
| 231 |
|
|
begin
|
| 232 |
|
|
|
| 233 |
|
|
StartTime <= $time;
|
| 234 |
|
|
|
| 235 |
|
|
rWBMEnable <= 1; //Enable Wish bone master
|
| 236 |
|
|
rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
|
| 237 |
|
|
rWBMReset <= 0; //No need to reset since we just came from reset
|
| 238 |
|
|
oMemSelect <= `SELECT_INST_MEM; //Start by sending the instructions
|
| 239 |
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
|
| 240 |
|
|
MST_O <= 1;
|
| 241 |
|
|
rInitialWriteAddress <= 0;
|
| 242 |
|
|
rSetWriteAddr <= 0;
|
| 243 |
|
|
rCoreBroadCast <= 1;
|
| 244 |
|
|
rIncCoreSelect <= 0;
|
| 245 |
|
|
RENDREN_O <= 0;
|
| 246 |
|
|
rResetVertexCount <= 0;
|
| 247 |
|
|
GACK_O <= 0;
|
| 248 |
|
|
//STDONE_O <= 0;
|
| 249 |
|
|
oHostDataAvailable <= 0;
|
| 250 |
|
|
|
| 251 |
|
|
rHostNextState <= `HOST_WAIT_INSTRUCTION;
|
| 252 |
|
|
end
|
| 253 |
|
|
//----------------------------------------
|
| 254 |
|
|
`HOST_WAIT_INSTRUCTION:
|
| 255 |
|
|
begin
|
| 256 |
|
|
rWBMEnable <= ~wWBMDone;
|
| 257 |
|
|
rInitiaReadAddr <= 0;
|
| 258 |
|
|
rWBMReset <= 0;
|
| 259 |
|
|
oMemSelect <= `SELECT_INST_MEM;
|
| 260 |
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
|
| 261 |
|
|
MST_O <= 1;
|
| 262 |
|
|
rInitialWriteAddress <= 0;
|
| 263 |
|
|
rSetWriteAddr <= 0;
|
| 264 |
|
|
rCoreBroadCast <= 1;
|
| 265 |
|
|
rIncCoreSelect <= 0;
|
| 266 |
|
|
RENDREN_O <= 0;
|
| 267 |
|
|
rResetVertexCount <= 0;
|
| 268 |
|
|
GACK_O <= 0;
|
| 269 |
|
|
//STDONE_O <= 0;
|
| 270 |
|
|
oHostDataAvailable <= 0;
|
| 271 |
|
|
|
| 272 |
|
|
if ( wWBMDone && ~wLastValidReadAddress )
|
| 273 |
|
|
rHostNextState <= `HOST_WRITE_INSTRUCTION;
|
| 274 |
|
|
else if (wWBMDone && wLastValidReadAddress )
|
| 275 |
|
|
rHostNextState <= `HOST_INITIAL_SCENE_PARAMS_STAGE;
|
| 276 |
|
|
else
|
| 277 |
|
|
rHostNextState <= `HOST_WAIT_INSTRUCTION;
|
| 278 |
|
|
end
|
| 279 |
|
|
//----------------------------------------
|
| 280 |
|
|
/*
|
| 281 |
|
|
Make sure to read-pointer points to the
|
| 282 |
|
|
first memory address at te params memory
|
| 283 |
|
|
*/
|
| 284 |
|
|
`HOST_INITIAL_SCENE_PARAMS_STAGE:
|
| 285 |
|
|
begin
|
| 286 |
|
|
rWBMEnable <= 0;
|
| 287 |
|
|
rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
|
| 288 |
|
|
rWBMReset <= 1;
|
| 289 |
|
|
oMemSelect <= `SELECT_SCENE_MEM; //We are reading from the scene memory
|
| 290 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
|
| 291 |
|
|
MST_O <= 1; //Keep master signal in 1 for now
|
| 292 |
|
|
rInitialWriteAddress <= 0; //We start writing from address zero now
|
| 293 |
|
|
rSetWriteAddr <= 1;
|
| 294 |
|
|
rCoreBroadCast <= 1; //Set to zero to unicast, starting from core 0
|
| 295 |
|
|
rIncCoreSelect <= 0; //Set to unicast to the next core
|
| 296 |
|
|
RENDREN_O <= 0;
|
| 297 |
|
|
rResetVertexCount <= 0;
|
| 298 |
|
|
GACK_O <= 0;
|
| 299 |
|
|
//STDONE_O <= 0;
|
| 300 |
|
|
oHostDataAvailable <= 0;
|
| 301 |
|
|
|
| 302 |
|
|
rHostNextState <= `HOST_WRITE_SCENE_PARAMS;
|
| 303 |
|
|
end
|
| 304 |
|
|
|
| 305 |
|
|
//----------------------------------------
|
| 306 |
|
|
//Broadcast the instructions to all the cores
|
| 307 |
|
|
`HOST_WRITE_SCENE_PARAMS:
|
| 308 |
|
|
begin
|
| 309 |
|
|
rWBMEnable <= 1;
|
| 310 |
|
|
rInitiaReadAddr <= 0;
|
| 311 |
|
|
rWBMReset <= 0;
|
| 312 |
|
|
oMemSelect <= `SELECT_SCENE_MEM;
|
| 313 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 314 |
|
|
MST_O <= 1;
|
| 315 |
|
|
rInitialWriteAddress <= 0;
|
| 316 |
|
|
rSetWriteAddr <= 0;
|
| 317 |
|
|
rCoreBroadCast <= 1;
|
| 318 |
|
|
rIncCoreSelect <= 0;
|
| 319 |
|
|
RENDREN_O <= 0;
|
| 320 |
|
|
rResetVertexCount <= 0;
|
| 321 |
|
|
GACK_O <= 0;
|
| 322 |
|
|
//STDONE_O <= 0;
|
| 323 |
|
|
oHostDataAvailable <= 0;
|
| 324 |
|
|
|
| 325 |
|
|
rHostNextState <= `HOST_WAIT_SCENE_PARAMS;
|
| 326 |
|
|
end
|
| 327 |
|
|
//----------------------------------------
|
| 328 |
|
|
`HOST_WAIT_SCENE_PARAMS:
|
| 329 |
|
|
begin
|
| 330 |
|
|
rWBMEnable <= ~wWBMDone;
|
| 331 |
|
|
rInitiaReadAddr <= 0;
|
| 332 |
|
|
rWBMReset <= 0;
|
| 333 |
|
|
oMemSelect <= `SELECT_SCENE_MEM;
|
| 334 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 335 |
|
|
MST_O <= 1;
|
| 336 |
|
|
rInitialWriteAddress <= 0;
|
| 337 |
|
|
rSetWriteAddr <= 0;
|
| 338 |
|
|
rCoreBroadCast <= 1;
|
| 339 |
|
|
rIncCoreSelect <= 0;
|
| 340 |
|
|
RENDREN_O <= 0;
|
| 341 |
|
|
rResetVertexCount <= 0;
|
| 342 |
|
|
GACK_O <= 0;
|
| 343 |
|
|
//STDONE_O <= 0;
|
| 344 |
|
|
oHostDataAvailable <= 0;
|
| 345 |
|
|
|
| 346 |
|
|
if ( wWBMDone && ~wLastParameter )
|
| 347 |
|
|
rHostNextState <= `HOST_WRITE_SCENE_PARAMS;
|
| 348 |
|
|
else if (wWBMDone && wLastParameter )
|
| 349 |
|
|
rHostNextState <= `HOST_PREPARE_CORE_CONFIG;
|
| 350 |
|
|
else
|
| 351 |
|
|
rHostNextState <= `HOST_WAIT_SCENE_PARAMS;
|
| 352 |
|
|
end
|
| 353 |
|
|
//----------------------------------------
|
| 354 |
|
|
/*
|
| 355 |
|
|
This state set the read Write Address pointer to
|
| 356 |
|
|
CREG_PIXEL_2D_INITIAL_POSITION memory position,
|
| 357 |
|
|
also selects the scene MEM from the external MEM
|
| 358 |
|
|
MUX.
|
| 359 |
|
|
*/
|
| 360 |
|
|
`HOST_PREPARE_CORE_CONFIG:
|
| 361 |
|
|
begin
|
| 362 |
|
|
rWBMEnable <= 0;
|
| 363 |
|
|
rInitiaReadAddr <= 0;
|
| 364 |
|
|
rWBMReset <= 0;
|
| 365 |
|
|
oMemSelect <= `SELECT_SCENE_MEM; //We are reading from the scene memory
|
| 366 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
|
| 367 |
|
|
MST_O <= 1; //Keep master signal in 1 for now
|
| 368 |
|
|
rInitialWriteAddress <= `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
|
| 369 |
|
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
| 370 |
|
|
rCoreBroadCast <= 0; //Set to zero to unicast, starting from core 0
|
| 371 |
|
|
rIncCoreSelect <= 0; //Set to unicast to the next core
|
| 372 |
|
|
RENDREN_O <= 0;
|
| 373 |
|
|
rResetVertexCount <= 0;
|
| 374 |
|
|
GACK_O <= 0;
|
| 375 |
|
|
//STDONE_O <= 0;
|
| 376 |
|
|
oHostDataAvailable <= 0;
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
| 380 |
|
|
end
|
| 381 |
|
|
|
| 382 |
|
|
//----------------------------------------
|
| 383 |
|
|
`HOST_UNICAST_CORE_CONFIG:
|
| 384 |
|
|
begin
|
| 385 |
|
|
rWBMEnable <= 1;
|
| 386 |
|
|
rInitiaReadAddr <= 0;
|
| 387 |
|
|
rWBMReset <= 0;
|
| 388 |
|
|
oMemSelect <= `SELECT_SCENE_MEM;
|
| 389 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 390 |
|
|
MST_O <= 1;
|
| 391 |
|
|
rInitialWriteAddress <= 0;
|
| 392 |
|
|
rSetWriteAddr <= 0;
|
| 393 |
|
|
rCoreBroadCast <= 0;
|
| 394 |
|
|
rIncCoreSelect <= 0;
|
| 395 |
|
|
RENDREN_O <= 0;
|
| 396 |
|
|
rResetVertexCount <= 0;
|
| 397 |
|
|
GACK_O <= 0;
|
| 398 |
|
|
//STDONE_O <= 0;
|
| 399 |
|
|
oHostDataAvailable <= 0;
|
| 400 |
|
|
|
| 401 |
|
|
rHostNextState <= `HOST_WAIT_CORE_CONFIG;
|
| 402 |
|
|
end
|
| 403 |
|
|
//----------------------------------------
|
| 404 |
|
|
`HOST_WAIT_CORE_CONFIG:
|
| 405 |
|
|
begin
|
| 406 |
|
|
rWBMEnable <= ~wWBMDone;
|
| 407 |
|
|
rInitiaReadAddr <= 0;
|
| 408 |
|
|
rWBMReset <= 0;
|
| 409 |
|
|
oMemSelect <= `SELECT_SCENE_MEM;
|
| 410 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 411 |
|
|
MST_O <= 1;
|
| 412 |
|
|
rInitialWriteAddress <= 0;
|
| 413 |
|
|
rSetWriteAddr <= 0;
|
| 414 |
|
|
rCoreBroadCast <= 0;
|
| 415 |
|
|
rIncCoreSelect <= 0;
|
| 416 |
|
|
RENDREN_O <= 0;
|
| 417 |
|
|
rResetVertexCount <= 0;
|
| 418 |
|
|
GACK_O <= 0;
|
| 419 |
|
|
//STDONE_O <= 0;
|
| 420 |
|
|
oHostDataAvailable <= 0;
|
| 421 |
|
|
|
| 422 |
|
|
|
| 423 |
|
|
if (wWBMDone && !(oReadAddress % 2))
|
| 424 |
|
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
| 425 |
|
|
else if (wWBMDone && (oReadAddress % 2) )
|
| 426 |
|
|
rHostNextState <= `HOST_PREPARE_NEXT_CORE_CONFIG;
|
| 427 |
|
|
else
|
| 428 |
|
|
rHostNextState <= `HOST_WAIT_CORE_CONFIG;
|
| 429 |
|
|
|
| 430 |
|
|
end
|
| 431 |
|
|
//----------------------------------------
|
| 432 |
|
|
/*
|
| 433 |
|
|
Reset the WBM to tell it to start reading
|
| 434 |
|
|
from address 0 at the Geometry memory.
|
| 435 |
|
|
*/
|
| 436 |
|
|
`HOST_PREPARE_NEXT_CORE_CONFIG:
|
| 437 |
|
|
begin
|
| 438 |
|
|
rWBMEnable <= 0;
|
| 439 |
|
|
rInitiaReadAddr <= 0;
|
| 440 |
|
|
rWBMReset <= 0;
|
| 441 |
|
|
oMemSelect <= `SELECT_GEO_MEM;
|
| 442 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 443 |
|
|
MST_O <= 0; //The master signal goes to zero until request
|
| 444 |
|
|
rInitialWriteAddress <= `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
|
| 445 |
|
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
| 446 |
|
|
rCoreBroadCast <= 0;
|
| 447 |
|
|
rIncCoreSelect <= 1; //Moving to configure the next core now
|
| 448 |
|
|
RENDREN_O <= 0;
|
| 449 |
|
|
rResetVertexCount <= 0;
|
| 450 |
|
|
GACK_O <= 0;
|
| 451 |
|
|
//STDONE_O <= 0;
|
| 452 |
|
|
oHostDataAvailable <= 0;
|
| 453 |
|
|
|
| 454 |
|
|
if (wCoreSelect[`MAX_CORES-1] == 1)
|
| 455 |
|
|
rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
|
| 456 |
|
|
else
|
| 457 |
|
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
| 458 |
|
|
end
|
| 459 |
|
|
//----------------------------------------
|
| 460 |
|
|
/*
|
| 461 |
|
|
Prepare the write address for the next primitive.
|
| 462 |
|
|
|
| 463 |
|
|
*/
|
| 464 |
|
|
`HOST_PREPARE_FOR_GEO_REQUESTS:
|
| 465 |
|
|
begin
|
| 466 |
|
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
| 467 |
|
|
rInitiaReadAddr <= 32'hA; //Start reading from addr 0 @ GEO MEM
|
| 468 |
|
|
rWBMReset <= 1; //Tell WBM to start reading from the addr bellow
|
| 469 |
|
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
| 470 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
| 471 |
|
|
MST_O <= 0; //The master signal goes to zero until request
|
| 472 |
|
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
| 473 |
|
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
| 474 |
|
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
| 475 |
|
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
| 476 |
|
|
RENDREN_O <= 0;
|
| 477 |
|
|
rResetVertexCount <= 1;
|
| 478 |
|
|
GACK_O <= 0;
|
| 479 |
|
|
//STDONE_O <= 0;
|
| 480 |
|
|
oHostDataAvailable <= 0;
|
| 481 |
|
|
|
| 482 |
|
|
if (iGPUDone)
|
| 483 |
|
|
rHostNextState <= `HOST_GPU_EXECUTION_DONE;
|
| 484 |
|
|
else
|
| 485 |
|
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
| 486 |
|
|
|
| 487 |
|
|
end
|
| 488 |
|
|
//----------------------------------------
|
| 489 |
|
|
`HOST_ACK_GEO_REQUEST:
|
| 490 |
|
|
begin
|
| 491 |
|
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
| 492 |
|
|
rInitiaReadAddr <= 0; //Ignored
|
| 493 |
|
|
rWBMReset <= 0; //Ignored
|
| 494 |
|
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
| 495 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
| 496 |
|
|
MST_O <= 0; //The master signal goes to zero until request
|
| 497 |
|
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
| 498 |
|
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
| 499 |
|
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
| 500 |
|
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
| 501 |
|
|
RENDREN_O <= 0;
|
| 502 |
|
|
rResetVertexCount <= 0;
|
| 503 |
|
|
GACK_O <= 1;
|
| 504 |
|
|
//STDONE_O <= 0;
|
| 505 |
|
|
oHostDataAvailable <= 0;
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
| 509 |
|
|
|
| 510 |
|
|
end
|
| 511 |
|
|
//----------------------------------------
|
| 512 |
|
|
/*
|
| 513 |
|
|
Send the next primitive to the HUB/SWITCH unit
|
| 514 |
|
|
so that it gets broadcasted to all the cores
|
| 515 |
|
|
*/
|
| 516 |
|
|
`HOST_BROADCAST_NEXT_VERTEX:
|
| 517 |
|
|
begin
|
| 518 |
|
|
rWBMEnable <= 1; //Start the Transmition
|
| 519 |
|
|
rInitiaReadAddr <= 0;
|
| 520 |
|
|
rWBMReset <= 0;
|
| 521 |
|
|
oMemSelect <= `SELECT_GEO_MEM;
|
| 522 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 523 |
|
|
MST_O <= 1; //Start the Transmition
|
| 524 |
|
|
rInitialWriteAddress <= 0;
|
| 525 |
|
|
rSetWriteAddr <= 0;
|
| 526 |
|
|
rCoreBroadCast <= 1;
|
| 527 |
|
|
rIncCoreSelect <= 0;
|
| 528 |
|
|
RENDREN_O <= `SELECT_ALL_CORES;
|
| 529 |
|
|
rResetVertexCount <= 0;
|
| 530 |
|
|
GACK_O <= 0;
|
| 531 |
|
|
//STDONE_O <= 0;
|
| 532 |
|
|
oHostDataAvailable <= 0;
|
| 533 |
|
|
|
| 534 |
|
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
| 535 |
|
|
|
| 536 |
|
|
end
|
| 537 |
|
|
//----------------------------------------
|
| 538 |
|
|
`HOST_WAIT_FOR_VERTEX:
|
| 539 |
|
|
begin
|
| 540 |
|
|
rWBMEnable <= ~wWBMDone; //Disable WBM when it is donw
|
| 541 |
|
|
rInitiaReadAddr <= 0;
|
| 542 |
|
|
rWBMReset <= 0;
|
| 543 |
|
|
oMemSelect <= `SELECT_GEO_MEM;
|
| 544 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 545 |
|
|
MST_O <= 1; //Start the Transmition
|
| 546 |
|
|
rInitialWriteAddress <= 0;
|
| 547 |
|
|
rSetWriteAddr <= 0;
|
| 548 |
|
|
rCoreBroadCast <= 1;
|
| 549 |
|
|
rIncCoreSelect <= 0;
|
| 550 |
|
|
RENDREN_O <= `SELECT_ALL_CORES;
|
| 551 |
|
|
rResetVertexCount <= 0;
|
| 552 |
|
|
GACK_O <= 0;
|
| 553 |
|
|
//STDONE_O <= 0;
|
| 554 |
|
|
oHostDataAvailable <= 0;
|
| 555 |
|
|
|
| 556 |
|
|
|
| 557 |
|
|
if (wWBMDone & ~wLastVertexInFrame )
|
| 558 |
|
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
| 559 |
|
|
else if (wWBMDone & wLastVertexInFrame )
|
| 560 |
|
|
rHostNextState <= `HOST_GET_PRIMITIVE_COUNT;
|
| 561 |
|
|
else
|
| 562 |
|
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
| 563 |
|
|
|
| 564 |
|
|
|
| 565 |
|
|
/*
|
| 566 |
|
|
if (wWBMDone)
|
| 567 |
|
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
| 568 |
|
|
else
|
| 569 |
|
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
| 570 |
|
|
*/
|
| 571 |
|
|
end
|
| 572 |
|
|
//----------------------------------------
|
| 573 |
|
|
`HOST_GET_PRIMITIVE_COUNT:
|
| 574 |
|
|
begin
|
| 575 |
|
|
rWBMEnable <= 0; //Disable WBM when it is donw
|
| 576 |
|
|
rInitiaReadAddr <= 0;
|
| 577 |
|
|
rWBMReset <= 0;
|
| 578 |
|
|
oMemSelect <= `SELECT_GEO_MEM;
|
| 579 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 580 |
|
|
MST_O <= 1; //Start the Transmition
|
| 581 |
|
|
rInitialWriteAddress <= 0;
|
| 582 |
|
|
rSetWriteAddr <= 0;
|
| 583 |
|
|
rCoreBroadCast <= 1;
|
| 584 |
|
|
rIncCoreSelect <= 0;
|
| 585 |
|
|
RENDREN_O <= `SELECT_ALL_CORES;
|
| 586 |
|
|
rResetVertexCount <= 0;
|
| 587 |
|
|
GACK_O <= 0;
|
| 588 |
|
|
//STDONE_O <= 0;
|
| 589 |
|
|
oHostDataAvailable <= 0;//1;
|
| 590 |
|
|
|
| 591 |
|
|
if (wVertexCount >= iPrimitiveCount)
|
| 592 |
|
|
rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
|
| 593 |
|
|
else
|
| 594 |
|
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
| 595 |
|
|
|
| 596 |
|
|
end
|
| 597 |
|
|
//----------------------------------------
|
| 598 |
|
|
/*
|
| 599 |
|
|
we wait until all the cores are ready for the next primitive,
|
| 600 |
|
|
this happens when the iHostDataReadConfirmed signal
|
| 601 |
|
|
gets asserted
|
| 602 |
|
|
*/
|
| 603 |
|
|
`HOST_WAIT_DATA_READ_CONFIRMATION:
|
| 604 |
|
|
begin
|
| 605 |
|
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
| 606 |
|
|
rInitiaReadAddr <= 0; //Ignored
|
| 607 |
|
|
rWBMReset <= 0; //Continue from previous read address
|
| 608 |
|
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
| 609 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
| 610 |
|
|
MST_O <= 0; //The master signal goes to zero until request
|
| 611 |
|
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
| 612 |
|
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
| 613 |
|
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
| 614 |
|
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
| 615 |
|
|
RENDREN_O <= `SELECT_ALL_CORES;
|
| 616 |
|
|
rResetVertexCount <= 0;
|
| 617 |
|
|
GACK_O <= 0;
|
| 618 |
|
|
//STDONE_O <= 0;
|
| 619 |
|
|
oHostDataAvailable <= 1;
|
| 620 |
|
|
|
| 621 |
|
|
if ( iHostDataReadConfirmed )
|
| 622 |
|
|
rHostNextState <= `HOST_ACK_GEO_REQUEST;
|
| 623 |
|
|
else
|
| 624 |
|
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
| 625 |
|
|
end
|
| 626 |
|
|
//----------------------------------------
|
| 627 |
|
|
`HOST_LAST_PRIMITIVE_REACHED:
|
| 628 |
|
|
begin
|
| 629 |
|
|
rWBMEnable <= 0; //Disable WBM when it is donw
|
| 630 |
|
|
rInitiaReadAddr <= 32'hA; //Reset primitive counter to first primitive
|
| 631 |
|
|
rWBMReset <= 1; //Reset primitive counter to first primitive
|
| 632 |
|
|
oMemSelect <= `SELECT_GEO_MEM;
|
| 633 |
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
| 634 |
|
|
MST_O <= 1;
|
| 635 |
|
|
rInitialWriteAddress <= 0;
|
| 636 |
|
|
rSetWriteAddr <= 0;
|
| 637 |
|
|
rCoreBroadCast <= 1;
|
| 638 |
|
|
rIncCoreSelect <= 0;
|
| 639 |
|
|
RENDREN_O <= `SELECT_ALL_CORES;
|
| 640 |
|
|
rResetVertexCount <= 0; //Reset the vertex count to zero
|
| 641 |
|
|
GACK_O <= 0;
|
| 642 |
|
|
//STDONE_O <= 1;
|
| 643 |
|
|
oHostDataAvailable <= 0;
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
|
|
if (iGPUCommitedResults)
|
| 647 |
|
|
rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
|
| 648 |
|
|
else
|
| 649 |
|
|
rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
|
| 650 |
|
|
end
|
| 651 |
|
|
//----------------------------------------
|
| 652 |
|
|
`HOST_GPU_EXECUTION_DONE:
|
| 653 |
|
|
begin
|
| 654 |
|
|
$display("THEIA Execution done in %dns\n",$time-StartTime);
|
| 655 |
|
|
rWBMEnable <= 0;
|
| 656 |
|
|
rInitiaReadAddr <= 0;
|
| 657 |
|
|
rWBMReset <= 0;
|
| 658 |
|
|
oMemSelect <= 0;
|
| 659 |
|
|
TGA_O <= 0;
|
| 660 |
|
|
MST_O <= 0;
|
| 661 |
|
|
rInitialWriteAddress <= 0;
|
| 662 |
|
|
rSetWriteAddr <= 0;
|
| 663 |
|
|
rCoreBroadCast <= 0;
|
| 664 |
|
|
rIncCoreSelect <= 0;
|
| 665 |
|
|
RENDREN_O <= 0;
|
| 666 |
|
|
rResetVertexCount <= 0;
|
| 667 |
|
|
GACK_O <= 0;
|
| 668 |
|
|
//STDONE_O <= 0;
|
| 669 |
|
|
oHostDataAvailable <= 0;
|
| 670 |
|
|
|
| 671 |
|
|
rHostNextState <= `HOST_GPU_EXECUTION_DONE;
|
| 672 |
|
|
end
|
| 673 |
|
|
//----------------------------------------
|
| 674 |
|
|
default:
|
| 675 |
|
|
begin
|
| 676 |
|
|
|
| 677 |
|
|
rWBMEnable <= 0;
|
| 678 |
|
|
rInitiaReadAddr <= 0;
|
| 679 |
|
|
rWBMReset <= 0;
|
| 680 |
|
|
oMemSelect <= 0;
|
| 681 |
|
|
TGA_O <= 0;
|
| 682 |
|
|
MST_O <= 0;
|
| 683 |
|
|
rInitialWriteAddress <= 0;
|
| 684 |
|
|
rSetWriteAddr <= 0;
|
| 685 |
|
|
rCoreBroadCast <= 0;
|
| 686 |
|
|
rIncCoreSelect <= 0;
|
| 687 |
|
|
RENDREN_O <= 0;
|
| 688 |
|
|
rResetVertexCount <= 0;
|
| 689 |
|
|
GACK_O <= 0;
|
| 690 |
|
|
//STDONE_O <= 0;
|
| 691 |
|
|
oHostDataAvailable <= 0;
|
| 692 |
|
|
|
| 693 |
|
|
rHostNextState <= `HOST_IDLE;
|
| 694 |
|
|
end
|
| 695 |
|
|
//----------------------------------------
|
| 696 |
|
|
endcase
|
| 697 |
|
|
end
|
| 698 |
|
|
|
| 699 |
|
|
endmodule
|
