URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [gpu_8_cores/] [rtl/] [Collaterals/] [Collaterals.v] - Blame information for rev 187

Go to most recent revision | Details | Compare with Previous | View Log


`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
//------------------------------------------------
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
        (
        input wire Clock,
        input wire Clear,
        input wire [SIZE-1:0] D,
        output reg [SIZE-1:0] Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 0;
      else
        Q = D;
    end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Enable,
        input wire [SIZE-1:0]    D,
        output reg [SIZE-1:0]    Q
);
 
 
always @ (posedge Clock)
begin
        if ( Reset )
                Q <= `WIDTH'b0;
        else
        begin
                if (Enable)
                        Q <= D;
        end
 
end//always
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
 
  always @(posedge Clock )
  begin
      if (Reset)
        Q = Initial;
      else
                begin
                if (Enable)
                        Q = Q + 1;
 
                end
  end
 
endmodule
 
//----------------------------------------------------------------------
 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
 (
 input wire [SEL_WIDTH-1:0] Sel,
 input wire  En,
 output wire [OUTPUT_WIDTH-1:0] O
 );
 
reg[OUTPUT_WIDTH-1:0] shift;
 
always @ ( * )
begin
        if (~En)
                shift = 1;
        else
                shift = (1 <<   Sel);
 
 
end
 
assign O = ( ~En ) ? 0 : shift ;
 
//assign O = En & (1 << Sel);
 
endmodule
 
//----------------------------------------------------------------------
 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 (
 input wire [1:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,I4,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                2'b11: O1 = I4;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
 
/*
module MUXFULLPARALELL_CORESELECT # ( parameter SIZE=`WIDTH )
 (
 input wire [`MAX_CORES-1:0] Sel,
 input wire [SIZE-1:0] I1[`MAX_CORES-1:0],
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
        genvar i;
   generate
                for (i = 0; i < `MAX_CORES; i = i +1)
                begin : CORE
                        `MAX_CORES'di: O1 = I1[i];
 
 
                end
        endgenerate
         default: O1 = SIZE-1'b0;
    endcase
 
  end
 
endmodule
*/
//--------
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                begin
                        if (tmp[SIZE-1])
                        begin
                                tmp <= Initial;
                        end
                        else
                        begin
                                tmp <= tmp << 1;
                        end
                end
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
 (
 input wire [2:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      3'b001: O1 = I1;
      3'b010: O1 = I2;
                3'b100: O1 = I3;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
//------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset || tmp[SIZE-1])
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//-----------------------------------------------------------
/*
        Sorry forgot how this flop is called.
        Any way Truth table is this
 
        Q       S       Q_next R
 
 
        1       0        1                0
        1       1       1                0
        X       X       0                 1
 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
        gets another S = 1, it keeps the output to 1.
*/
module FFToggleOnce_1Bit
(
        input wire Clock,
        input wire Reset,
        input wire Enable,
        input wire S,
        output reg Q
 
);
 
 
reg Q_next;
 
always @ (negedge Clock)
begin
        Q <= Q_next;
end
 
always @ ( posedge Clock )
begin
        if (Reset)
                Q_next <= 0;
        else if (Enable)
                Q_next <= (S && !Q) || Q;
        else
                Q_next <= Q;
end
endmodule
 
//--------------------------------------------------------------
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//-----------------------------------------------------------
 
/*
module UpCounterXXX_16
(
input wire Clock, Reset,
input wire [15:0] Initial,
output reg [15:0] Q
);
 
 
  always @(posedge Clock )
    begin
      if (Reset)
        Q = Initial;
      else
        Q = Q + 1'b1;
      end
 
endmodule
*/
//-----------------------------------------------------------
module UpCounter_16E
(
input wire Clock,
input wire Reset,
input wire [15:0] Initial,
input wire Enable,
output wire [15:0] Q
);
        reg [15:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 1'b1;
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_32
(
input wire Clock,
input wire Reset,
input wire [31:0] Initial,
input wire Enable,
output wire [31:0] Q
);
        reg [31:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
                begin
         Temp = Initial;
                end
      else
                begin
                        if (Enable)
                        begin
                                Temp =  Temp + 1'b1;
                        end
                end
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_3
(
input wire Clock,
input wire Reset,
input wire [2:0] Initial,
input wire Enable,
output wire [2:0] Q
);
        reg [2:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 3'b1;
  end
        assign Q = Temp;
 
endmodule
 
 
module FFD32_POSEDGE
(
        input wire Clock,
        input wire[31:0] D,
        output reg[31:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
 
//------------------------------------------------
/*
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
        output reg[`INSTRUCTION_OP_LENGTH-1:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = `INSTRUCTION_OP_LENGTH'b0;
      else
        Q = D;
    end
endmodule
//------------------------------------------------
 
module FF32_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[31:0] D,
        output reg[31:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 32'b0;
      else
        Q = D;
    end
endmodule
//------------------------------------------------
 
module FF16_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[15:0] D,
        output reg[15:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 16'b0;
      else
        Q = D;
    end
endmodule
*/
//------------------------------------------------
module MUXFULLPARALELL_96bits_2SEL
 (
 input wire Sel,
 input wire [95:0]I1, I2,
 output reg [95:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
 
module MUXFULLPARALELL_16bits_2SEL_X
 (
 input wire [1:0] Sel,
 input wire [15:0]I1, I2, I3,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                default: O1 = 16'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
 (
 input wire Sel,
 input wire [15:0]I1, I2,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
 
//------------------------------------------------
/*
module MUXFULLPARALELL_1Bit_1SEL
 (
 input wire Sel,
 input wire I1, I2,
 output reg O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD_OPCODE_POSEDGE
(
        input wire Clock,
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
        output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD16_POSEDGE
(
        input wire Clock,
        input wire[15:0] D,
        output reg[15:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
*/
//--------------------------------------------------------------
 
  module FFT1
  (
   input wire D,
   input wire Clock,
   input wire Reset ,
   output reg Q
 );
 
  always @ ( posedge Clock or posedge Reset )
  begin
 
        if (Reset)
        begin
    Q <= 1'b0;
   end
        else
        begin
                if (D)
                        Q <=  ! Q;
        end
 
  end//always
 
 endmodule
//--------------------------------------------------------------

Browse

Tools

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [gpu_8_cores/] [rtl/] [Collaterals/] [Collaterals.v] - Blame information for rev 187

Line No.	Rev	Author	Line
1	36	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`//------------------------------------------------`
23			module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
24			`(`
25			`input wire Clock,`
26			`input wire Clear,`
27			`input wire [SIZE-1:0] D,`
28			`output reg [SIZE-1:0] Q`
29			`);`
30
31			`always @(posedge Clock or posedge Clear)`
32			`begin`
33			`if (Clear)`
34			`Q = 0;`
35			`else`
36			`Q = D;`
37			`end`
38			`endmodule`
39			`//----------------------------------------------------`
40			module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
41			`(`
42			`input wire Clock,`
43			`input wire Reset,`
44			`input wire Enable,`
45			`input wire [SIZE-1:0] D,`
46			`output reg [SIZE-1:0] Q`
47			`);`
48
49
50			`always @ (posedge Clock)`
51			`begin`
52			`if ( Reset )`
53			Q <= `WIDTH'b0;
54			`else`
55			`begin`
56			`if (Enable)`
57			`Q <= D;`
58			`end`
59
60			`end//always`
61
62			`endmodule`
63			`//------------------------------------------------`
64			module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
65			`(`
66			`input wire Clock, Reset,`
67			`input wire [SIZE-1:0] Initial,`
68			`input wire Enable,`
69			`output reg [SIZE-1:0] Q`
70			`);`
71
72
73			`always @(posedge Clock )`
74			`begin`
75			`if (Reset)`
76			`Q = Initial;`
77			`else`
78			`begin`
79			`if (Enable)`
80			`Q = Q + 1;`
81
82			`end`
83			`end`
84
85			`endmodule`
86	104	diegovalve
87			`//----------------------------------------------------------------------`
88
89			`module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )`
90			`(`
91			`input wire [SEL_WIDTH-1:0] Sel,`
92			`input wire En,`
93			`output wire [OUTPUT_WIDTH-1:0] O`
94			`);`
95
96			`reg[OUTPUT_WIDTH-1:0] shift;`
97
98			`always @ ( * )`
99			`begin`
100			`if (~En)`
101			`shift = 1;`
102			`else`
103			`shift = (1 << Sel);`
104
105
106			`end`
107
108			`assign O = ( ~En ) ? 0 : shift ;`
109
110			`//assign O = En & (1 << Sel);`
111	70	diegovalve
112	104	diegovalve	`endmodule`
113
114			`//----------------------------------------------------------------------`
115	76	diegovalve
116	36	diegovalve	module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
117			`(`
118			`input wire [1:0] Sel,`
119	76	diegovalve	`input wire [SIZE-1:0]I1, I2, I3,I4,`
120	36	diegovalve	`output reg [SIZE-1:0] O1`
121			`);`
122
123			`always @( * )`
124
125			`begin`
126
127			`case (Sel)`
128
129			`2'b00: O1 = I1;`
130			`2'b01: O1 = I2;`
131	76	diegovalve	`2'b10: O1 = I3;`
132			`2'b11: O1 = I4;`
133	36	diegovalve	`default: O1 = SIZE-1'b0;`
134
135			`endcase`
136
137			`end`
138
139			`endmodule`
140	104	diegovalve
141			`/*`
142			module MUXFULLPARALELL_CORESELECT # ( parameter SIZE=`WIDTH )
143			`(`
144			input wire [`MAX_CORES-1:0] Sel,
145			input wire [SIZE-1:0] I1[`MAX_CORES-1:0],
146			`output reg [SIZE-1:0] O1`
147			`);`
148	36	diegovalve
149	104	diegovalve	`always @( * )`
150
151			`begin`
152
153			`case (Sel)`
154			`genvar i;`
155			`generate`
156			for (i = 0; i < `MAX_CORES; i = i +1)
157			`begin : CORE`
158			`MAX_CORES'di: O1 = I1[i];
159
160
161			`end`
162			`endgenerate`
163			`default: O1 = SIZE-1'b0;`
164			`endcase`
165
166			`end`
167
168			`endmodule`
169			`*/`
170	76	diegovalve	`//--------`
171			module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
172			`( input wire Clock,`
173			`input wire Reset,`
174			`input wire[SIZE-1:0] Initial,`
175	104	diegovalve	`input wire Enable,`
176	76	diegovalve	`output wire[SIZE-1:0] O`
177			`);`
178
179			`reg [SIZE-1:0] tmp;`
180
181
182			`always @(posedge Clock)`
183			`begin`
184			`if (Reset)`
185			`tmp <= Initial;`
186			`else`
187			`begin`
188			`if (Enable)`
189			`begin`
190			`if (tmp[SIZE-1])`
191	104	diegovalve	`begin`
192	76	diegovalve	`tmp <= Initial;`
193	104	diegovalve	`end`
194			`else`
195			`begin`
196	76	diegovalve	`tmp <= tmp << 1;`
197	104	diegovalve	`end`
198	76	diegovalve	`end`
199			`end`
200			`end`
201
202
203			`assign O = tmp;`
204			`endmodule`
205	36	diegovalve	`//------------------------------------------------`
206			module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
207			`(`
208			`input wire [2:0] Sel,`
209			`input wire [SIZE-1:0]I1, I2, I3,`
210			`output reg [SIZE-1:0] O1`
211			`);`
212
213			`always @( * )`
214
215			`begin`
216
217			`case (Sel)`
218
219			`3'b001: O1 = I1;`
220			`3'b010: O1 = I2;`
221			`3'b100: O1 = I3;`
222			`default: O1 = SIZE-1'b0;`
223
224			`endcase`
225
226			`end`
227
228			`endmodule`
229			`//------------------------------------------------`
230			module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
231			`( input wire Clock,`
232			`input wire Reset,`
233			`input wire[SIZE-1:0] Initial,`
234			`input wire Enable,`
235			`output wire[SIZE-1:0] O`
236			`);`
237
238			`reg [SIZE-1:0] tmp;`
239
240
241			`always @(posedge Clock)`
242			`begin`
243			`if (Reset)`
244			`tmp <= Initial;`
245			`else`
246			`begin`
247			`if (Enable)`
248			`tmp <= tmp << 1;`
249			`end`
250			`end`
251
252
253			`assign O = tmp;`
254			`endmodule`
255			`//------------------------------------------------`
256			`//------------------------------------------------`
257			module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
258			`( input wire Clock,`
259			`input wire Reset,`
260			`input wire[SIZE-1:0] Initial,`
261			`input wire Enable,`
262			`output wire[SIZE-1:0] O`
263			`);`
264
265			`reg [SIZE-1:0] tmp;`
266
267
268			`always @(posedge Clock)`
269			`begin`
270			`if (Reset \|\| tmp[SIZE-1])`
271			`tmp <= Initial;`
272			`else`
273			`begin`
274			`if (Enable)`
275			`tmp <= tmp << 1;`
276			`end`
277			`end`
278
279
280			`assign O = tmp;`
281			`endmodule`
282			`//-----------------------------------------------------------`
283			`/*`
284			`Sorry forgot how this flop is called.`
285			`Any way Truth table is this`
286
287			`Q S Q_next R`
288
289
290			`1 0 1 0`
291			`1 1 1 0`
292			`X X 0 1`
293
294			`The idea is that it toggles from 0 to 1 when S = 1, but if it`
295			`gets another S = 1, it keeps the output to 1.`
296			`*/`
297			`module FFToggleOnce_1Bit`
298			`(`
299			`input wire Clock,`
300			`input wire Reset,`
301			`input wire Enable,`
302			`input wire S,`
303			`output reg Q`
304
305			`);`
306
307
308			`reg Q_next;`
309
310			`always @ (negedge Clock)`
311			`begin`
312			`Q <= Q_next;`
313			`end`
314
315			`always @ ( posedge Clock )`
316			`begin`
317			`if (Reset)`
318			`Q_next <= 0;`
319			`else if (Enable)`
320			`Q_next <= (S && !Q) \|\| Q;`
321			`else`
322			`Q_next <= Q;`
323			`end`
324			`endmodule`
325
326			`//--------------------------------------------------------------`
327			`//**********************OLD MODS*************************//`
328			`//**********************OLD MODS*************************//`
329			`//**********************OLD MODS*************************//`
330			`//**********************OLD MODS*************************//`
331			`//-----------------------------------------------------------`
332
333			`/*`
334			`module UpCounterXXX_16`
335			`(`
336			`input wire Clock, Reset,`
337			`input wire [15:0] Initial,`
338			`output reg [15:0] Q`
339			`);`
340
341
342			`always @(posedge Clock )`
343			`begin`
344			`if (Reset)`
345			`Q = Initial;`
346			`else`
347			`Q = Q + 1'b1;`
348			`end`
349
350			`endmodule`
351			`*/`
352			`//-----------------------------------------------------------`
353			`module UpCounter_16E`
354			`(`
355			`input wire Clock,`
356			`input wire Reset,`
357			`input wire [15:0] Initial,`
358			`input wire Enable,`
359			`output wire [15:0] Q`
360			`);`
361			`reg [15:0] Temp;`
362
363
364			`always @(posedge Clock or posedge Reset)`
365			`begin`
366			`if (Reset)`
367			`Temp = Initial;`
368			`else`
369			`if (Enable)`
370			`Temp = Temp + 1'b1;`
371			`end`
372			`assign Q = Temp;`
373
374			`endmodule`
375			`//-----------------------------------------------------------`
376			`module UpCounter_32`
377			`(`
378			`input wire Clock,`
379			`input wire Reset,`
380			`input wire [31:0] Initial,`
381			`input wire Enable,`
382			`output wire [31:0] Q`
383			`);`
384			`reg [31:0] Temp;`
385
386
387			`always @(posedge Clock or posedge Reset)`
388			`begin`
389			`if (Reset)`
390			`begin`
391			`Temp = Initial;`
392			`end`
393			`else`
394			`begin`
395			`if (Enable)`
396			`begin`
397			`Temp = Temp + 1'b1;`
398			`end`
399			`end`
400			`end`
401			`assign Q = Temp;`
402
403			`endmodule`
404			`//-----------------------------------------------------------`
405			`module UpCounter_3`
406			`(`
407			`input wire Clock,`
408			`input wire Reset,`
409			`input wire [2:0] Initial,`
410			`input wire Enable,`
411			`output wire [2:0] Q`
412			`);`
413			`reg [2:0] Temp;`
414
415
416			`always @(posedge Clock or posedge Reset)`
417			`begin`
418			`if (Reset)`
419			`Temp = Initial;`
420			`else`
421			`if (Enable)`
422			`Temp = Temp + 3'b1;`
423			`end`
424			`assign Q = Temp;`
425
426			`endmodule`
427
428
429			`module FFD32_POSEDGE`
430			`(`
431			`input wire Clock,`
432			`input wire[31:0] D,`
433			`output reg[31:0] Q`
434			`);`
435
436			`always @ (posedge Clock)`
437			`Q <= D;`
438
439			`endmodule`
440
441			`//------------------------------------------------`
442	70	diegovalve	`/*`
443	36	diegovalve	`module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET`
444			`(`
445			`input wire Clock,`
446			`input wire Clear,`
447			input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
448			output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
449			`);`
450
451			`always @(posedge Clock or posedge Clear)`
452			`begin`
453			`if (Clear)`
454			Q = `INSTRUCTION_OP_LENGTH'b0;
455			`else`
456			`Q = D;`
457			`end`
458			`endmodule`
459			`//------------------------------------------------`
460	70	diegovalve
461	36	diegovalve	`module FF32_POSEDGE_SYNCRONOUS_RESET`
462			`(`
463			`input wire Clock,`
464			`input wire Clear,`
465			`input wire[31:0] D,`
466			`output reg[31:0] Q`
467			`);`
468
469			`always @(posedge Clock or posedge Clear)`
470			`begin`
471			`if (Clear)`
472			`Q = 32'b0;`
473			`else`
474			`Q = D;`
475			`end`
476			`endmodule`
477			`//------------------------------------------------`
478	63	diegovalve
479	36	diegovalve	`module FF16_POSEDGE_SYNCRONOUS_RESET`
480			`(`
481			`input wire Clock,`
482			`input wire Clear,`
483			`input wire[15:0] D,`
484			`output reg[15:0] Q`
485			`);`
486
487			`always @(posedge Clock or posedge Clear)`
488			`begin`
489			`if (Clear)`
490			`Q = 16'b0;`
491			`else`
492			`Q = D;`
493			`end`
494			`endmodule`
495	70	diegovalve	`*/`
496	36	diegovalve	`//------------------------------------------------`
497			`module MUXFULLPARALELL_96bits_2SEL`
498			`(`
499			`input wire Sel,`
500			`input wire [95:0]I1, I2,`
501			`output reg [95:0] O1`
502			`);`
503
504
505
506			`always @( * )`
507
508			`begin`
509
510			`case (Sel)`
511
512			`1'b0: O1 = I1;`
513			`1'b1: O1 = I2;`
514
515			`endcase`
516
517			`end`
518
519			`endmodule`
520			`//------------------------------------------------`
521
522			`module MUXFULLPARALELL_16bits_2SEL_X`
523			`(`
524			`input wire [1:0] Sel,`
525			`input wire [15:0]I1, I2, I3,`
526			`output reg [15:0] O1`
527			`);`
528
529
530
531			`always @( * )`
532
533			`begin`
534
535			`case (Sel)`
536
537			`2'b00: O1 = I1;`
538			`2'b01: O1 = I2;`
539			`2'b10: O1 = I3;`
540			`default: O1 = 16'b0;`
541
542			`endcase`
543
544			`end`
545
546			`endmodule`
547			`//------------------------------------------------`
548			`module MUXFULLPARALELL_16bits_2SEL`
549			`(`
550			`input wire Sel,`
551			`input wire [15:0]I1, I2,`
552			`output reg [15:0] O1`
553			`);`
554
555
556
557			`always @( * )`
558
559			`begin`
560
561			`case (Sel)`
562
563			`1'b0: O1 = I1;`
564			`1'b1: O1 = I2;`
565
566			`endcase`
567
568			`end`
569
570			`endmodule`
571
572
573			`//------------------------------------------------`
574	63	diegovalve	`/*`
575	36	diegovalve	`module MUXFULLPARALELL_1Bit_1SEL`
576			`(`
577			`input wire Sel,`
578			`input wire I1, I2,`
579			`output reg O1`
580			`);`
581
582
583
584			`always @( * )`
585
586			`begin`
587
588			`case (Sel)`
589
590			`1'b0: O1 = I1;`
591			`1'b1: O1 = I2;`
592
593			`endcase`
594
595			`end`
596
597			`endmodule`
598	63	diegovalve	`*/`
599	36	diegovalve	`//--------------------------------------------------------------`
600	63	diegovalve	`/*`
601	36	diegovalve	`module FFD_OPCODE_POSEDGE`
602			`(`
603			`input wire Clock,`
604			input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
605			output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
606			`);`
607
608			`always @ (posedge Clock)`
609			`Q <= D;`
610
611			`endmodule`
612	63	diegovalve	`*/`
613	36	diegovalve	`//--------------------------------------------------------------`
614	63	diegovalve	`/*`
615	36	diegovalve	`module FFD16_POSEDGE`
616			`(`
617			`input wire Clock,`
618			`input wire[15:0] D,`
619			`output reg[15:0] Q`
620			`);`
621
622			`always @ (posedge Clock)`
623			`Q <= D;`
624
625			`endmodule`
626	63	diegovalve	`*/`
627	36	diegovalve	`//--------------------------------------------------------------`
628
629			`module FFT1`
630			`(`
631			`input wire D,`
632			`input wire Clock,`
633			`input wire Reset ,`
634			`output reg Q`
635			`);`
636
637			`always @ ( posedge Clock or posedge Reset )`
638			`begin`
639
640			`if (Reset)`
641			`begin`
642			`Q <= 1'b0;`
643			`end`
644			`else`
645			`begin`
646			`if (D)`
647			`Q <= ! Q;`
648			`end`
649
650			`end//always`
651
652			`endmodule`
653			`//--------------------------------------------------------------`