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URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

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1 76 diegovalve
/**********************************************************************************
2
Theia, Ray Cast Programable graphic Processing Unit.
3
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
4
 
5
This program is free software; you can redistribute it and/or
6
modify it under the terms of the GNU General Public License
7
as published by the Free Software Foundation; either version 2
8
of the License, or (at your option) any later version.
9
 
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14
 
15
You should have received a copy of the GNU General Public License
16
along with this program; if not, write to the Free Software
17
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18
 
19
***********************************************************************************/
20
 
21
/**********************************************************************************
22
Description:
23
 This is the top level block for THEIA.
24
 THEIA core has 5 main logical blocks called Units.
25
 This module implements the interconections between the Units.
26
 
27
 Units:
28
  > EXE: Mananges execution logic for the SHADERS.
29
  > GEO: Manages geometry data structures.
30
  > IO: Input/Output (Wishbone).
31
  > MEM: Internal memory, separate for Instructions and data.
32
  > CONTROL: Main control Finite state machine.
33
 
34
 Internal Buses:
35
        THEIA has separate instruction and data buses.
36
        THEIA avoids using tri-state buses by having separate input/output
37
        for each bus.
38
        There are 2 separate data buses since the Data memory
39
        has a Dual read channel.
40
   Please see the MEM unit chapter in the documentation for more details.
41
 
42
 External Buses:
43
        External buses are managed by the IO Unit.
44
        External buses follow the wishbone protocol.
45
        Please see the IO unit chapter in the documentation for more details.
46
**********************************************************************************/
47
 
48
`timescale 1ns / 1ps
49
`include "aDefinitions.v"
50
 
51
module THEIACORE
52
(
53
 
54
input wire                    CLK_I,    //Input clock
55
input wire                    RST_I,    //Input reset
56
//Theia Interfaces
57
input wire                    MST_I,    //Master signal, THEIA enters configuration mode
58
                                       //when this gets asserted (see documentation)
59
//Wish Bone Interface
60
input wire [`WB_WIDTH-1:0]    DAT_I,     //Input data bus  (Wishbone)
61
output wire [`WB_WIDTH-1:0]   DAT_O,     //Output data bus (Wishbone)
62
input wire                    ACK_I,    //Input ack
63
output wire                   ACK_O,    //Output ack
64
output wire [`WB_WIDTH-1:0]   ADR_O,     //Output address
65
input wire [`WB_WIDTH-1:0]    ADR_I,     //Input address
66
output wire                   WE_O,             //Output write enable
67
input wire                    WE_I,    //Input write enable
68
output wire                   STB_O,    //Strobe signal, see wishbone documentation
69
input wire                    STB_I,    //Strobe signal, see wishbone documentation
70
output wire                   CYC_O,    //Bus cycle signal, see wishbone documentation
71
input wire                    CYC_I,   //Bus cycle signal, see wishbone documentation
72
output wire     [1:0]             TGC_O,   //Bus cycle tag, see THEAI documentation
73
input wire [1:0]              TGA_I,   //Input address tag, see THEAI documentation
74
output wire [1:0]             TGA_O,   //Output address tag, see THEAI documentation
75 105 diegovalve
input wire      [1:0]             TGC_I,   //Bus cycle tag, see THEAI documentation
76
input wire                    GNT_I,   //Bus arbiter 'Granted' signal, see THEAI documentation
77 76 diegovalve
input wire                    RENDREN_I,
78 105 diegovalve
 
79
output wire                  GRDY_O,            //Data Latched
80
input wire                   STDONE_I,          //Scene traverse complete
81
input wire                   HDA_I,
82
output wire                  RCOMMIT_O,
83
 
84
output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
85
output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
86
output wire                                              OMEM_WE_O,
87
 
88
input wire                  TMEM_ACK_I,
89
input wire [`WB_WIDTH-1:0]  TMEM_DAT_I ,
90
output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
91
output wire                 TMEM_WE_O,
92
output wire                 TMEM_STB_O,
93
output wire                 TMEM_CYC_O,
94
input wire                  TMEM_GNT_I,
95
 
96
`ifdef DEBUG
97
input wire[`MAX_CORES-1:0]    iDebug_CoreID,
98 76 diegovalve
`endif
99
//Control Register
100 105 diegovalve
input wire [15:0]                         CREG_I,
101 76 diegovalve
output wire                   DONE_O
102
 
103
 
104
);
105 105 diegovalve
 
106
//When we flip the SMEM, this means we are ready to receive more data
107
assign GRDY_O = wCU2_FlipMem;
108 76 diegovalve
 
109
//Alias this signals
110
wire Clock,Reset;
111
assign Clock = CLK_I;
112
assign Reset = RST_I;
113 105 diegovalve
 
114 82 diegovalve
wire                              wIO_Busy;
115 76 diegovalve
wire [`DATA_ROW_WIDTH-1:0]                        wEXE_2__MEM_WriteData;
116
wire [`DATA_ROW_WIDTH-1:0]                        wUCODE_RAMBus;
117
wire [`DATA_ADDRESS_WIDTH-1:0]    wEXE_2__MEM_wDataWriteAddress;
118
wire                              w2IO__AddrIsImm;
119
wire [`DATA_ADDRESS_WIDTH-1:0]    wUCODE_RAMAddress;
120
wire [`DATA_ADDRESS_WIDTH-1:0]    w2IO__Adr_O_Pointer;
121
wire [`DATA_ADDRESS_WIDTH-1:0]    wGEO2_IO__Adr_O_Pointer;
122
wire                                                                             wEXE_2__DataWriteEnable;
123
wire                                                                             wUCODE_RAMWriteEnable;
124 117 diegovalve
//wire [2:0]                                                             RamBusOwner;
125 76 diegovalve
//Unit intercoanection wires
126
 
127
wire                                                                            wCU2__MicrocodeExecutionDone;
128
wire [`ROM_ADDRESS_WIDTH-1:0]            InitialCodeAddress;
129
wire [`ROM_ADDRESS_WIDTH-1:0]            wInstructionPointer1,wInstructionPointer2;
130
wire [`INSTRUCTION_WIDTH-1:0]    wEncodedInstruction1,wEncodedInstruction2,wIO2_MEM__ExternalInstruction;
131
wire                                                                            wCU2__ExecuteMicroCode;
132
wire  [`ROM_ADDRESS_WIDTH-1:0]   wIO2_MEM__InstructionWriteAddr;
133
wire [95:0]                                                      wMEM_2__EXE_DataRead0, wMEM_2__EXE_DataRead1,wMEM_2__IO_DataRead0, wMEM_2__IO_DataRead1;
134
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE_2__MEM_DataReadAddress0,wEXE_2__MEM_DataReadAddress1;
135
wire [`DATA_ADDRESS_WIDTH-1:0]   wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
136
 
137
 
138
wire [`WIDTH-1:0]                                        w2IO__AddressOffset;
139
wire [`DATA_ADDRESS_WIDTH-1:0]   w2IO__DataWriteAddress;
140
wire                                                                            w2IO__Store;
141
wire                                                                            w2IO__EnableWBMaster;
142
 
143
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO2_MEM__DataWriteAddress;
144
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO_2_MEM__DataReadAddress0;
145
wire [`DATA_ROW_WIDTH-1:0]               wIO2_MEM__Bus;
146
wire [`WIDTH-1:0]                                        wIO2_MEM__Data;
147
wire [`WIDTH-1:0]                                        wIO2_WBM__Address;
148
wire                                                                            wIO2_MEM__DataWriteEnable;
149
wire                                                                            wIO2__Done;
150
wire                                                                            wCU2_GEO__GeometryFetchEnable;
151
wire                                                                            wIFU2__MicroCodeReturnValue;
152
wire                                                                            wCU2_BCU__ACK;
153
wire                                                                            wGEO2_CU__RequestAABBIU;
154
wire                                                                            wGEO2_CU__RequestBIU;
155
wire                             wGEO2_CU__RequestTCC;
156
wire                                                                            wGEO2_CU__GeometryUnitDone;
157
wire                                                                            wGEO2_CU__Sync;
158
wire                                                                            wEXE2__uCodeDone;
159
wire                                                                            wEXE2_IFU__EXEBusy;
160
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE2_IDU_DataFordward_LastDestination;
161
wire                                                                            wALU2_EXE__BranchTaken;
162
wire                                                                            wALU2_IFU_BranchNotTaken;
163
wire                                                                            w2IO__SetAddress;
164
wire                                                                            wIDU2_IFU__IDUBusy;
165
//Control Registe wires
166
wire[15:0]                                                               wCR2_ControlRegister;
167
wire                                                                            wCR2_TextureMappingEnabled;
168
wire                             wGEO2_CU__TFFDone;
169
wire                             wCU2_GEO__TriggerTFF;
170
wire                             wIO2_MEM_InstructionWriteEnable;
171
wire                             wCU2_IO__WritePixel;
172
wire                             wGEO2_IO__AddrIsImm;
173
wire[31:0]                       wGEO2_IO__AddressOffset;
174
wire                             wGEO2_IO__EnableWBMaster;
175
wire                             wGEO2_IO__SetAddress;
176
wire[`WIDTH-1:0]                 wGEO2__CurrentPitch,wCU2_GEO_Pitch;
177
wire                             wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
178 105 diegovalve
 
179
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteAddress;
180
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteData;
181
wire wEXE_2__IO_OMEMWriteEnable;
182
 
183
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_TMEMAddress;
184
wire [`DATA_ROW_WIDTH-1:0] wIO_2_EXE__TMEMData;
185
wire wIO_2_EXE__DataAvailable;
186
wire wEXE_2_IO__DataRequest;
187
 
188 76 diegovalve
wire wCU2_FlipMemEnabled;
189
wire w2MEM_FlipMemory;
190
 
191
`ifdef DEBUG
192
        wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
193
`endif
194
//--------------------------------------------------------
195
 
196
 
197
assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
198
wire wCU2_FlipMem;
199
//--------------------------------------------------------
200
//Control Unit Instance
201
        ControlUnit CU
202
        (
203
           .Clock(Clock),
204
                .Reset(Reset),
205
                .oFlipMemEnabled(                   wCU2_FlipMemEnabled            ),
206
                .oFlipMem(                          wCU2_FlipMem                   ),
207
                .iControlRegister(                  wCR2_ControlRegister           ),
208 117 diegovalve
                //.oRamBusOwner(                      RamBusOwner                    ),
209 76 diegovalve
                .oGFUEnable(                        wCU2_GEO__GeometryFetchEnable  ),
210
                .iTriggerAABBIURequest(             wGEO2_CU__RequestAABBIU        ),
211
                .iTriggerBIURequest(                wGEO2_CU__RequestBIU           ),
212
                .iTriggertTCCRequest(               wGEO2_CU__RequestTCC           ),
213
                .oUCodeEnable(                      wCU2__ExecuteMicroCode         ),
214
                .oCodeInstructioPointer(           InitialCodeAddress             ),
215
                .iUCodeDone(                        wCU2__MicrocodeExecutionDone   ),
216
                .iIODone(                           wIO2__Done                     ),
217
                .oIOWritePixel(                     wCU2_IO__WritePixel            ),
218
                .iUCodeReturnValue(                 wIFU2__MicroCodeReturnValue    ),
219
                .iGEOSync(                          wGEO2_CU__Sync                 ),
220
                .iTFFDone(                          wGEO2_CU__TFFDone              ),
221
                .oTriggerTFF(                       wCU2_GEO__TriggerTFF           ),
222
                .MST_I(                             MST_I                          ),
223
                .oSetCurrentPitch(                  wCU2_GEO__SetPitch             ),
224 105 diegovalve
                .iGFUDone(                          wGEO2_CU__GeometryUnitDone     ),
225 76 diegovalve
                .iRenderEnable(                     RENDREN_I                      ),
226 105 diegovalve
                .iSceneTraverseComplete(            STDONE_I                       ),
227
                .oResultCommited(                   RCOMMIT_O                      ),
228
                .iHostDataAvailable(                HDA_I                                                                        ),
229
 
230
 
231
                `ifdef DEBUG
232
                .iDebug_CoreID( iDebug_CoreID ),
233
                `endif
234 76 diegovalve
                .oDone(                             DONE_O                         )
235
 
236
        );
237
 
238
 
239
 
240
 
241
//--------------------------------------------------------      
242
 
243
//assign w2MEM_FlipMemory =  (wCU2__ExecuteMicroCode | wCU2_FlipMem ) & wCU2_FlipMemEnabled;
244
assign w2MEM_FlipMemory =  wCU2_FlipMem  & wCU2_FlipMemEnabled;
245
MemoryUnit MEM
246
(
247
.Clock(Clock),
248
.Reset(Reset),
249
 
250
.iFlipMemory( w2MEM_FlipMemory ),
251
 
252
//Data Bus to/from EXE
253
.iDataReadAddress1_EXE(       wEXE_2__MEM_DataReadAddress0        ),
254
.iDataReadAddress2_EXE(       wEXE_2__MEM_DataReadAddress1        ),
255
.oData1_EXE(                  wMEM_2__EXE_DataRead0               ),
256
.oData2_EXE(                  wMEM_2__EXE_DataRead1               ),
257
.iDataWriteEnable_EXE(        wEXE_2__DataWriteEnable          ),
258
.iDataWriteAddress_EXE(       wEXE_2__MEM_wDataWriteAddress        ),
259
.iData_EXE(                   wEXE_2__MEM_WriteData          ),
260
 
261
//Data Bus to/from IO
262
 
263
.iDataReadAddress1_IO(       wIO_2_MEM__DataReadAddress0        ),
264
.iDataReadAddress2_IO(       wIO_2_MEM__DataReadAddress1        ),
265
.oData1_IO(                  wMEM_2__IO_DataRead0               ),
266
.oData2_IO(                  wMEM_2__IO_DataRead1               ),
267
.iDataWriteEnable_IO(        wIO2_MEM__DataWriteEnable          ),
268
.iDataWriteAddress_IO(       wIO2_MEM__DataWriteAddress        ),
269 105 diegovalve
.iData_IO(                   wIO2_MEM__Bus          ),
270
 
271
`ifdef DEBUG
272
.iDebug_CoreID( iDebug_CoreID ),
273
`endif
274 76 diegovalve
 
275
 
276
//Instruction Bus
277
.iInstructionReadAddress1(  wInstructionPointer1             ),
278
.iInstructionReadAddress2(  wInstructionPointer2             ),
279
.oInstruction1(             wEncodedInstruction1             ),
280
.oInstruction2(             wEncodedInstruction2             ),
281
.iInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
282
.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr  ),
283
.iInstruction(             wIO2_MEM__ExternalInstruction   ),
284
.iControlRegister(         CREG_I                          ),
285
.oControlRegister(         wCR2_ControlRegister            )
286
 
287
);
288
 
289
////--------------------------------------------------------
290
 
291
 
292
ExecutionUnit EXE
293
(
294
 
295
.Clock( Clock),
296
.Reset( Reset ),
297
.iInitialCodeAddress(    InitialCodeAddress     ),
298
.iInstruction1(          wEncodedInstruction1      ),
299
.iInstruction2(          wEncodedInstruction2      ),
300
.oInstructionPointer1(   wInstructionPointer1    ),
301
.oInstructionPointer2(   wInstructionPointer2    ),
302
.iDataRead0(             wMEM_2__EXE_DataRead0             ),
303
.iDataRead1(             wMEM_2__EXE_DataRead1             ),
304
.iTrigger(               wCU2__ExecuteMicroCode ),
305
.oDataReadAddress0( wEXE_2__MEM_DataReadAddress0 ),
306
.oDataReadAddress1( wEXE_2__MEM_DataReadAddress1 ),
307
.oDataWriteEnable(  wEXE_2__DataWriteEnable  ),
308
.oDataWriteAddress( wEXE_2__MEM_wDataWriteAddress      ),
309
.oDataBus(          wEXE_2__MEM_WriteData          ),
310 105 diegovalve
.oReturnCode(       wIFU2__MicroCodeReturnValue ),
311
/**************/
312
.oOMEMWriteAddress(   wEXE_2__IO_WriteAddress ),
313
.oOMEMWriteData(      wEXE_2__IO_WriteData    ),
314
.oOMEMWriteEnable(  wEXE_2__IO_OMEMWriteEnable ),
315
 
316
.oTMEMReadAddress(   wEXE_2__IO_TMEMAddress   ),
317
.iTMEMReadData(      wIO_2_EXE__TMEMData      ),
318
.iTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
319
.oTMEMDataRequest(   wEXE_2_IO__DataRequest   ),
320
/**************/
321
`ifdef DEBUG
322
.iDebug_CoreID( iDebug_CoreID ),
323 76 diegovalve
`endif
324
.oDone(             wCU2__MicrocodeExecutionDone )
325
 
326
);
327
 
328
////--------------------------------------------------------
329
wire wGEO2__RequestingTextures;
330
wire w2IO_WriteBack_Set;
331
 
332
assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
333
//---------------------------------------------------------------------------------------------------
334
wire[`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress1;
335
assign wEXE_2__MEM_DataReadAddress1 = (wCU2_IO__WritePixel == 0) ?  wUCODE_RAMReadAddress1 : wIO_2_MEM__DataReadAddress1;
336
assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
337 105 diegovalve
assign w2IO__AddrIsImm       = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm       : 1'b0;
338
assign w2IO__AddressOffset   = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset   : 32'b0;
339
assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_ADDR_O;
340
//assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `CREG_PIXEL_2D_INITIAL_POSITION; 
341 76 diegovalve
 
342
wire w2IO_MasterCycleType;
343
assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
344
 
345 105 diegovalve
 
346
 
347
assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
348
 
349
 
350 76 diegovalve
IO_Unit IO
351
(
352
 .Clock(               Clock                            ),
353
 .Reset(               Reset                            ),
354 105 diegovalve
 .iEnable(           0 ),// w2IO__EnableWBMaster              ),
355 76 diegovalve
 .iBusCyc_Type(         w2IO_MasterCycleType            ),
356
 
357 105 diegovalve
 .iStore(              1),//w2IO__Store                      ),
358 76 diegovalve
 .iAdr_DataWriteBack(    w2IO__DataWriteAddress         ),
359
 .iAdr_O_Set(      w2IO__SetAddress                     ),
360
 .iAdr_O_Imm(       w2IO__AddressOffset                 ),
361
 .iAdr_O_Type(      w2IO__AddrIsImm                     ),
362 105 diegovalve
 .iAdr_O_Pointer(  w2IO__Adr_O_Pointer                  ),
363 76 diegovalve
 .iReadDataBus(        wMEM_2__IO_DataRead0                       ),
364 105 diegovalve
 .iReadDataBus2(        wMEM_2__IO_DataRead1                       ),
365
 .iDat_O_Pointer(     `OREG_PIXEL_COLOR                 ),
366 76 diegovalve
 
367 105 diegovalve
 
368 76 diegovalve
 .oDataReadAddress(    wIO_2_MEM__DataReadAddress0      ),
369
 .oDataReadAddress2(   wIO_2_MEM__DataReadAddress1       ),
370
 .oDataWriteAddress(   wIO2_MEM__DataWriteAddress    ),
371
 .oDataBus(               wIO2_MEM__Bus                 ),
372
 .oInstructionBus(     wIO2_MEM__ExternalInstruction    ),
373
 
374
 .oDataWriteEnable(         wIO2_MEM__DataWriteEnable    ),
375
 .oData(                    wIO2_MEM__Data                       ),
376
 .oInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
377
 .oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
378
 .iWriteBack_Set( w2IO_WriteBack_Set ),
379 82 diegovalve
 .oBusy(                      wIO_Busy                  ),
380 76 diegovalve
 .oDone(               wIO2__Done                       ),
381 105 diegovalve
 /**********/
382
 .iOMEM_WriteAddress(   wEXE_2__IO_WriteAddress         ),
383
 .iOMEM_WriteData(      wEXE_2__IO_WriteData            ),
384
 .iOMEM_WriteEnable(    wEXE_2__IO_OMEMWriteEnable    ),
385
 .OMEM_DAT_O( OMEM_DAT_O ),
386
 .OMEM_ADR_O( OMEM_ADR_O ),
387
 .OMEM_WE_O( OMEM_WE_O ),
388
 
389
 
390
 .oTMEMReadData(      wIO_2_EXE__TMEMData      ),
391
 .iTMEMDataRequest(   wEXE_2_IO__DataRequest   ),
392
 .iTMEMReadAddress(   wEXE_2__IO_TMEMAddress   ),
393
 .oTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
394
 
395
.TMEM_ACK_I( TMEM_ACK_I ),
396
.TMEM_DAT_I( TMEM_DAT_I ),
397
.TMEM_ADR_O( TMEM_ADR_O ),
398
.TMEM_WE_O(  TMEM_WE_O  ),
399
.TMEM_STB_O( TMEM_STB_O ),
400
.TMEM_CYC_O( TMEM_CYC_O ),
401
.TMEM_GNT_I( TMEM_GNT_I ),
402
 
403
 /**********/
404 76 diegovalve
 .MST_I( MST_I ),
405
  //Wish Bone Interface
406
.DAT_I( DAT_I ),
407
.DAT_O( DAT_O ),
408
.ACK_I( ACK_I & GNT_I ),
409
.ACK_O( ACK_O ),
410
.ADR_O( ADR_O ),
411
.ADR_I( ADR_I ),
412
.WE_O(  WE_O  ),
413
.WE_I(  WE_I  ),
414
.STB_O( STB_O ),
415
.STB_I( STB_I ),
416
.CYC_O( CYC_O ),
417
.TGA_I( TGA_I ),
418 105 diegovalve
.CYC_I( CYC_I ),
419 76 diegovalve
.GNT_I( GNT_I ),
420
.TGC_O( TGC_O )
421
 
422
 
423
);
424
//---------------------------------------------------------------------------------------------------
425
endmodule

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