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`ifndef COLLATERALS_V
`define COLLATERALS_V
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
 
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Enable,
        input wire [SIZE-1:0]    D,
        output reg [SIZE-1:0]    Q
);
 
 
always @ (posedge Clock)
begin
        if ( Reset )
                Q <= {SIZE{1'b0}};
        else
        begin
                if (Enable)
                        Q <= D;
        end
 
end//always
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
 
  always @(posedge Clock )
  begin
      if (Reset)
        Q <= Initial;
      else
                begin
                if (Enable)
                        Q <= Q + 1;
 
                end
  end
 
endmodule
 
//----------------------------------------------------------------------
 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
 (
 input wire [SEL_WIDTH-1:0] Sel,
 input wire  En,
 output wire [OUTPUT_WIDTH-1:0] O
 );
 
reg[OUTPUT_WIDTH-1:0] shift;
 
always @ ( * )
begin
        if (~En)
                shift = 1;
        else
                shift = (1 <<   Sel);
 
 
end
 
assign O = ( ~En ) ? 0 : shift ;
 
//assign O = En & (1 << Sel);
 
endmodule
 
//----------------------------------------------------------------------
 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 (
 input wire [1:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,I4,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                2'b11: O1 = I4;
                default: O1 = SIZE;
 
    endcase
 
  end
 
endmodule
 
//--------
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                begin
                        if (tmp[SIZE-1])
                        begin
                                tmp <= Initial;
                        end
                        else
                        begin
                                tmp <= tmp << 1;
                        end
                end
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
 (
 input wire [2:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      3'b001: O1 = I1;
      3'b010: O1 = I2;
      3'b100: O1 = I3;
      default: O1 = SIZE;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
//------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset || tmp[SIZE-1])
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//-----------------------------------------------------------
/*
        Sorry forgot how this flop is called.
        Any way Truth table is this
 
        Q       S       Q_next R
 
 
        1       0        1                0
        1       1       1                0
        X       X       0                 1
 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
        gets another S = 1, it keeps the output to 1.
*/
module FFToggleOnce_1Bit
(
        input wire Clock,
        input wire Reset,
        input wire Enable,
        input wire S,
        output reg Q
 
);
 
 
reg Q_next;
 
always @ (negedge Clock)
begin
        Q <= Q_next;
end
 
always @ ( posedge Clock )
begin
        if (Reset)
                Q_next <= 0;
        else if (Enable)
                Q_next <= (S && !Q) || Q;
        else
                Q_next <= Q;
end
endmodule
 
//-----------------------------------------------------------
 
 
module FFD32_POSEDGE
(
        input wire Clock,
        input wire[31:0] D,
        output reg[31:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_96bits_2SEL
 (
 input wire Sel,
 input wire [95:0]I1, I2,
 output reg [95:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
 (
 input wire Sel,
 input wire [15:0]I1, I2,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
//--------------------------------------------------------------
 
  module FFT1
  (
   input wire D,
   input wire Clock,
   input wire Reset ,
   output reg Q
 );
 
  always @ ( posedge Clock or posedge Reset )
  begin
 
        if (Reset)
        begin
    Q <= 1'b0;
   end
        else
        begin
                if (D)
                        Q <=  ! Q;
        end
 
  end//always
 
 endmodule
//--------------------------------------------------------------
 
`endif

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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Collaterals.v] - Blame information for rev 175

Line No.	Rev	Author	Line
1	174	diegovalve	`ifndef COLLATERALS_V
2			`define COLLATERALS_V
3
4	158	diegovalve	`timescale 1ns / 1ps
5			`include "aDefinitions.v"
6			`/**********************************************************************************`
7			`Theia, Ray Cast Programable graphic Processing Unit.`
8			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
9
10			`This program is free software; you can redistribute it and/or`
11			`modify it under the terms of the GNU General Public License`
12			`as published by the Free Software Foundation; either version 2`
13			`of the License, or (at your option) any later version.`
14
15			`This program is distributed in the hope that it will be useful,`
16			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`GNU General Public License for more details.`
19
20			`You should have received a copy of the GNU General Public License`
21			`along with this program; if not, write to the Free Software`
22			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
23
24			`***********************************************************************************/`
25	175	diegovalve
26	158	diegovalve	`//----------------------------------------------------`
27			module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
28			`(`
29			`input wire Clock,`
30			`input wire Reset,`
31			`input wire Enable,`
32			`input wire [SIZE-1:0] D,`
33			`output reg [SIZE-1:0] Q`
34			`);`
35
36
37			`always @ (posedge Clock)`
38			`begin`
39			`if ( Reset )`
40	175	diegovalve	`Q <= {SIZE{1'b0}};`
41	158	diegovalve	`else`
42			`begin`
43			`if (Enable)`
44			`Q <= D;`
45			`end`
46
47			`end//always`
48
49			`endmodule`
50			`//------------------------------------------------`
51			module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
52			`(`
53			`input wire Clock, Reset,`
54			`input wire [SIZE-1:0] Initial,`
55			`input wire Enable,`
56			`output reg [SIZE-1:0] Q`
57			`);`
58
59
60			`always @(posedge Clock )`
61			`begin`
62			`if (Reset)`
63			`Q <= Initial;`
64			`else`
65			`begin`
66			`if (Enable)`
67			`Q <= Q + 1;`
68
69			`end`
70			`end`
71
72			`endmodule`
73
74			`//----------------------------------------------------------------------`
75
76			`module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )`
77			`(`
78			`input wire [SEL_WIDTH-1:0] Sel,`
79			`input wire En,`
80			`output wire [OUTPUT_WIDTH-1:0] O`
81			`);`
82
83			`reg[OUTPUT_WIDTH-1:0] shift;`
84
85			`always @ ( * )`
86			`begin`
87			`if (~En)`
88			`shift = 1;`
89			`else`
90			`shift = (1 << Sel);`
91
92
93			`end`
94
95			`assign O = ( ~En ) ? 0 : shift ;`
96
97			`//assign O = En & (1 << Sel);`
98
99			`endmodule`
100
101			`//----------------------------------------------------------------------`
102
103			module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
104			`(`
105			`input wire [1:0] Sel,`
106			`input wire [SIZE-1:0]I1, I2, I3,I4,`
107			`output reg [SIZE-1:0] O1`
108			`);`
109
110			`always @( * )`
111
112			`begin`
113
114			`case (Sel)`
115
116			`2'b00: O1 = I1;`
117			`2'b01: O1 = I2;`
118			`2'b10: O1 = I3;`
119			`2'b11: O1 = I4;`
120	175	diegovalve	`default: O1 = SIZE;`
121	158	diegovalve
122			`endcase`
123
124			`end`
125
126			`endmodule`
127
128			`//--------`
129			module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
130			`( input wire Clock,`
131			`input wire Reset,`
132			`input wire[SIZE-1:0] Initial,`
133			`input wire Enable,`
134			`output wire[SIZE-1:0] O`
135			`);`
136
137			`reg [SIZE-1:0] tmp;`
138
139
140			`always @(posedge Clock)`
141			`begin`
142			`if (Reset)`
143			`tmp <= Initial;`
144			`else`
145			`begin`
146			`if (Enable)`
147			`begin`
148			`if (tmp[SIZE-1])`
149			`begin`
150			`tmp <= Initial;`
151			`end`
152			`else`
153			`begin`
154			`tmp <= tmp << 1;`
155			`end`
156			`end`
157			`end`
158			`end`
159
160
161			`assign O = tmp;`
162			`endmodule`
163			`//------------------------------------------------`
164			module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
165			`(`
166			`input wire [2:0] Sel,`
167			`input wire [SIZE-1:0]I1, I2, I3,`
168			`output reg [SIZE-1:0] O1`
169			`);`
170
171			`always @( * )`
172
173			`begin`
174
175			`case (Sel)`
176
177			`3'b001: O1 = I1;`
178			`3'b010: O1 = I2;`
179	175	diegovalve	`3'b100: O1 = I3;`
180			`default: O1 = SIZE;`
181	158	diegovalve
182			`endcase`
183
184			`end`
185
186			`endmodule`
187			`//------------------------------------------------`
188			module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
189			`( input wire Clock,`
190			`input wire Reset,`
191			`input wire[SIZE-1:0] Initial,`
192			`input wire Enable,`
193			`output wire[SIZE-1:0] O`
194			`);`
195
196			`reg [SIZE-1:0] tmp;`
197
198
199			`always @(posedge Clock)`
200			`begin`
201			`if (Reset)`
202			`tmp <= Initial;`
203			`else`
204			`begin`
205			`if (Enable)`
206			`tmp <= tmp << 1;`
207			`end`
208			`end`
209
210
211			`assign O = tmp;`
212			`endmodule`
213			`//------------------------------------------------`
214			`//------------------------------------------------`
215			module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
216			`( input wire Clock,`
217			`input wire Reset,`
218			`input wire[SIZE-1:0] Initial,`
219			`input wire Enable,`
220			`output wire[SIZE-1:0] O`
221			`);`
222
223			`reg [SIZE-1:0] tmp;`
224
225
226			`always @(posedge Clock)`
227			`begin`
228			`if (Reset \|\| tmp[SIZE-1])`
229			`tmp <= Initial;`
230			`else`
231			`begin`
232			`if (Enable)`
233			`tmp <= tmp << 1;`
234			`end`
235			`end`
236
237
238			`assign O = tmp;`
239			`endmodule`
240			`//-----------------------------------------------------------`
241			`/*`
242			`Sorry forgot how this flop is called.`
243			`Any way Truth table is this`
244
245			`Q S Q_next R`
246
247
248			`1 0 1 0`
249			`1 1 1 0`
250			`X X 0 1`
251
252			`The idea is that it toggles from 0 to 1 when S = 1, but if it`
253			`gets another S = 1, it keeps the output to 1.`
254			`*/`
255			`module FFToggleOnce_1Bit`
256			`(`
257			`input wire Clock,`
258			`input wire Reset,`
259			`input wire Enable,`
260			`input wire S,`
261			`output reg Q`
262
263			`);`
264
265
266			`reg Q_next;`
267
268			`always @ (negedge Clock)`
269			`begin`
270			`Q <= Q_next;`
271			`end`
272
273			`always @ ( posedge Clock )`
274			`begin`
275			`if (Reset)`
276			`Q_next <= 0;`
277			`else if (Enable)`
278			`Q_next <= (S && !Q) \|\| Q;`
279			`else`
280			`Q_next <= Q;`
281			`end`
282			`endmodule`
283
284			`//-----------------------------------------------------------`
285
286
287			`module FFD32_POSEDGE`
288			`(`
289			`input wire Clock,`
290			`input wire[31:0] D,`
291			`output reg[31:0] Q`
292			`);`
293
294			`always @ (posedge Clock)`
295			`Q <= D;`
296
297			`endmodule`
298
299			`//------------------------------------------------`
300			`module MUXFULLPARALELL_96bits_2SEL`
301			`(`
302			`input wire Sel,`
303			`input wire [95:0]I1, I2,`
304			`output reg [95:0] O1`
305			`);`
306
307
308
309			`always @( * )`
310
311			`begin`
312
313			`case (Sel)`
314
315			`1'b0: O1 = I1;`
316			`1'b1: O1 = I2;`
317
318			`endcase`
319
320			`end`
321
322			`endmodule`
323
324			`//------------------------------------------------`
325			`module MUXFULLPARALELL_16bits_2SEL`
326			`(`
327			`input wire Sel,`
328			`input wire [15:0]I1, I2,`
329			`output reg [15:0] O1`
330			`);`
331
332
333
334			`always @( * )`
335
336			`begin`
337
338			`case (Sel)`
339
340			`1'b0: O1 = I1;`
341			`1'b1: O1 = I2;`
342
343			`endcase`
344
345			`end`
346
347			`endmodule`
348
349			`//--------------------------------------------------------------`
350
351			`module FFT1`
352			`(`
353			`input wire D,`
354			`input wire Clock,`
355			`input wire Reset ,`
356			`output reg Q`
357			`);`
358
359			`always @ ( posedge Clock or posedge Reset )`
360			`begin`
361
362			`if (Reset)`
363			`begin`
364			`Q <= 1'b0;`
365			`end`
366			`else`
367			`begin`
368			`if (D)`
369			`Q <= ! Q;`
370			`end`
371
372			`end//always`
373
374			`endmodule`
375			`//--------------------------------------------------------------`
376	174	diegovalve
377			`endif