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`ifndef COLLATERALS_V
`define COLLATERALS_V
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
 
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Enable,
        input wire [SIZE-1:0]    D,
        output reg [SIZE-1:0]    Q
);
 
 
always @ (posedge Clock)
begin
        if ( Reset )
                Q <= {SIZE{1'b0}};
        else
        begin
                if (Enable)
                        Q <= D;
        end
 
end//always
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
 
  always @(posedge Clock )
  begin
      if (Reset)
        Q <= Initial;
      else
                begin
                if (Enable)
                        Q <= Q + 1;
 
                end
  end
 
endmodule
 
//----------------------------------------------------------------------
 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
 (
 input wire [SEL_WIDTH-1:0] Sel,
 input wire  En,
 output wire [OUTPUT_WIDTH-1:0] O
 );
 
reg[OUTPUT_WIDTH-1:0] shift;
 
always @ ( * )
begin
        if (~En)
                shift = 1;
        else
                shift = (1 <<   Sel);
 
 
end
 
assign O = ( ~En ) ? 0 : shift ;
 
//assign O = En & (1 << Sel);
 
endmodule
 
//----------------------------------------------------------------------
module MUXFULLPARALELL_GENERIC #(parameter  WIDTH = `WIDTH, parameter  CHANNELS = 4, parameter SELBITS = 2)
(
 
    input wire   [(CHANNELS*WIDTH)-1:0]      in_bus,
    input wire   [SELBITS-1:0]    sel,
 
    output wire [WIDTH-1:0]                 out
    );
 
genvar ig;
 
wire    [WIDTH-1:0] input_array [0:CHANNELS-1];
 
assign  out = input_array[sel];
 
generate
    for(ig=0; ig<CHANNELS; ig=ig+1)
         begin: array_assignments
        assign  input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
    end
endgenerate
 
 
 
endmodule
//----------------------------------------------------------------------
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 (
 input wire [1:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,I4,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                2'b11: O1 = I4;
                default: O1 = SIZE;
 
    endcase
 
  end
 
endmodule
 
//--------
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                begin
                        if (tmp[SIZE-1])
                        begin
                                tmp <= Initial;
                        end
                        else
                        begin
                                tmp <= tmp << 1;
                        end
                end
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
 (
 input wire [2:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      3'b001: O1 = I1;
      3'b010: O1 = I2;
      3'b100: O1 = I3;
      default: O1 = SIZE;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
//------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset || tmp[SIZE-1])
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//-----------------------------------------------------------
/*
        Sorry forgot how this flop is called.
        Any way Truth table is this
 
        Q       S       Q_next R
 
 
        1       0        1                0
        1       1       1                0
        X       X       0                 1
 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
        gets another S = 1, it keeps the output to 1.
*/
module FFToggleOnce_1Bit
(
        input wire Clock,
        input wire Reset,
        input wire Enable,
        input wire S,
        output reg Q
 
);
 
 
reg Q_next;
 
always @ (negedge Clock)
begin
        Q <= Q_next;
end
 
always @ ( posedge Clock )
begin
        if (Reset)
                Q_next <= 0;
        else if (Enable)
                Q_next <= (S && !Q) || Q;
        else
                Q_next <= Q;
end
endmodule
 
//-----------------------------------------------------------
 
 
module FFD32_POSEDGE
(
        input wire Clock,
        input wire[31:0] D,
        output reg[31:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_96bits_2SEL
 (
 input wire Sel,
 input wire [95:0]I1, I2,
 output reg [95:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
 (
 input wire Sel,
 input wire [15:0]I1, I2,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
//--------------------------------------------------------------
 
  module FFT1
  (
   input wire D,
   input wire Clock,
   input wire Reset ,
   output reg Q
 );
 
  always @ ( posedge Clock or posedge Reset )
  begin
 
        if (Reset)
        begin
    Q <= 1'b0;
   end
        else
        begin
                if (D)
                        Q <=  ! Q;
        end
 
  end//always
 
 endmodule
//--------------------------------------------------------------
 
`endif

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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Collaterals.v] - Blame information for rev 228

Line No.	Rev	Author	Line
1	174	diegovalve	`ifndef COLLATERALS_V
2			`define COLLATERALS_V
3
4	158	diegovalve	`timescale 1ns / 1ps
5			`include "aDefinitions.v"
6			`/**********************************************************************************`
7			`Theia, Ray Cast Programable graphic Processing Unit.`
8			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
9
10			`This program is free software; you can redistribute it and/or`
11			`modify it under the terms of the GNU General Public License`
12			`as published by the Free Software Foundation; either version 2`
13			`of the License, or (at your option) any later version.`
14
15			`This program is distributed in the hope that it will be useful,`
16			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`GNU General Public License for more details.`
19
20			`You should have received a copy of the GNU General Public License`
21			`along with this program; if not, write to the Free Software`
22			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
23
24			`***********************************************************************************/`
25	175	diegovalve
26	158	diegovalve	`//----------------------------------------------------`
27			module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
28			`(`
29			`input wire Clock,`
30			`input wire Reset,`
31			`input wire Enable,`
32			`input wire [SIZE-1:0] D,`
33			`output reg [SIZE-1:0] Q`
34			`);`
35
36
37			`always @ (posedge Clock)`
38			`begin`
39			`if ( Reset )`
40	175	diegovalve	`Q <= {SIZE{1'b0}};`
41	158	diegovalve	`else`
42			`begin`
43			`if (Enable)`
44			`Q <= D;`
45			`end`
46
47			`end//always`
48
49			`endmodule`
50			`//------------------------------------------------`
51			module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
52			`(`
53			`input wire Clock, Reset,`
54			`input wire [SIZE-1:0] Initial,`
55			`input wire Enable,`
56			`output reg [SIZE-1:0] Q`
57			`);`
58
59
60			`always @(posedge Clock )`
61			`begin`
62			`if (Reset)`
63			`Q <= Initial;`
64			`else`
65			`begin`
66			`if (Enable)`
67			`Q <= Q + 1;`
68
69			`end`
70			`end`
71
72			`endmodule`
73
74			`//----------------------------------------------------------------------`
75
76			`module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )`
77			`(`
78			`input wire [SEL_WIDTH-1:0] Sel,`
79			`input wire En,`
80			`output wire [OUTPUT_WIDTH-1:0] O`
81			`);`
82
83			`reg[OUTPUT_WIDTH-1:0] shift;`
84
85			`always @ ( * )`
86			`begin`
87			`if (~En)`
88			`shift = 1;`
89			`else`
90			`shift = (1 << Sel);`
91
92
93			`end`
94
95			`assign O = ( ~En ) ? 0 : shift ;`
96
97			`//assign O = En & (1 << Sel);`
98
99			`endmodule`
100
101	176	diegovalve	`//----------------------------------------------------------------------`
102			module MUXFULLPARALELL_GENERIC #(parameter WIDTH = `WIDTH, parameter CHANNELS = 4, parameter SELBITS = 2)
103			`(`
104
105			`input wire [(CHANNELS*WIDTH)-1:0] in_bus,`
106			`input wire [SELBITS-1:0] sel,`
107
108			`output wire [WIDTH-1:0] out`
109			`);`
110
111			`genvar ig;`
112
113			`wire [WIDTH-1:0] input_array [0:CHANNELS-1];`
114
115			`assign out = input_array[sel];`
116
117			`generate`
118			`for(ig=0; ig<CHANNELS; ig=ig+1)`
119			`begin: array_assignments`
120			`assign input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];`
121			`end`
122			`endgenerate`
123
124
125
126			`endmodule`
127	158	diegovalve	`//----------------------------------------------------------------------`
128			module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
129			`(`
130			`input wire [1:0] Sel,`
131			`input wire [SIZE-1:0]I1, I2, I3,I4,`
132			`output reg [SIZE-1:0] O1`
133			`);`
134
135			`always @( * )`
136
137			`begin`
138
139			`case (Sel)`
140
141			`2'b00: O1 = I1;`
142			`2'b01: O1 = I2;`
143			`2'b10: O1 = I3;`
144			`2'b11: O1 = I4;`
145	175	diegovalve	`default: O1 = SIZE;`
146	158	diegovalve
147			`endcase`
148
149			`end`
150
151			`endmodule`
152
153			`//--------`
154			module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
155			`( input wire Clock,`
156			`input wire Reset,`
157			`input wire[SIZE-1:0] Initial,`
158			`input wire Enable,`
159			`output wire[SIZE-1:0] O`
160			`);`
161
162			`reg [SIZE-1:0] tmp;`
163
164
165			`always @(posedge Clock)`
166			`begin`
167			`if (Reset)`
168			`tmp <= Initial;`
169			`else`
170			`begin`
171			`if (Enable)`
172			`begin`
173			`if (tmp[SIZE-1])`
174			`begin`
175			`tmp <= Initial;`
176			`end`
177			`else`
178			`begin`
179			`tmp <= tmp << 1;`
180			`end`
181			`end`
182			`end`
183			`end`
184
185
186			`assign O = tmp;`
187			`endmodule`
188			`//------------------------------------------------`
189			module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
190			`(`
191			`input wire [2:0] Sel,`
192			`input wire [SIZE-1:0]I1, I2, I3,`
193			`output reg [SIZE-1:0] O1`
194			`);`
195
196			`always @( * )`
197
198			`begin`
199
200			`case (Sel)`
201
202			`3'b001: O1 = I1;`
203			`3'b010: O1 = I2;`
204	175	diegovalve	`3'b100: O1 = I3;`
205			`default: O1 = SIZE;`
206	158	diegovalve
207			`endcase`
208
209			`end`
210
211			`endmodule`
212			`//------------------------------------------------`
213			module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
214			`( input wire Clock,`
215			`input wire Reset,`
216			`input wire[SIZE-1:0] Initial,`
217			`input wire Enable,`
218			`output wire[SIZE-1:0] O`
219			`);`
220
221			`reg [SIZE-1:0] tmp;`
222
223
224			`always @(posedge Clock)`
225			`begin`
226			`if (Reset)`
227			`tmp <= Initial;`
228			`else`
229			`begin`
230			`if (Enable)`
231			`tmp <= tmp << 1;`
232			`end`
233			`end`
234
235
236			`assign O = tmp;`
237			`endmodule`
238			`//------------------------------------------------`
239			`//------------------------------------------------`
240			module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
241			`( input wire Clock,`
242			`input wire Reset,`
243			`input wire[SIZE-1:0] Initial,`
244			`input wire Enable,`
245			`output wire[SIZE-1:0] O`
246			`);`
247
248			`reg [SIZE-1:0] tmp;`
249
250
251			`always @(posedge Clock)`
252			`begin`
253			`if (Reset \|\| tmp[SIZE-1])`
254			`tmp <= Initial;`
255			`else`
256			`begin`
257			`if (Enable)`
258			`tmp <= tmp << 1;`
259			`end`
260			`end`
261
262
263			`assign O = tmp;`
264			`endmodule`
265			`//-----------------------------------------------------------`
266			`/*`
267			`Sorry forgot how this flop is called.`
268			`Any way Truth table is this`
269
270			`Q S Q_next R`
271
272
273			`1 0 1 0`
274			`1 1 1 0`
275			`X X 0 1`
276
277			`The idea is that it toggles from 0 to 1 when S = 1, but if it`
278			`gets another S = 1, it keeps the output to 1.`
279			`*/`
280			`module FFToggleOnce_1Bit`
281			`(`
282			`input wire Clock,`
283			`input wire Reset,`
284			`input wire Enable,`
285			`input wire S,`
286			`output reg Q`
287
288			`);`
289
290
291			`reg Q_next;`
292
293			`always @ (negedge Clock)`
294			`begin`
295			`Q <= Q_next;`
296			`end`
297
298			`always @ ( posedge Clock )`
299			`begin`
300			`if (Reset)`
301			`Q_next <= 0;`
302			`else if (Enable)`
303			`Q_next <= (S && !Q) \|\| Q;`
304			`else`
305			`Q_next <= Q;`
306			`end`
307			`endmodule`
308
309			`//-----------------------------------------------------------`
310
311
312			`module FFD32_POSEDGE`
313			`(`
314			`input wire Clock,`
315			`input wire[31:0] D,`
316			`output reg[31:0] Q`
317			`);`
318
319			`always @ (posedge Clock)`
320			`Q <= D;`
321
322			`endmodule`
323
324			`//------------------------------------------------`
325			`module MUXFULLPARALELL_96bits_2SEL`
326			`(`
327			`input wire Sel,`
328			`input wire [95:0]I1, I2,`
329			`output reg [95:0] O1`
330			`);`
331
332
333
334			`always @( * )`
335
336			`begin`
337
338			`case (Sel)`
339
340			`1'b0: O1 = I1;`
341			`1'b1: O1 = I2;`
342
343			`endcase`
344
345			`end`
346
347			`endmodule`
348
349			`//------------------------------------------------`
350			`module MUXFULLPARALELL_16bits_2SEL`
351			`(`
352			`input wire Sel,`
353			`input wire [15:0]I1, I2,`
354			`output reg [15:0] O1`
355			`);`
356
357
358
359			`always @( * )`
360
361			`begin`
362
363			`case (Sel)`
364
365			`1'b0: O1 = I1;`
366			`1'b1: O1 = I2;`
367
368			`endcase`
369
370			`end`
371
372			`endmodule`
373
374			`//--------------------------------------------------------------`
375
376			`module FFT1`
377			`(`
378			`input wire D,`
379			`input wire Clock,`
380			`input wire Reset ,`
381			`output reg Q`
382			`);`
383
384			`always @ ( posedge Clock or posedge Reset )`
385			`begin`
386
387			`if (Reset)`
388			`begin`
389			`Q <= 1'b0;`
390			`end`
391			`else`
392			`begin`
393			`if (D)`
394			`Q <= ! Q;`
395			`end`
396
397			`end//always`
398
399			`endmodule`
400			`//--------------------------------------------------------------`
401	174	diegovalve
402			`endif