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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_ExecutionFSM.v] - Blame information for rev 166

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET                                                        0
`define EXEU_INITIAL_STATE                                              1
`define EXEU_WAIT_FOR_DECODE                                            2
`define EXEU_FETCH_DECODED_INST                                 3
`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
`define EXEU_WRITE_BACK_TO_RAM                                  5
`define EXEU_HANDLE_JUMP                                                        7
 
 
 
module ExecutionFSM
(
input wire                                                              Clock,
input wire                                                              Reset,
 
input   wire                                                                            iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
//output        reg                                                                     ReadyForNextInstruction,
output wire                                                                     oJumpFlag                       ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
output  wire                                                                    oRAMWriteEnable         ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
output  wire                                                                    oExeLatchedValues,
output  reg                                                                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
output  wire                                                                                                    oTriggerALU,
 
input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
input wire                                                                                                              iALUOutputReady,
input   wire                                                                                                            iBranchTaken,
input wire                                                                                                              iBranchNotTaken,
 
 
`ifdef DEBUG
        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
        input wire [`MAX_CORES-1:0]         iDebug_CoreID,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
assign oALUChannelX1 = iSource1[95:64];
assign oALUChannelY1 = iSource1[63:32];
assign oALUChannelZ1 = iSource1[31:0];
 
assign oALUChannelX2 = iSource0[95:64];
assign oALUChannelY2 = iSource0[63:32];
assign oALUChannelZ2 = iSource0[31:0];
 
assign oALUOperation = iOperation;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iDestination ),
        .Q(oRAMWriteAddress)
);
 
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
                CurrentState <= `EXEU_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
                  //------------------------------------------
                  `EXEU_AFTER_RESET:
                  begin
                                //ReadyForNextInstruction = 1;
                                oBusy                                                   = 0;
                                rInputLatchesEnabled            =       1;
 
 
                                NextState       = `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /**
                        At the same time iDecodeDone goes to 1, our Flops
                        will store the value, so next clock cycle we can
                        tell IDU to go ahead and decode the next instruction
                        in the pipeline.
                  */
                  `EXEU_WAIT_FOR_DECODE:
                  begin
 
 
                                //ReadyForNextInstruction = 1;
                                oBusy                                                   = 0;
                                rInputLatchesEnabled            =       1;
 
 
                        if ( iDecodeDone )      //This same thing triggers the ALU
                                NextState       = `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState       = `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /*
                  If the instruction is aritmetic then pass the parameters
                  the ALU, else if it store iOperation then...
                  */
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
                  begin
 
                                //ReadyForNextInstruction = 0;                                          //*
                                oBusy                                                   = 1;
                                rInputLatchesEnabled            =       0;               //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
                                        NextState = `EXEU_WAIT_FOR_DECODE;
                                else
                                        NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
                  end
                  //------------------------------------------
                  `EXEU_WRITE_BACK_TO_RAM:
                  begin
 
                                //ReadyForNextInstruction = 0;                                          
                                oBusy                                                   = 1;
                                rInputLatchesEnabled            =       1;
 
                        if ( iDecodeDone )
                                NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState = `EXEU_WAIT_FOR_DECODE;
 
                  end
 
                  //------------------------------------------
                  default:
                  begin
 
                                //ReadyForNextInstruction = 1;
                                oBusy                                                   = 0;
                                rInputLatchesEnabled            =       1;
 
                                NextState = `EXEU_AFTER_RESET;
                  end
                  //------------------------------------------
        endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
        $display("Opening ucode dump file....\n");
        ucode_file = $fopen("Code.log","w");
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
        $display("Opening Register lof file...\n");
        reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[95:64] ),
        .Q(wALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[63:32] ),
        .Q(wALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[31:0] ),
        .Q(wALUChannelZ1)
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[95:64] ),
        .Q(wALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[63:32] ),
        .Q(wALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[31:0] ),
        .Q(wALUChannelZ2)
);
 
 
        always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
        begin
                `LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
        end
 
        always @ (negedge  Clock && iDebug_CoreID == `DEBUG_CORE)
        begin
        if ( iALUOutputReady )
        begin
 
 
                if (iBranchTaken)
                        `LOGME"<BT>");
 
                if (iBranchNotTaken     )
                        `LOGME"<BNT>");
 
                if (oRAMWriteEnable)
                        `LOGME"<WE>");
 
                `LOGME "(%dns ",$time);
                                        case ( oALUOperation )
                                        `RETURN: `LOGME"RETURN");
                                        `ADD:   `LOGME"ADD");
                                        `SUB:           `LOGME"SUB");
                                        `DIV:           `LOGME"DIV");
                                        `MUL:   `LOGME"MUL");
                                        `MAG:           `LOGME"MAG");
                                        `JGX:           `LOGME"JGX");
                                        `JLX:           `LOGME"JLX");
                                        `JGEX:  `LOGME"JGEX");
                                        `JGEY:  `LOGME"JGEY");
                                        `JGEZ:  `LOGME"JGEZ");
                                        `JLEX:  `LOGME"JLEX");
                                        `JLEY:  `LOGME"JLEY");
                                        `JLEZ:  `LOGME"JLEZ");
                                        `JMP:           `LOGME"JMP");
                                        `ZERO:  `LOGME"ZERO");
                                        `JNEX:  `LOGME"JNEX");
                                        `JNEY:  `LOGME"JNEY");
                                        `JNEZ:  `LOGME"JNEZ");
                                        `JEQX:  `LOGME"JEQX");
                                        `JEQY:  `LOGME"JEQY");
                                        `JEQZ:  `LOGME"JEQZ");
                                        `CROSS: `LOGME"CROSS");
                                        `DOT:           `LOGME"DOT");
                                        `SETX:  `LOGME"SETX");
                                        `SETY:  `LOGME"SETY");
                                        `SETZ:  `LOGME"SETZ");
                                        `NOP:   `LOGME"NOP");
                                        `COPY:  `LOGME"COPY");
                                        `INC:           `LOGME"INC");
                                        `DEC:           `LOGME"DEC");
                                        `MOD:           `LOGME"MOD");
                                        `FRAC:  `LOGME"FRAC");
                                        `NEG:    `LOGME"NEG");
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
                                        `MULP:          `LOGME"MULP");
                                        `XCHANGEX:      `LOGME"XCHANGEX");
                                        `IMUL:      `LOGME"IMUL");
                                        `UNSCALE:      `LOGME"UNSCALE");
                                        `INCX: `LOGME"INCX");
                                        `INCY: `LOGME"INCY");
                                        `INCZ: `LOGME"INCZ");
                                        `OMWRITE: `LOGME"OMWRITE");
                                        `TMREAD: `LOGME"TMREAD");
                                        `LEA:     `LOGME"LEA");
                                        `CALL:    `LOGME"CALL");
                                        `RET:     `LOGME"RET");
                                        `DEBUG_PRINT:
                                        begin
                                                `LOGME"DEBUG_PRINT");
 
                                        end
                                        default:
                                        begin
                                                `LOGME"**********ERROR UNKNOWN OP*********");
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
                                        //      $stop();
                                        end
                                        endcase
 
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
                                        oRAMWriteAddress,
                                        wALUChannelX1,wALUChannelY1,wALUChannelZ1,
                                        wALUChannelX2,wALUChannelY2,wALUChannelZ2
 
                                        );
 
                                        if (oALUOperation == `RETURN)
                                                `LOGME"\n\n\n");
 
                end
        end //always
 
        always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
        begin
        if ( iALUOutputReady )
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
        end //always
`endif
 
endmodule

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Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_ExecutionFSM.v] - Blame information for rev 166

Line No.	Rev	Author	Line
1	158	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define EXEU_AFTER_RESET 0
23			`define EXEU_INITIAL_STATE 1
24			`define EXEU_WAIT_FOR_DECODE 2
25			`define EXEU_FETCH_DECODED_INST 3
26			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
27			`define EXEU_WRITE_BACK_TO_RAM 5
28			`define EXEU_HANDLE_JUMP 7
29
30
31
32			`module ExecutionFSM`
33			`(`
34			`input wire Clock,`
35			`input wire Reset,`
36
37			`input wire iDecodeDone,`
38			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
39			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
40			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
41			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
42			`//output reg ReadyForNextInstruction,`
43			`output wire oJumpFlag ,`
44			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
45			`output wire oRAMWriteEnable ,`
46			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
47			`output wire oExeLatchedValues,`
48			`output reg oBusy ,`
49
50			`//ALU ports and control signals`
51			output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
52			output wire [`WIDTH-1:0] oALUChannelX1,
53			output wire [`WIDTH-1:0] oALUChannelY1,
54			output wire [`WIDTH-1:0] oALUChannelZ1,
55			output wire [`WIDTH-1:0] oALUChannelX2,
56			output wire [`WIDTH-1:0] oALUChannelY2,
57			output wire [`WIDTH-1:0] oALUChannelZ2,
58			`output wire oTriggerALU,`
59
60			input wire [`WIDTH-1:0] iALUResultX,
61			input wire [`WIDTH-1:0] iALUResultY,
62			input wire [`WIDTH-1:0] iALUResultZ,
63			`input wire iALUOutputReady,`
64			`input wire iBranchTaken,`
65			`input wire iBranchNotTaken,`
66
67
68			`ifdef DEBUG
69			input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
70			input wire [`MAX_CORES-1:0] iDebug_CoreID,
71			`endif
72			`//Data forward Signals`
73			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
74
75
76			`);`
77
78			`wire wLatchNow;`
79			`reg rInputLatchesEnabled;`
80
81			`//If ALU says jump, just pass along`
82			`assign oJumpFlag = iBranchTaken;`
83			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
84			`assign oJumpIp = oRAMWriteAddress;`
85
86			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
87			`assign oExeLatchedValues = wLatchNow;`
88			`assign oTriggerALU = wLatchNow;`
89
90			`wire wOperationIsJump;`
91			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
92
93			`//Don't allow me to write back back if the operation is a NOP`
94			`ifdef DEBUG
95			`assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&`
96			(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
97			`else
98			assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
99			`endif
100
101
102			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
103
104			`assign oALUChannelX1 = iSource1[95:64];`
105			`assign oALUChannelY1 = iSource1[63:32];`
106			`assign oALUChannelZ1 = iSource1[31:0];`
107
108			`assign oALUChannelX2 = iSource0[95:64];`
109			`assign oALUChannelY2 = iSource0[63:32];`
110			`assign oALUChannelZ2 = iSource0[31:0];`
111
112			`assign oALUOperation = iOperation;`
113
114			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
115			`(`
116			`.Clock( Clock ),//wLatchNow ),`
117			`.Reset( Reset),`
118			`.Enable( wLatchNow ),//1'b1 ),`
119			`.D( iDestination ),`
120			`.Q(oRAMWriteAddress)`
121			`);`
122
123			`//Data forwarding`
124			`assign oLastDestination = oRAMWriteAddress;`
125
126			`reg [7:0] CurrentState;`
127			`reg [7:0] NextState;`
128
129
130			`//------------------------------------------------`
131			`always @(posedge Clock or posedge Reset)`
132			`begin`
133
134
135
136			`if (Reset)`
137			CurrentState <= `EXEU_AFTER_RESET;
138			`else`
139			`CurrentState <= NextState;`
140
141			`end`
142			`//------------------------------------------------`
143
144
145			`always @( * )`
146			`begin`
147			`case (CurrentState)`
148			`//------------------------------------------`
149			`EXEU_AFTER_RESET:
150			`begin`
151			`//ReadyForNextInstruction = 1;`
152			`oBusy = 0;`
153			`rInputLatchesEnabled = 1;`
154
155
156			NextState = `EXEU_WAIT_FOR_DECODE;
157			`end`
158			`//------------------------------------------`
159			`/**`
160			`At the same time iDecodeDone goes to 1, our Flops`
161			`will store the value, so next clock cycle we can`
162			`tell IDU to go ahead and decode the next instruction`
163			`in the pipeline.`
164			`*/`
165			`EXEU_WAIT_FOR_DECODE:
166			`begin`
167
168
169			`//ReadyForNextInstruction = 1;`
170			`oBusy = 0;`
171			`rInputLatchesEnabled = 1;`
172
173
174			`if ( iDecodeDone ) //This same thing triggers the ALU`
175			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
176			`else`
177			NextState = `EXEU_WAIT_FOR_DECODE;
178			`end`
179			`//------------------------------------------`
180			`/*`
181			`If the instruction is aritmetic then pass the parameters`
182			`the ALU, else if it store iOperation then...`
183			`*/`
184			`EXEU_WAIT_FOR_ALU_EXECUTION:
185			`begin`
186
187			`//ReadyForNextInstruction = 0; //*`
188			`oBusy = 1;`
189			`rInputLatchesEnabled = 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
190
191
192
193			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
194			NextState = `EXEU_WAIT_FOR_DECODE;
195			`else`
196			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
197			`end`
198			`//------------------------------------------`
199			`EXEU_WRITE_BACK_TO_RAM:
200			`begin`
201
202			`//ReadyForNextInstruction = 0;`
203			`oBusy = 1;`
204			`rInputLatchesEnabled = 1;`
205
206			`if ( iDecodeDone )`
207			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
208			`else`
209			NextState = `EXEU_WAIT_FOR_DECODE;
210
211			`end`
212
213			`//------------------------------------------`
214			`default:`
215			`begin`
216
217			`//ReadyForNextInstruction = 1;`
218			`oBusy = 0;`
219			`rInputLatchesEnabled = 1;`
220
221			NextState = `EXEU_AFTER_RESET;
222			`end`
223			`//------------------------------------------`
224			`endcase`
225			`end`
226
227			`//-----------------------------------------------------------------------`
228			`ifdef DUMP_CODE
229			`integer ucode_file;`
230			`integer reg_log;`
231			`initial`
232			`begin`
233
234			`$display("Opening ucode dump file....\n");`
235			`ucode_file = $fopen("Code.log","w");`
236			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
237			`$display("Opening Register lof file...\n");`
238			`reg_log = $fopen("Registers.log","w");`
239
240			`end`
241
242			`endif //Ucode dump
243
244			`//-----------------------------------------------------------------------`
245			`ifdef DEBUG
246			wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
247			wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
248
249			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
250			`(`
251			`.Clock( Clock ),`
252			`.Reset( Reset),`
253			`.Enable( wLatchNow ),`
254			`.D( iSource1[95:64] ),`
255			`.Q(wALUChannelX1)`
256			`);`
257			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
258			`(`
259			`.Clock( Clock ),`
260			`.Reset( Reset),`
261			`.Enable( wLatchNow ),`
262			`.D( iSource1[63:32] ),`
263			`.Q(wALUChannelY1)`
264			`);`
265			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
266			`(`
267			`.Clock( Clock ),`
268			`.Reset( Reset),`
269			`.Enable( wLatchNow ),`
270			`.D( iSource1[31:0] ),`
271			`.Q(wALUChannelZ1)`
272			`);`
273
274
275			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
276			`(`
277			`.Clock( Clock ),`
278			`.Reset( Reset),`
279			`.Enable( wLatchNow ),`
280			`.D( iSource0[95:64] ),`
281			`.Q(wALUChannelX2)`
282			`);`
283			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
284			`(`
285			`.Clock( Clock ),`
286			`.Reset( Reset),`
287			`.Enable( wLatchNow ),`
288			`.D( iSource0[63:32] ),`
289			`.Q(wALUChannelY2)`
290			`);`
291			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
292			`(`
293			`.Clock( Clock ),`
294			`.Reset( Reset),`
295			`.Enable( wLatchNow ),`
296			`.D( iSource0[31:0] ),`
297			`.Q(wALUChannelZ2)`
298			`);`
299
300
301			always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
302			`begin`
303			`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
304			`end`
305
306			always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
307			`begin`
308			`if ( iALUOutputReady )`
309			`begin`
310
311
312			`if (iBranchTaken)`
313			`LOGME"<BT>");
314
315			`if (iBranchNotTaken )`
316			`LOGME"<BNT>");
317
318			`if (oRAMWriteEnable)`
319			`LOGME"<WE>");
320
321			`LOGME "(%dns ",$time);
322			`case ( oALUOperation )`
323			`RETURN: `LOGME"RETURN");
324			`ADD: `LOGME"ADD");
325			`SUB: `LOGME"SUB");
326			`DIV: `LOGME"DIV");
327			`MUL: `LOGME"MUL");
328			`MAG: `LOGME"MAG");
329			`JGX: `LOGME"JGX");
330			`JLX: `LOGME"JLX");
331			`JGEX: `LOGME"JGEX");
332			`JGEY: `LOGME"JGEY");
333			`JGEZ: `LOGME"JGEZ");
334			`JLEX: `LOGME"JLEX");
335			`JLEY: `LOGME"JLEY");
336			`JLEZ: `LOGME"JLEZ");
337			`JMP: `LOGME"JMP");
338			`ZERO: `LOGME"ZERO");
339			`JNEX: `LOGME"JNEX");
340			`JNEY: `LOGME"JNEY");
341			`JNEZ: `LOGME"JNEZ");
342			`JEQX: `LOGME"JEQX");
343			`JEQY: `LOGME"JEQY");
344			`JEQZ: `LOGME"JEQZ");
345			`CROSS: `LOGME"CROSS");
346			`DOT: `LOGME"DOT");
347			`SETX: `LOGME"SETX");
348			`SETY: `LOGME"SETY");
349			`SETZ: `LOGME"SETZ");
350			`NOP: `LOGME"NOP");
351			`COPY: `LOGME"COPY");
352			`INC: `LOGME"INC");
353			`DEC: `LOGME"DEC");
354			`MOD: `LOGME"MOD");
355			`FRAC: `LOGME"FRAC");
356			`NEG: `LOGME"NEG");
357			`SWIZZLE3D: `LOGME"SWIZZLE3D");
358			`MULP: `LOGME"MULP");
359			`XCHANGEX: `LOGME"XCHANGEX");
360			`IMUL: `LOGME"IMUL");
361			`UNSCALE: `LOGME"UNSCALE");
362			`INCX: `LOGME"INCX");
363			`INCY: `LOGME"INCY");
364			`INCZ: `LOGME"INCZ");
365			`OMWRITE: `LOGME"OMWRITE");
366			`TMREAD: `LOGME"TMREAD");
367			`LEA: `LOGME"LEA");
368			`CALL: `LOGME"CALL");
369			`RET: `LOGME"RET");
370			`DEBUG_PRINT:
371			`begin`
372			`LOGME"DEBUG_PRINT");
373
374			`end`
375			`default:`
376			`begin`
377			`LOGME"********ERROR UNKNOWN OP*******");
378			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
379			`// $stop();`
380			`end`
381			`endcase`
382
383			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
384			`oRAMWriteAddress,`
385			`wALUChannelX1,wALUChannelY1,wALUChannelZ1,`
386			`wALUChannelX2,wALUChannelY2,wALUChannelZ2`
387
388			`);`
389
390			if (oALUOperation == `RETURN)
391			`LOGME"\n\n\n");
392
393			`end`
394			`end //always`
395
396			always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
397			`begin`
398			`if ( iALUOutputReady )`
399			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
400			`end //always`
401			`endif
402
403			`endmodule`