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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_ExecutionFSM.v] - Blame information for rev 174

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`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATAOR
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET                                                        0
`define EXEU_INITIAL_STATE                                              1
`define EXEU_WAIT_FOR_DECODE                                            2
`define EXEU_FETCH_DECODED_INST                                 3
`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
`define EXEU_WRITE_BACK_TO_RAM                                  5
`define EXEU_HANDLE_JUMP                                                        7
 
 
 
module ExecutionFSM
(
input wire                                                              Clock,
input wire                                                              Reset,
 
input   wire                                                                            iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
//output        reg                                                                     ReadyForNextInstruction,
output wire                                                                     oJumpFlag                       ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
output  wire                                                                    oRAMWriteEnable         ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
output  wire                                                                    oExeLatchedValues,
output  reg                                                                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
output  wire                                                                                                    oTriggerALU,
 
input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
input wire                                                                                                              iALUOutputReady,
input   wire                                                                                                            iBranchTaken,
input wire                                                                                                              iBranchNotTaken,
 
 
`ifdef DEBUG
        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
        input wire [`MAX_CORES-1:0]         iDebug_CoreID,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
assign oALUChannelX1 = iSource1[95:64];
assign oALUChannelY1 = iSource1[63:32];
assign oALUChannelZ1 = iSource1[31:0];
 
assign oALUChannelX2 = iSource0[95:64];
assign oALUChannelY2 = iSource0[63:32];
assign oALUChannelZ2 = iSource0[31:0];
 
assign oALUOperation = iOperation;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iDestination ),
        .Q(oRAMWriteAddress)
);
 
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
                CurrentState <= `EXEU_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
                  //------------------------------------------
                  `EXEU_AFTER_RESET:
                  begin
                                //ReadyForNextInstruction = 1;
                                oBusy                                                   = 0;
                                rInputLatchesEnabled            =       1;
 
 
                                NextState       = `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /**
                        At the same time iDecodeDone goes to 1, our Flops
                        will store the value, so next clock cycle we can
                        tell IDU to go ahead and decode the next instruction
                        in the pipeline.
                  */
                  `EXEU_WAIT_FOR_DECODE:
                  begin
 
 
                                //ReadyForNextInstruction = 1;
                                oBusy                                                   = 0;
                                rInputLatchesEnabled            =       1;
 
 
                        if ( iDecodeDone )      //This same thing triggers the ALU
                                NextState       = `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState       = `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /*
                  If the instruction is aritmetic then pass the parameters
                  the ALU, else if it store iOperation then...
                  */
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
                  begin
 
                                //ReadyForNextInstruction = 0;                                          //*
                                oBusy                                                   = 1;
                                rInputLatchesEnabled            =       0;               //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
                                        NextState = `EXEU_WAIT_FOR_DECODE;
                                else
                                        NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
                  end
                  //------------------------------------------
                  `EXEU_WRITE_BACK_TO_RAM:
                  begin
 
                                //ReadyForNextInstruction = 0;                                          
                                oBusy                                                   = 1;
                                rInputLatchesEnabled            =       1;
 
                        if ( iDecodeDone )
                                NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState = `EXEU_WAIT_FOR_DECODE;
 
                  end
 
                  //------------------------------------------
                  default:
                  begin
 
                                //ReadyForNextInstruction = 1;
                                oBusy                                                   = 0;
                                rInputLatchesEnabled            =       1;
 
                                NextState = `EXEU_AFTER_RESET;
                  end
                  //------------------------------------------
        endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
        $display("Opening ucode dump file....\n");
        ucode_file = $fopen("Code.log","w");
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
        $display("Opening Register lof file...\n");
        reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[95:64] ),
        .Q(wALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[63:32] ),
        .Q(wALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[31:0] ),
        .Q(wALUChannelZ1)
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[95:64] ),
        .Q(wALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[63:32] ),
        .Q(wALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[31:0] ),
        .Q(wALUChannelZ2)
);
 
 
        always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
        begin
                `LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
        end
 
        always @ (negedge  Clock && iDebug_CoreID == `DEBUG_CORE)
        begin
        if ( iALUOutputReady )
        begin
 
 
                if (iBranchTaken)
                        `LOGME"<BT>");
 
                if (iBranchNotTaken     )
                        `LOGME"<BNT>");
 
                if (oRAMWriteEnable)
                        `LOGME"<WE>");
 
                `LOGME "(%dns ",$time);
                                        case ( oALUOperation )
                                        `RETURN: `LOGME"RETURN");
                                        `ADD:   `LOGME"ADD");
                                        `SUB:           `LOGME"SUB");
                                        `DIV:           `LOGME"DIV");
                                        `MUL:   `LOGME"MUL");
                                        `MAG:           `LOGME"MAG");
                                        `JGX:           `LOGME"JGX");
                                        `JLX:           `LOGME"JLX");
                                        `JGEX:  `LOGME"JGEX");
                                        `JGEY:  `LOGME"JGEY");
                                        `JGEZ:  `LOGME"JGEZ");
                                        `JLEX:  `LOGME"JLEX");
                                        `JLEY:  `LOGME"JLEY");
                                        `JLEZ:  `LOGME"JLEZ");
                                        `JMP:           `LOGME"JMP");
                                        `ZERO:  `LOGME"ZERO");
                                        `JNEX:  `LOGME"JNEX");
                                        `JNEY:  `LOGME"JNEY");
                                        `JNEZ:  `LOGME"JNEZ");
                                        `JEQX:  `LOGME"JEQX");
                                        `JEQY:  `LOGME"JEQY");
                                        `JEQZ:  `LOGME"JEQZ");
                                        `CROSS: `LOGME"CROSS");
                                        `DOT:           `LOGME"DOT");
                                        `SETX:  `LOGME"SETX");
                                        `SETY:  `LOGME"SETY");
                                        `SETZ:  `LOGME"SETZ");
                                        `NOP:   `LOGME"NOP");
                                        `COPY:  `LOGME"COPY");
                                        `INC:           `LOGME"INC");
                                        `DEC:           `LOGME"DEC");
                                        `MOD:           `LOGME"MOD");
                                        `FRAC:  `LOGME"FRAC");
                                        `NEG:    `LOGME"NEG");
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
                                        `MULP:          `LOGME"MULP");
                                        `XCHANGEX:      `LOGME"XCHANGEX");
                                        `IMUL:      `LOGME"IMUL");
                                        `UNSCALE:      `LOGME"UNSCALE");
                                        `INCX: `LOGME"INCX");
                                        `INCY: `LOGME"INCY");
                                        `INCZ: `LOGME"INCZ");
                                        `OMWRITE: `LOGME"OMWRITE");
                                        `TMREAD: `LOGME"TMREAD");
                                        `LEA:     `LOGME"LEA");
                                        `CALL:    `LOGME"CALL");
                                        `RET:     `LOGME"RET");
                                        `DEBUG_PRINT:
                                        begin
                                                `LOGME"DEBUG_PRINT");
 
                                        end
                                        default:
                                        begin
                                                `LOGME"**********ERROR UNKNOWN OP*********");
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
                                        //      $stop();
                                        end
                                        endcase
 
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
                                        oRAMWriteAddress,
                                        wALUChannelX1,wALUChannelY1,wALUChannelZ1,
                                        wALUChannelX2,wALUChannelY2,wALUChannelZ2
 
                                        );
 
                                        if (oALUOperation == `RETURN)
                                                `LOGME"\n\n\n");
 
                end
        end //always
 
        always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
        begin
        if ( iALUOutputReady )
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
        end //always
`endif
 
endmodule

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Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_ExecutionFSM.v] - Blame information for rev 174

Line No.	Rev	Author	Line
1	158	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3	174	diegovalve	`ifdef VERILATAOR
4			`endif
5	158	diegovalve	`/**********************************************************************************`
6			`Theia, Ray Cast Programable graphic Processing Unit.`
7			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
8
9			`This program is free software; you can redistribute it and/or`
10			`modify it under the terms of the GNU General Public License`
11			`as published by the Free Software Foundation; either version 2`
12			`of the License, or (at your option) any later version.`
13
14			`This program is distributed in the hope that it will be useful,`
15			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`GNU General Public License for more details.`
18
19			`You should have received a copy of the GNU General Public License`
20			`along with this program; if not, write to the Free Software`
21			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
22
23			`***********************************************************************************/`
24			`define EXEU_AFTER_RESET 0
25			`define EXEU_INITIAL_STATE 1
26			`define EXEU_WAIT_FOR_DECODE 2
27			`define EXEU_FETCH_DECODED_INST 3
28			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
29			`define EXEU_WRITE_BACK_TO_RAM 5
30			`define EXEU_HANDLE_JUMP 7
31
32
33
34			`module ExecutionFSM`
35			`(`
36			`input wire Clock,`
37			`input wire Reset,`
38
39			`input wire iDecodeDone,`
40			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
41			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
42			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
43			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
44			`//output reg ReadyForNextInstruction,`
45			`output wire oJumpFlag ,`
46			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
47			`output wire oRAMWriteEnable ,`
48			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
49			`output wire oExeLatchedValues,`
50			`output reg oBusy ,`
51
52			`//ALU ports and control signals`
53			output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
54			output wire [`WIDTH-1:0] oALUChannelX1,
55			output wire [`WIDTH-1:0] oALUChannelY1,
56			output wire [`WIDTH-1:0] oALUChannelZ1,
57			output wire [`WIDTH-1:0] oALUChannelX2,
58			output wire [`WIDTH-1:0] oALUChannelY2,
59			output wire [`WIDTH-1:0] oALUChannelZ2,
60			`output wire oTriggerALU,`
61
62			input wire [`WIDTH-1:0] iALUResultX,
63			input wire [`WIDTH-1:0] iALUResultY,
64			input wire [`WIDTH-1:0] iALUResultZ,
65			`input wire iALUOutputReady,`
66			`input wire iBranchTaken,`
67			`input wire iBranchNotTaken,`
68
69
70			`ifdef DEBUG
71			input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
72			input wire [`MAX_CORES-1:0] iDebug_CoreID,
73			`endif
74			`//Data forward Signals`
75			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
76
77
78			`);`
79
80			`wire wLatchNow;`
81			`reg rInputLatchesEnabled;`
82
83			`//If ALU says jump, just pass along`
84			`assign oJumpFlag = iBranchTaken;`
85			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
86			`assign oJumpIp = oRAMWriteAddress;`
87
88			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
89			`assign oExeLatchedValues = wLatchNow;`
90			`assign oTriggerALU = wLatchNow;`
91
92			`wire wOperationIsJump;`
93			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
94
95			`//Don't allow me to write back back if the operation is a NOP`
96			`ifdef DEBUG
97			`assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&`
98			(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
99			`else
100			assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
101			`endif
102
103
104			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
105
106			`assign oALUChannelX1 = iSource1[95:64];`
107			`assign oALUChannelY1 = iSource1[63:32];`
108			`assign oALUChannelZ1 = iSource1[31:0];`
109
110			`assign oALUChannelX2 = iSource0[95:64];`
111			`assign oALUChannelY2 = iSource0[63:32];`
112			`assign oALUChannelZ2 = iSource0[31:0];`
113
114			`assign oALUOperation = iOperation;`
115
116			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
117			`(`
118			`.Clock( Clock ),//wLatchNow ),`
119			`.Reset( Reset),`
120			`.Enable( wLatchNow ),//1'b1 ),`
121			`.D( iDestination ),`
122			`.Q(oRAMWriteAddress)`
123			`);`
124
125			`//Data forwarding`
126			`assign oLastDestination = oRAMWriteAddress;`
127
128			`reg [7:0] CurrentState;`
129			`reg [7:0] NextState;`
130
131
132			`//------------------------------------------------`
133			`always @(posedge Clock or posedge Reset)`
134			`begin`
135
136
137
138			`if (Reset)`
139			CurrentState <= `EXEU_AFTER_RESET;
140			`else`
141			`CurrentState <= NextState;`
142
143			`end`
144			`//------------------------------------------------`
145
146
147			`always @( * )`
148			`begin`
149			`case (CurrentState)`
150			`//------------------------------------------`
151			`EXEU_AFTER_RESET:
152			`begin`
153			`//ReadyForNextInstruction = 1;`
154			`oBusy = 0;`
155			`rInputLatchesEnabled = 1;`
156
157
158			NextState = `EXEU_WAIT_FOR_DECODE;
159			`end`
160			`//------------------------------------------`
161			`/**`
162			`At the same time iDecodeDone goes to 1, our Flops`
163			`will store the value, so next clock cycle we can`
164			`tell IDU to go ahead and decode the next instruction`
165			`in the pipeline.`
166			`*/`
167			`EXEU_WAIT_FOR_DECODE:
168			`begin`
169
170
171			`//ReadyForNextInstruction = 1;`
172			`oBusy = 0;`
173			`rInputLatchesEnabled = 1;`
174
175
176			`if ( iDecodeDone ) //This same thing triggers the ALU`
177			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
178			`else`
179			NextState = `EXEU_WAIT_FOR_DECODE;
180			`end`
181			`//------------------------------------------`
182			`/*`
183			`If the instruction is aritmetic then pass the parameters`
184			`the ALU, else if it store iOperation then...`
185			`*/`
186			`EXEU_WAIT_FOR_ALU_EXECUTION:
187			`begin`
188
189			`//ReadyForNextInstruction = 0; //*`
190			`oBusy = 1;`
191			`rInputLatchesEnabled = 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
192
193
194
195			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
196			NextState = `EXEU_WAIT_FOR_DECODE;
197			`else`
198			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
199			`end`
200			`//------------------------------------------`
201			`EXEU_WRITE_BACK_TO_RAM:
202			`begin`
203
204			`//ReadyForNextInstruction = 0;`
205			`oBusy = 1;`
206			`rInputLatchesEnabled = 1;`
207
208			`if ( iDecodeDone )`
209			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
210			`else`
211			NextState = `EXEU_WAIT_FOR_DECODE;
212
213			`end`
214
215			`//------------------------------------------`
216			`default:`
217			`begin`
218
219			`//ReadyForNextInstruction = 1;`
220			`oBusy = 0;`
221			`rInputLatchesEnabled = 1;`
222
223			NextState = `EXEU_AFTER_RESET;
224			`end`
225			`//------------------------------------------`
226			`endcase`
227			`end`
228
229			`//-----------------------------------------------------------------------`
230			`ifdef DUMP_CODE
231			`integer ucode_file;`
232			`integer reg_log;`
233			`initial`
234			`begin`
235
236			`$display("Opening ucode dump file....\n");`
237			`ucode_file = $fopen("Code.log","w");`
238			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
239			`$display("Opening Register lof file...\n");`
240			`reg_log = $fopen("Registers.log","w");`
241
242			`end`
243
244			`endif //Ucode dump
245
246			`//-----------------------------------------------------------------------`
247			`ifdef DEBUG
248			wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
249			wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
250
251			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
252			`(`
253			`.Clock( Clock ),`
254			`.Reset( Reset),`
255			`.Enable( wLatchNow ),`
256			`.D( iSource1[95:64] ),`
257			`.Q(wALUChannelX1)`
258			`);`
259			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
260			`(`
261			`.Clock( Clock ),`
262			`.Reset( Reset),`
263			`.Enable( wLatchNow ),`
264			`.D( iSource1[63:32] ),`
265			`.Q(wALUChannelY1)`
266			`);`
267			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
268			`(`
269			`.Clock( Clock ),`
270			`.Reset( Reset),`
271			`.Enable( wLatchNow ),`
272			`.D( iSource1[31:0] ),`
273			`.Q(wALUChannelZ1)`
274			`);`
275
276
277			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
278			`(`
279			`.Clock( Clock ),`
280			`.Reset( Reset),`
281			`.Enable( wLatchNow ),`
282			`.D( iSource0[95:64] ),`
283			`.Q(wALUChannelX2)`
284			`);`
285			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
286			`(`
287			`.Clock( Clock ),`
288			`.Reset( Reset),`
289			`.Enable( wLatchNow ),`
290			`.D( iSource0[63:32] ),`
291			`.Q(wALUChannelY2)`
292			`);`
293			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
294			`(`
295			`.Clock( Clock ),`
296			`.Reset( Reset),`
297			`.Enable( wLatchNow ),`
298			`.D( iSource0[31:0] ),`
299			`.Q(wALUChannelZ2)`
300			`);`
301
302
303			always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
304			`begin`
305			`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
306			`end`
307
308			always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
309			`begin`
310			`if ( iALUOutputReady )`
311			`begin`
312
313
314			`if (iBranchTaken)`
315			`LOGME"<BT>");
316
317			`if (iBranchNotTaken )`
318			`LOGME"<BNT>");
319
320			`if (oRAMWriteEnable)`
321			`LOGME"<WE>");
322
323			`LOGME "(%dns ",$time);
324			`case ( oALUOperation )`
325			`RETURN: `LOGME"RETURN");
326			`ADD: `LOGME"ADD");
327			`SUB: `LOGME"SUB");
328			`DIV: `LOGME"DIV");
329			`MUL: `LOGME"MUL");
330			`MAG: `LOGME"MAG");
331			`JGX: `LOGME"JGX");
332			`JLX: `LOGME"JLX");
333			`JGEX: `LOGME"JGEX");
334			`JGEY: `LOGME"JGEY");
335			`JGEZ: `LOGME"JGEZ");
336			`JLEX: `LOGME"JLEX");
337			`JLEY: `LOGME"JLEY");
338			`JLEZ: `LOGME"JLEZ");
339			`JMP: `LOGME"JMP");
340			`ZERO: `LOGME"ZERO");
341			`JNEX: `LOGME"JNEX");
342			`JNEY: `LOGME"JNEY");
343			`JNEZ: `LOGME"JNEZ");
344			`JEQX: `LOGME"JEQX");
345			`JEQY: `LOGME"JEQY");
346			`JEQZ: `LOGME"JEQZ");
347			`CROSS: `LOGME"CROSS");
348			`DOT: `LOGME"DOT");
349			`SETX: `LOGME"SETX");
350			`SETY: `LOGME"SETY");
351			`SETZ: `LOGME"SETZ");
352			`NOP: `LOGME"NOP");
353			`COPY: `LOGME"COPY");
354			`INC: `LOGME"INC");
355			`DEC: `LOGME"DEC");
356			`MOD: `LOGME"MOD");
357			`FRAC: `LOGME"FRAC");
358			`NEG: `LOGME"NEG");
359			`SWIZZLE3D: `LOGME"SWIZZLE3D");
360			`MULP: `LOGME"MULP");
361			`XCHANGEX: `LOGME"XCHANGEX");
362			`IMUL: `LOGME"IMUL");
363			`UNSCALE: `LOGME"UNSCALE");
364			`INCX: `LOGME"INCX");
365			`INCY: `LOGME"INCY");
366			`INCZ: `LOGME"INCZ");
367			`OMWRITE: `LOGME"OMWRITE");
368			`TMREAD: `LOGME"TMREAD");
369			`LEA: `LOGME"LEA");
370			`CALL: `LOGME"CALL");
371			`RET: `LOGME"RET");
372			`DEBUG_PRINT:
373			`begin`
374			`LOGME"DEBUG_PRINT");
375
376			`end`
377			`default:`
378			`begin`
379			`LOGME"********ERROR UNKNOWN OP*******");
380			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
381			`// $stop();`
382			`end`
383			`endcase`
384
385			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
386			`oRAMWriteAddress,`
387			`wALUChannelX1,wALUChannelY1,wALUChannelZ1,`
388			`wALUChannelX2,wALUChannelY2,wALUChannelZ2`
389
390			`);`
391
392			if (oALUOperation == `RETURN)
393			`LOGME"\n\n\n");
394
395			`end`
396			`end //always`
397
398			always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
399			`begin`
400			`if ( iALUOutputReady )`
401			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
402			`end //always`
403			`endif
404
405	174	diegovalve	`endmodule`