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`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATAOR
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET             0
`define EXEU_INITIAL_STATE           1
`define EXEU_WAIT_FOR_DECODE         2
`define EXEU_FETCH_DECODED_INST      3
`define EXEU_WAIT_FOR_ALU_EXECUTION  4
`define EXEU_WRITE_BACK_TO_RAM       5
`define EXEU_HANDLE_JUMP             7
 
 
 
module ExecutionFSM
(
input wire                              Clock,
input wire                              Reset,
 
input wire                              iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]  iOperation,
input wire[`DATA_ROW_WIDTH-1:0]         iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]     iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]         RAMBus,
output wire                             oJumpFlag    ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]   oJumpIp     ,
output  wire                            oRAMWriteEnable  ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]  oRAMWriteAddress  ,
output  wire                            oExeLatchedValues,
output  reg                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]    oALUOperation,
output  wire [`WIDTH-1:0]                    oALUChannelX1,
output  wire [`WIDTH-1:0]                    oALUChannelY1,
output  wire [`WIDTH-1:0]                    oALUChannelZ1,
output  wire [`WIDTH-1:0]                    oALUChannelX2,
output  wire [`WIDTH-1:0]                    oALUChannelY2,
output  wire [`WIDTH-1:0]                    oALUChannelZ2,
output  wire                                 oTriggerALU,
 
input  wire   [`WIDTH-1:0]                   iALUResultX,
input  wire   [`WIDTH-1:0]                   iALUResultY,
input wire   [`WIDTH-1:0]                    iALUResultZ,
input wire                                   iALUOutputReady,
input wire                                   iBranchTaken,
input wire                                   iBranchNotTaken,
 
 
`ifdef DEBUG
 input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
 input wire [`MAX_CORES-1:0]         iDebug_CoreID,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
 assign oRAMWriteEnable = iALUOutputReady && (!wOperationIsJump || oALUOperation == `RET ) &&
  (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
 assign oRAMWriteEnable = iALUOutputReady && (!wOperationIsJump || oALUOperation == `RET) && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
assign oALUChannelX1 = iSource1[95:64];
assign oALUChannelY1 = iSource1[63:32];
assign oALUChannelZ1 = iSource1[31:0];
 
assign oALUChannelX2 = iSource0[95:64];
assign oALUChannelY2 = iSource0[63:32];
assign oALUChannelZ2 = iSource0[31:0];
 
assign oALUOperation = iOperation;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
(
 .Clock( Clock ),//wLatchNow ),
 .Reset( Reset),
 .Enable( wLatchNow ),//1'b1 ),
 .D( iDestination ),
 .Q(oRAMWriteAddress)
);
 
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
  CurrentState <= `EXEU_AFTER_RESET;
    else
  CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
    //------------------------------------------
    `EXEU_AFTER_RESET:
    begin
    //ReadyForNextInstruction = 1;
    oBusy       = 0;
    rInputLatchesEnabled  = 1;
 
 
    NextState  = `EXEU_WAIT_FOR_DECODE;
    end
    //------------------------------------------
    /**
   At the same time iDecodeDone goes to 1, our Flops
   will store the value, so next clock cycle we can
   tell IDU to go ahead and decode the next instruction
   in the pipeline.
    */
    `EXEU_WAIT_FOR_DECODE:
    begin
 
 
    //ReadyForNextInstruction = 1;
    oBusy       = 0;
    rInputLatchesEnabled  = 1;
 
 
   if ( iDecodeDone ) //This same thing triggers the ALU
    NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
   else
    NextState = `EXEU_WAIT_FOR_DECODE;
    end
    //------------------------------------------
    /*
    If the instruction is aritmetic then pass the parameters
    the ALU, else if it store iOperation then...
    */
    `EXEU_WAIT_FOR_ALU_EXECUTION:
    begin
 
    //ReadyForNextInstruction = 0;      //*
    oBusy       = 1;
    rInputLatchesEnabled  = 0;  //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
    if ( iALUOutputReady ) /////This same thing enables writing th results to RAM
     NextState = `EXEU_WAIT_FOR_DECODE;
    else
     NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
    end
    //------------------------------------------
    `EXEU_WRITE_BACK_TO_RAM:
    begin
 
    //ReadyForNextInstruction = 0;      
    oBusy       = 1;
    rInputLatchesEnabled  = 1;
 
   if ( iDecodeDone )
    NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
   else
    NextState = `EXEU_WAIT_FOR_DECODE;
 
    end
 
    //------------------------------------------
    default:
    begin
 
    //ReadyForNextInstruction = 1;
    oBusy       = 0;
    rInputLatchesEnabled  = 1;
 
    NextState = `EXEU_AFTER_RESET;
    end
    //------------------------------------------
 endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
 $display("Opening ucode dump file....\n");
 ucode_file = $fopen("Code.log","w");
 $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
 $display("Opening Register lof file...\n");
 reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( wLatchNow ),
 .D( iSource1[95:64] ),
 .Q(wALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( wLatchNow ),
 .D( iSource1[63:32] ),
 .Q(wALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( wLatchNow ),
 .D( iSource1[31:0] ),
 .Q(wALUChannelZ1)
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( wLatchNow ),
 .D( iSource0[95:64] ),
 .Q(wALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( wLatchNow ),
 .D( iSource0[63:32] ),
 .Q(wALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( wLatchNow ),
 .D( iSource0[31:0] ),
 .Q(wALUChannelZ2)
);
 
 
 always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
 begin
  `LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
 end
 
 always @ (negedge  Clock && iDebug_CoreID == `DEBUG_CORE)
 begin
 if ( iALUOutputReady )
 begin
 
 
  if (iBranchTaken)
   `LOGME"<BT>");
 
  if (iBranchNotTaken )
   `LOGME"<BNT>");
 
  if (oRAMWriteEnable)
   `LOGME"<WE>");
 
  `LOGME "(%dns ",$time);
     case ( oALUOperation )
     `RETURN: `LOGME"RETURN");
     `ADD:  `LOGME"ADD");
     `SUB:  `LOGME"SUB");
     `DIV:  `LOGME"DIV");
     `MUL:  `LOGME"MUL");
     `MAG:  `LOGME"MAG");
     `JGX:  `LOGME"JGX");
     `JLX:  `LOGME"JLX");
     `JGEX: `LOGME"JGEX");
     `JGEY: `LOGME"JGEY");
     `JGEZ: `LOGME"JGEZ");
     `JLEX: `LOGME"JLEX");
     `JLEY: `LOGME"JLEY");
     `JLEZ: `LOGME"JLEZ");
     `JMP:  `LOGME"JMP");
     `ZERO: `LOGME"ZERO");
     `JNEX: `LOGME"JNEX");
     `JNEY: `LOGME"JNEY");
     `JNEZ: `LOGME"JNEZ");
     `JEQX: `LOGME"JEQX");
     `JEQY: `LOGME"JEQY");
     `JEQZ: `LOGME"JEQZ");
     `CROSS: `LOGME"CROSS");
     `DOT:  `LOGME"DOT");
     `SETX: `LOGME"SETX");
     `SETY: `LOGME"SETY");
     `SETZ: `LOGME"SETZ");
     `NOP:  `LOGME"NOP");
     `COPY: `LOGME"COPY");
     `INC:  `LOGME"INC");
     `DEC:  `LOGME"DEC");
     `MOD:  `LOGME"MOD");
     `FRAC: `LOGME"FRAC");
     `NEG:    `LOGME"NEG");
     `SWIZZLE3D: `LOGME"SWIZZLE3D");
     `MULP:  `LOGME"MULP");
     `XCHANGEX:  `LOGME"XCHANGEX");
          `XCHANGEY:  `LOGME"XCHANGEY");
          `XCHANGEZ:  `LOGME"XCHANGEZ");
     `IMUL:      `LOGME"IMUL");
     `UNSCALE:   `LOGME"UNSCALE");
          `RESCALE:    `LOGME"UNSCALE");
     `INCX: `LOGME"INCX");
     `INCY: `LOGME"INCY");
     `INCZ: `LOGME"INCZ");
     `OMWRITE: `LOGME"OMWRITE");
     `TMREAD: `LOGME"TMREAD");
     `LEA:     `LOGME"LEA");
     `CALL:    `LOGME"CALL");
     `RET:     `LOGME"RET");
     `DEBUG_PRINT:
     begin
      `LOGME"DEBUG_PRINT");
 
     end
     default:
     begin
      `LOGME"**********ERROR UNKNOWN OP*********");
      $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
     // $stop();
     end
     endcase
 
     `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
     oRAMWriteAddress,
     wALUChannelX1,wALUChannelY1,wALUChannelZ1,
     wALUChannelX2,wALUChannelY2,wALUChannelZ2
 
     );
 
     if (oALUOperation == `RETURN)
      `LOGME"\n\n\n");
 
  end
 end //always
 
 always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
 begin
 if ( iALUOutputReady )
  `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
 end //always
`endif
 
endmodule

Line No.	Rev	Author	Line
1	158	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3	174	diegovalve	`ifdef VERILATAOR
4			`endif
5	158	diegovalve	`/**********************************************************************************`
6			`Theia, Ray Cast Programable graphic Processing Unit.`
7			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
8
9			`This program is free software; you can redistribute it and/or`
10			`modify it under the terms of the GNU General Public License`
11			`as published by the Free Software Foundation; either version 2`
12			`of the License, or (at your option) any later version.`
13
14			`This program is distributed in the hope that it will be useful,`
15			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`GNU General Public License for more details.`
18
19			`You should have received a copy of the GNU General Public License`
20			`along with this program; if not, write to the Free Software`
21			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
22
23			`***********************************************************************************/`
24	175	diegovalve	`define EXEU_AFTER_RESET 0
25			`define EXEU_INITIAL_STATE 1
26			`define EXEU_WAIT_FOR_DECODE 2
27			`define EXEU_FETCH_DECODED_INST 3
28			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
29			`define EXEU_WRITE_BACK_TO_RAM 5
30			`define EXEU_HANDLE_JUMP 7
31	158	diegovalve
32
33
34			`module ExecutionFSM`
35			`(`
36	175	diegovalve	`input wire Clock,`
37			`input wire Reset,`
38	158	diegovalve
39	175	diegovalve	`input wire iDecodeDone,`
40			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
41			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
42			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
43			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
44			`output wire oJumpFlag ,`
45			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
46			`output wire oRAMWriteEnable ,`
47			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
48			`output wire oExeLatchedValues,`
49			`output reg oBusy ,`
50	158	diegovalve
51			`//ALU ports and control signals`
52	175	diegovalve	output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
53			output wire [`WIDTH-1:0] oALUChannelX1,
54			output wire [`WIDTH-1:0] oALUChannelY1,
55			output wire [`WIDTH-1:0] oALUChannelZ1,
56			output wire [`WIDTH-1:0] oALUChannelX2,
57			output wire [`WIDTH-1:0] oALUChannelY2,
58			output wire [`WIDTH-1:0] oALUChannelZ2,
59			`output wire oTriggerALU,`
60	158	diegovalve
61	175	diegovalve	input wire [`WIDTH-1:0] iALUResultX,
62			input wire [`WIDTH-1:0] iALUResultY,
63			input wire [`WIDTH-1:0] iALUResultZ,
64			`input wire iALUOutputReady,`
65			`input wire iBranchTaken,`
66			`input wire iBranchNotTaken,`
67	158	diegovalve
68
69			`ifdef DEBUG
70	175	diegovalve	input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
71			input wire [`MAX_CORES-1:0] iDebug_CoreID,
72	158	diegovalve	`endif
73			`//Data forward Signals`
74			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
75
76
77			`);`
78
79			`wire wLatchNow;`
80			`reg rInputLatchesEnabled;`
81
82			`//If ALU says jump, just pass along`
83			`assign oJumpFlag = iBranchTaken;`
84			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
85			`assign oJumpIp = oRAMWriteAddress;`
86
87			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
88			`assign oExeLatchedValues = wLatchNow;`
89			`assign oTriggerALU = wLatchNow;`
90
91			`wire wOperationIsJump;`
92			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
93
94			`//Don't allow me to write back back if the operation is a NOP`
95			`ifdef DEBUG
96	178	diegovalve	assign oRAMWriteEnable = iALUOutputReady && (!wOperationIsJump \|\| oALUOperation == `RET ) &&
97	175	diegovalve	(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
98	158	diegovalve	`else
99	178	diegovalve	assign oRAMWriteEnable = iALUOutputReady && (!wOperationIsJump \|\| oALUOperation == `RET) && oALUOperation != `NOP;
100	175	diegovalve	`endif
101	158	diegovalve
102
103			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
104
105			`assign oALUChannelX1 = iSource1[95:64];`
106			`assign oALUChannelY1 = iSource1[63:32];`
107			`assign oALUChannelZ1 = iSource1[31:0];`
108
109			`assign oALUChannelX2 = iSource0[95:64];`
110			`assign oALUChannelY2 = iSource0[63:32];`
111			`assign oALUChannelZ2 = iSource0[31:0];`
112
113			`assign oALUOperation = iOperation;`
114
115			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
116			`(`
117	175	diegovalve	`.Clock( Clock ),//wLatchNow ),`
118			`.Reset( Reset),`
119			`.Enable( wLatchNow ),//1'b1 ),`
120			`.D( iDestination ),`
121			`.Q(oRAMWriteAddress)`
122	158	diegovalve	`);`
123
124			`//Data forwarding`
125			`assign oLastDestination = oRAMWriteAddress;`
126
127			`reg [7:0] CurrentState;`
128			`reg [7:0] NextState;`
129
130
131			`//------------------------------------------------`
132			`always @(posedge Clock or posedge Reset)`
133			`begin`
134
135	175	diegovalve
136
137	158	diegovalve	`if (Reset)`
138	175	diegovalve	CurrentState <= `EXEU_AFTER_RESET;
139	158	diegovalve	`else`
140	175	diegovalve	`CurrentState <= NextState;`
141
142	158	diegovalve	`end`
143			`//------------------------------------------------`
144
145
146			`always @( * )`
147			`begin`
148			`case (CurrentState)`
149	175	diegovalve	`//------------------------------------------`
150			`EXEU_AFTER_RESET:
151			`begin`
152			`//ReadyForNextInstruction = 1;`
153			`oBusy = 0;`
154			`rInputLatchesEnabled = 1;`
155
156
157			NextState = `EXEU_WAIT_FOR_DECODE;
158			`end`
159			`//------------------------------------------`
160			`/**`
161			`At the same time iDecodeDone goes to 1, our Flops`
162			`will store the value, so next clock cycle we can`
163			`tell IDU to go ahead and decode the next instruction`
164			`in the pipeline.`
165			`*/`
166			`EXEU_WAIT_FOR_DECODE:
167			`begin`
168
169	158	diegovalve
170	175	diegovalve	`//ReadyForNextInstruction = 1;`
171			`oBusy = 0;`
172			`rInputLatchesEnabled = 1;`
173
174
175			`if ( iDecodeDone ) //This same thing triggers the ALU`
176			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
177			`else`
178			NextState = `EXEU_WAIT_FOR_DECODE;
179			`end`
180			`//------------------------------------------`
181			`/*`
182			`If the instruction is aritmetic then pass the parameters`
183			`the ALU, else if it store iOperation then...`
184			`*/`
185			`EXEU_WAIT_FOR_ALU_EXECUTION:
186			`begin`
187	158	diegovalve
188	175	diegovalve	`//ReadyForNextInstruction = 0; //*`
189			`oBusy = 1;`
190			`rInputLatchesEnabled = 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
191
192	158	diegovalve
193	175	diegovalve
194			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
195			NextState = `EXEU_WAIT_FOR_DECODE;
196			`else`
197			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
198			`end`
199			`//------------------------------------------`
200			`EXEU_WRITE_BACK_TO_RAM:
201			`begin`
202
203			`//ReadyForNextInstruction = 0;`
204			`oBusy = 1;`
205			`rInputLatchesEnabled = 1;`
206
207			`if ( iDecodeDone )`
208			NextState = `EXEU_WAIT_FOR_ALU_EXECUTION;
209			`else`
210			NextState = `EXEU_WAIT_FOR_DECODE;
211
212			`end`
213
214			`//------------------------------------------`
215			`default:`
216			`begin`
217
218			`//ReadyForNextInstruction = 1;`
219			`oBusy = 0;`
220			`rInputLatchesEnabled = 1;`
221	158	diegovalve
222	175	diegovalve	NextState = `EXEU_AFTER_RESET;
223			`end`
224			`//------------------------------------------`
225			`endcase`
226	158	diegovalve	`end`
227
228			`//-----------------------------------------------------------------------`
229			`ifdef DUMP_CODE
230			`integer ucode_file;`
231			`integer reg_log;`
232			`initial`
233			`begin`
234
235	175	diegovalve	`$display("Opening ucode dump file....\n");`
236			`ucode_file = $fopen("Code.log","w");`
237			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
238			`$display("Opening Register lof file...\n");`
239			`reg_log = $fopen("Registers.log","w");`
240
241	158	diegovalve	`end`
242
243			`endif //Ucode dump
244
245			`//-----------------------------------------------------------------------`
246			`ifdef DEBUG
247			wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
248			wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
249
250			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
251			`(`
252	175	diegovalve	`.Clock( Clock ),`
253			`.Reset( Reset),`
254			`.Enable( wLatchNow ),`
255			`.D( iSource1[95:64] ),`
256			`.Q(wALUChannelX1)`
257	158	diegovalve	`);`
258			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
259			`(`
260	175	diegovalve	`.Clock( Clock ),`
261			`.Reset( Reset),`
262			`.Enable( wLatchNow ),`
263			`.D( iSource1[63:32] ),`
264			`.Q(wALUChannelY1)`
265	158	diegovalve	`);`
266			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
267			`(`
268	175	diegovalve	`.Clock( Clock ),`
269			`.Reset( Reset),`
270			`.Enable( wLatchNow ),`
271			`.D( iSource1[31:0] ),`
272			`.Q(wALUChannelZ1)`
273	158	diegovalve	`);`
274
275
276			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
277			`(`
278	175	diegovalve	`.Clock( Clock ),`
279			`.Reset( Reset),`
280			`.Enable( wLatchNow ),`
281			`.D( iSource0[95:64] ),`
282			`.Q(wALUChannelX2)`
283	158	diegovalve	`);`
284			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
285			`(`
286	175	diegovalve	`.Clock( Clock ),`
287			`.Reset( Reset),`
288			`.Enable( wLatchNow ),`
289			`.D( iSource0[63:32] ),`
290			`.Q(wALUChannelY2)`
291	158	diegovalve	`);`
292			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
293			`(`
294	175	diegovalve	`.Clock( Clock ),`
295			`.Reset( Reset),`
296			`.Enable( wLatchNow ),`
297			`.D( iSource0[31:0] ),`
298			`.Q(wALUChannelZ2)`
299	158	diegovalve	`);`
300
301
302	175	diegovalve	always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
303			`begin`
304			`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
305			`end`
306	158	diegovalve
307	175	diegovalve	always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
308			`begin`
309			`if ( iALUOutputReady )`
310			`begin`
311
312
313			`if (iBranchTaken)`
314			`LOGME"<BT>");
315
316			`if (iBranchNotTaken )`
317			`LOGME"<BNT>");
318
319			`if (oRAMWriteEnable)`
320			`LOGME"<WE>");
321
322			`LOGME "(%dns ",$time);
323			`case ( oALUOperation )`
324			`RETURN: `LOGME"RETURN");
325			`ADD: `LOGME"ADD");
326			`SUB: `LOGME"SUB");
327			`DIV: `LOGME"DIV");
328			`MUL: `LOGME"MUL");
329			`MAG: `LOGME"MAG");
330			`JGX: `LOGME"JGX");
331			`JLX: `LOGME"JLX");
332			`JGEX: `LOGME"JGEX");
333			`JGEY: `LOGME"JGEY");
334			`JGEZ: `LOGME"JGEZ");
335			`JLEX: `LOGME"JLEX");
336			`JLEY: `LOGME"JLEY");
337			`JLEZ: `LOGME"JLEZ");
338			`JMP: `LOGME"JMP");
339			`ZERO: `LOGME"ZERO");
340			`JNEX: `LOGME"JNEX");
341			`JNEY: `LOGME"JNEY");
342			`JNEZ: `LOGME"JNEZ");
343			`JEQX: `LOGME"JEQX");
344			`JEQY: `LOGME"JEQY");
345			`JEQZ: `LOGME"JEQZ");
346			`CROSS: `LOGME"CROSS");
347			`DOT: `LOGME"DOT");
348			`SETX: `LOGME"SETX");
349			`SETY: `LOGME"SETY");
350			`SETZ: `LOGME"SETZ");
351			`NOP: `LOGME"NOP");
352			`COPY: `LOGME"COPY");
353			`INC: `LOGME"INC");
354			`DEC: `LOGME"DEC");
355			`MOD: `LOGME"MOD");
356			`FRAC: `LOGME"FRAC");
357			`NEG: `LOGME"NEG");
358			`SWIZZLE3D: `LOGME"SWIZZLE3D");
359			`MULP: `LOGME"MULP");
360			`XCHANGEX: `LOGME"XCHANGEX");
361	188	diegovalve	`XCHANGEY: `LOGME"XCHANGEY");
362			`XCHANGEZ: `LOGME"XCHANGEZ");
363	175	diegovalve	`IMUL: `LOGME"IMUL");
364	178	diegovalve	`UNSCALE: `LOGME"UNSCALE");
365			`RESCALE: `LOGME"UNSCALE");
366	175	diegovalve	`INCX: `LOGME"INCX");
367			`INCY: `LOGME"INCY");
368			`INCZ: `LOGME"INCZ");
369			`OMWRITE: `LOGME"OMWRITE");
370			`TMREAD: `LOGME"TMREAD");
371			`LEA: `LOGME"LEA");
372			`CALL: `LOGME"CALL");
373			`RET: `LOGME"RET");
374			`DEBUG_PRINT:
375			`begin`
376			`LOGME"DEBUG_PRINT");
377
378			`end`
379			`default:`
380			`begin`
381			`LOGME"********ERROR UNKNOWN OP*******");
382			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
383			`// $stop();`
384			`end`
385			`endcase`
386
387			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
388			`oRAMWriteAddress,`
389			`wALUChannelX1,wALUChannelY1,wALUChannelZ1,`
390			`wALUChannelX2,wALUChannelY2,wALUChannelZ2`
391
392			`);`
393
394			if (oALUOperation == `RETURN)
395			`LOGME"\n\n\n");
396
397			`end`
398			`end //always`
399
400			always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
401			`begin`
402			`if ( iALUOutputReady )`
403			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
404			`end //always`
405	158	diegovalve	`endif
406
407	174	diegovalve	`endmodule`

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