OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_MEM2WBM.v] - Blame information for rev 228

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 158 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
3
 
4
/**********************************************************************************
5
Theia, Ray Cast Programable graphic Processing Unit.
6
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
7
 
8
This program is free software; you can redistribute it and/or
9
modify it under the terms of the GNU General Public License
10
as published by the Free Software Foundation; either version 2
11
of the License, or (at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21
 
22
***********************************************************************************/
23
/*
24
This unit is used when the External Address that comes into IO is not a immediate value,
25
ie. it is a value that we need to read from one of our internal memory locations.
26
Since each internal memory locations contains 3 * 32bits slots, ie X,Y and Z parts of the
27
memory location, then we make three requests for external data, one for every X Y and Z
28
part of our internal registry.So, summarising, each internal memory location, stores 3
29
external memory addresses to request to WBM. Once the 3 data has been read from outside world,
30
they will get stored back into 3 consecutive inernal memory addreses starting from
31
iDataInitialStorageAddress
32
*/
33
//---------------------------------------------------------------------
34
module MEM2WBMUnitB
35
(
36
input wire                          Clock,
37
input wire                          Reset,
38
input wire                                                                      iEnable,
39
//output reg                          oSetAddress,
40
input wire[`DATA_ADDRESS_WIDTH-1:0]  iMEMDataPointer,
41
input wire[`DATA_ADDRESS_WIDTH-1:0]  iMEMDataPointer2,
42
output wire [`WIDTH-1:0]            oReadDataElement,
43
output wire [`WIDTH-1:0]            oReadDataElement2,
44
output wire[`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress,    //This tells MEM unit from wich address we want to read
45
output wire[`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress2,    //This tells MEM unit from wich address we want to read
46
input wire [`DATA_ROW_WIDTH-1:0]         iReadDataBus,             //This comes from the MEM unit
47
input wire [`DATA_ROW_WIDTH-1:0]         iReadDataBus2,            //This comes from the MEM unit
48
output wire                                                                     oDataWriteEnable,
49
output wire                                                                     oDataWriteEnable2,
50
output wire                          oDataAvailable,
51
input wire                          iRequestNextElement,
52
input wire[`DATA_ADDRESS_WIDTH-1:0]  iDataInitialStorageAddress, //Initial address to store data ////########
53
output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,  //Were to store the values comming from WBM ////########
54
output wire                          oDone
55
);
56
assign oDataWriteEnable2 = 0;
57
assign oDataWriteEnable = 0; //We only read.
58
wire [3:0] wXYZSelector;
59
wire[`WIDTH-1:0] wValueFromBus,wLatchedValue;
60
assign oDataReadAddress = iMEMDataPointer;
61
assign oDataReadAddress2 = iMEMDataPointer2;
62
assign oDone = wXYZSelector[3];
63
 
64
wire wLacthNow;
65
 
66
wire iRequestNextElement_Delay;
67
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_x
68
(
69
        .Clock(         Clock ),
70
        .Reset(         Reset ),
71
        .Enable( 1'b1 ),
72
        .D( iRequestNextElement ),
73
        .Q( iRequestNextElement_Delay )
74
 
75
);
76
 
77
assign oDataAvailable = iEnable & ~iRequestNextElement_Delay & wLacthNow;// & ~oDone;
78
 
79
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_EnableDelay
80
(
81
        .Clock(         Clock ),
82
        .Reset(         Reset ),
83
        .Enable( 1'b1 ),
84
        .D( iEnable ),
85
        .Q( wLacthNow )
86
 
87
);
88
 
89
assign oDataWriteAddress = iDataInitialStorageAddress;
90
 
91
 
92
SHIFTLEFT_POSEDGE #(4) SHL
93
(
94
  .Clock(iRequestNextElement | ~iEnable),
95
  .Enable(1'b1),
96
  .Reset(~iEnable | Reset ),
97
  .Initial(4'b1),
98
  .O(wXYZSelector)
99
 
100
);
101
 
102
MUXFULLPARALELL_3SEL_WALKINGONE MUXA
103
 (
104
 .Sel( wXYZSelector[2:0] ),
105
 .I2( iReadDataBus[63:32]),
106
 .I1( iReadDataBus[95:64]),
107
 .I3( iReadDataBus[31:0] ),
108
 .O1( oReadDataElement )
109
 
110
 );
111
 
112
 
113
 
114
MUXFULLPARALELL_3SEL_WALKINGONE MUXA2
115
 (
116
 .Sel( wXYZSelector[2:0] ),
117
 .I2( iReadDataBus2[63:32]),
118
 .I1( iReadDataBus2[95:64]),
119
 .I3( iReadDataBus2[31:0] ),
120
 .O1( oReadDataElement2 )
121
 );
122
 
123
endmodule
124
//---------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.