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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_OMemInterface.v] - Blame information for rev 196

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Line No. Rev Author Line
1 158 diegovalve
`timescale 1ns / 1ps
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`include "aDefinitions.v"
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module Module_OMemInterface
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(
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        input wire Clock,
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        input wire Reset,
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        input wire                  iWriteEnable,
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        input wire [`DATA_ROW_WIDTH-1:0]     iData,
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        input wire [`DATA_ROW_WIDTH-1:0]     iAddress,
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        output wire [`WB_WIDTH-1:0] ADR_O,
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        output wire[`WB_WIDTH-1:0]  DAT_O,
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        output wire                                         WE_O
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);
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wire [2:0] wCurrentWord;
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assign WE_O = iWriteEnable;
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CIRCULAR_SHIFTLEFT_POSEDGE #(3) SHL
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(
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  .Clock(Clock),
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  .Enable(iWriteEnable),
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  .Reset(Reset),
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  .Initial(3'b1),
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  .O(wCurrentWord)
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);
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MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX1
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 (
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        .Sel( wCurrentWord ),
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        .I3(iAddress[31:0]),
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        .I2(iAddress[63:32]),
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        .I1(iAddress[95:64]),
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        .O1( ADR_O )
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 );
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 MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX2
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 (
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        .Sel( wCurrentWord ),
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        .I3(iData[31:0]),
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        .I2(iData[63:32]),
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        .I1(iData[95:64]),
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        .O1( DAT_O )
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 );
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endmodule

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