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`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Module_Swizzle.v"
`include "Module_ArithmeticComparison.v"
`include "Module_RadixRMul.v"
`include "Module_FixedPointDivision.v"
`include "Module_FixedPointSquareRoot.v"
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
 
 
 
//--------------------------------------------------------------
module VectorALU
(
 input wire                                   Clock,
 input wire                                   Reset,
 input  wire[`INSTRUCTION_OP_LENGTH-1:0]      iOperation,
 input  wire[`WIDTH-1:0]                      iChannel_Ax,
 input  wire[`WIDTH-1:0]                      iChannel_Bx,
 input  wire[`WIDTH-1:0]                      iChannel_Ay,
 input  wire[`WIDTH-1:0]                      iChannel_By,
 input  wire[`WIDTH-1:0]                      iChannel_Az,
 input  wire[`WIDTH-1:0]                      iChannel_Bz,
 output wire [`WIDTH-1:0]                     oResultA,
 output wire [`WIDTH-1:0]                     oResultB,
 output wire [`WIDTH-1:0]                     oResultC,
 input  wire                                  iInputReady,
 output reg                                   oBranchTaken,
 output reg                                   oBranchNotTaken,
 output reg                                   oReturnFromSub,
 input wire [`ROM_ADDRESS_WIDTH-1:0]          iCurrentIP,
 
 //Connections to the O Memory
 output wire [`DATA_ROW_WIDTH-1:0]            oOMEMWriteAddress,
 output wire [`DATA_ROW_WIDTH-1:0]            oOMEMWriteData,
 output wire                                  oOMEM_WriteEnable,
 //Connections to the R Memory
 output wire [`DATA_ROW_WIDTH-1:0]            oTMEMReadAddress,
 input wire [`DATA_ROW_WIDTH-1:0]             iTMEMReadData,
 input wire                                   iTMEMDataAvailable,
 output wire                                  oTMEMDataRequest,
 output reg                                   OutputReady
 
);
 
 
 
 
 
wire wMultiplcationUnscaled;
assign wMultiplcationUnscaled = (iOperation == `IMUL) ? 1'b1 : 1'b0;
 
//--------------------------------------------------------------
 
reg [7:0]  InputReadyA,InputReadyB,InputReadyC;
 
//------------------------------------------------------
/*
 This is the block that takes care of all tha arithmetic
 comparisons. Supported operations are <,>,<=,>=,==,!=
 
*/
//------------------------------------------------------
reg [`WIDTH-1:0] wMultiplicationA_Ax;
reg  [`WIDTH-1:0] wMultiplicationA_Bx;
wire [`LONG_WIDTH-1:0] wMultiplicationA_Result;
wire  wMultiplicationA_InputReady;
wire wMultiplicationA_OutputReady;
wire wMultiplicationOutputReady, wMultiplicationOutputReadyA,
wMultiplicationOutputReadyB,wMultiplicationOutputReadyC,wMultiplicationOutputReadyD;
 
wire wAddSubAOutputReady,wAddSubBOutputReady,wAddSubCOutputReady;
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation;
wire [`WIDTH-1:0] wSwizzleOutputX,wSwizzleOutputY,wSwizzleOutputZ;
 
//--------------------------------------------------------------------
reg [`WIDTH-1:0] ResultA,ResultB,ResultC;
 
//Output Flip Flops,
//This flip flop will control the outputs so that the
//values of the outputs change ONLY when when there is 
//a positive edge of OutputReady
 
FFD32_POSEDGE ResultAFFD
(
 .Clock( OutputReady ),
 .D( ResultA ),
 .Q( oResultA )
);
 
FFD32_POSEDGE ResultBFFD
(
 .Clock( OutputReady ),
 .D( ResultB ),
 .Q( oResultB )
);
 
FFD32_POSEDGE ResultCFFD
(
 .Clock( OutputReady ),
 .D( ResultC ),
 .Q( oResultC )
);
//--------------------------------------------------------------------
 
 
 
Swizzle3D Swizzle1
(
 .Source0_X( iChannel_Bx ),
 .Source0_Y( iChannel_By ),
 .Source0_Z( iChannel_Bz ),
 .iOperation( iChannel_Ax ),
 
 .SwizzleX( wSwizzleOutputX ),
 .SwizzleY( wSwizzleOutputY ),
 .SwizzleZ( wSwizzleOutputZ )
);
//---------------------------------------------------------------------
wire [`LONG_WIDTH-1:0] wModulus2N_ResultA,wModulus2N_ResultB,wModulus2N_ResultC;
 
//---------------------------------------------------------------------(
 
wire IOW_Operation,wOMEM_We;
assign IOW_Operation = (iOperation == `OMWRITE);
 
always @ ( * )
begin
 if (iOperation == `RET)
  oReturnFromSub = OutputReady;
 else
  oReturnFromSub = 1'b0;
 
end
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_AWE
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( 1'b1 ),
 .D( IOW_Operation ),
 .Q( wOMEM_We )
);
 
assign oOMEM_WriteEnable = wOMEM_We & IOW_Operation;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD1_A
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( iInputReady ),
 .D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ),
 .Q( oOMEMWriteAddress)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( iInputReady ),
 .D( {iChannel_Bx,iChannel_By,iChannel_Bz} ),
 .Q( oOMEMWriteData )
);
 
 
 
wire wTMReadOutputReady;
assign wTMReadOutputReady = iTMEMDataAvailable;
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( 1'b1 ),
 .D( iTMEMDataAvailable ),
 .Q( wTMReadOutputReady )
);
*/
//assign oTMEMReadAddress = {iChannel_Ax,iChannel_Ay,iChannel_Az};
 
//We wait 1 clock cycle before be send the data read request, because
//we need to lathc the values at the output
 
wire wOpTRead;
assign wOpTRead = ( iOperation == `TMREAD ) ? 1'b1 : 1'b0;
wire wTMEMRequest;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE123
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( 1'b1 ),
 .D( wOpTRead ),
 .Q( wTMEMRequest )
);
assign oTMEMDataRequest = wTMEMRequest & wOpTRead;
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B445
(
 .Clock( Clock ),
 .Reset( Reset),
 .Enable( iInputReady & wOpTRead ),
 .D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ),
 .Q( oTMEMReadAddress )
);
 
/*
 This MUX will select the apropiated X,Y or Z depending on
 wheter it is XYZ iOperation. This gets defined by the bits 3 and 4
 of iOperation, and only applies for oBranchTaken and Store operations.
*/
 
wire      wArithmeticComparison_Result;
wire      ArithmeticComparison_InputReady;
wire      ArithmeticComparison_OutputReady;
reg[`WIDTH-1:0]  ArithmeticComparison_A,ArithmeticComparison_B;
 
 
always @ ( * )
begin
 case ( {iOperation[4],iOperation[3]} )
  2'b01:   ArithmeticComparison_A = iChannel_Ax;
  2'b10:   ArithmeticComparison_A = iChannel_Ay;
  2'b11:  ArithmeticComparison_A = iChannel_Az;
  default: ArithmeticComparison_A = 0; //Should never happen
 endcase
end
//---------------------------------------------------------------------
always @ ( * )
begin
 case ( {iOperation[4],iOperation[3]} )
  2'b01:   ArithmeticComparison_B = iChannel_Bx;
  2'b10:   ArithmeticComparison_B = iChannel_By;
  2'b11:  ArithmeticComparison_B = iChannel_Bz;
  default: ArithmeticComparison_B = 0; //Should never happen
 endcase
end
 
//---------------------------------------------------------------------
/*
 The onbly instance of Aritmetic comparison in the ALU,
 ArithmeticComparison operations matches the 3 LSB of
 Global ALU iOperation for oBranchTaken Instruction family
*/
 
assign ArithmeticComparison_InputReady = iInputReady;
 
wire wArithmeticComparisonResult;
 
ArithmeticComparison ArithmeticComparison_1
(
 .Clock( Clock ),
 .X( ArithmeticComparison_A ),
 .Y( ArithmeticComparison_B ),
 .iOperation( iOperation[2:0] ),
 .iInputReady( ArithmeticComparison_InputReady ),
 .OutputReady( ArithmeticComparison_OutputReady ),
 .Result( wArithmeticComparisonResult )
);
 
 
assign  wArithmeticComparison_Result = wArithmeticComparisonResult && OutputReady;
//--------------------------------------------------------------------
 RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_A
(
 
 .Clock( Clock ),
 .Reset( Reset ),
 .A( wMultiplicationA_Ax ),
 .B( wMultiplicationA_Bx ),
 .R( wMultiplicationA_Result ),
 .iUnscaled( wMultiplcationUnscaled ),
 .iInputReady( wMultiplicationA_InputReady ),
 .OutputReady( wMultiplicationA_OutputReady )
);
 
//--------------------------------------------------------------------
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationA_Ax = iChannel_Ay; // Ay * Bz
 `MAG:   wMultiplicationA_Ax = iChannel_Ax;
 `MULP:  wMultiplicationA_Ax = iChannel_Ax; //Az = Ax * Ay
 default:  wMultiplicationA_Ax = iChannel_Ax; // Ax * Bx
 endcase
end
//--------------------------------------------------------------------
 
//assign wMultiplicationA_Ax = iChannel_Ax;
 
assign wMultiplicationA_InputReady
 = (iOperation == `CROSS ||
  iOperation == `DOT ||
  iOperation == `MUL  ||
  iOperation == `IMUL  ||
  iOperation == `MAG ||
  iOperation == `MULP
  ) ? iInputReady : 0;
 
//--------------------------------------------------------------------
always @ ( * )
begin
 case (iOperation)
 `MUL,`IMUL:   wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx
 `MAG:   wMultiplicationA_Bx = iChannel_Ax; //Ax^2
 `DOT:   wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx
 `CROSS:  wMultiplicationA_Bx = iChannel_Bz; // Ay * Bz
 `MULP:  wMultiplicationA_Bx = iChannel_Ay;  //Az = Ax * Ay
 default:  wMultiplicationA_Bx = 32'b0;
 endcase
end
//--------------------------------------------------------------------
 
//------------------------------------------------------
 
reg [`WIDTH-1:0] wMultiplicationB_Ay;
reg [`WIDTH-1:0]  wMultiplicationB_By;
wire [`LONG_WIDTH-1:0] wMultiplicationB_Result;
wire wMultiplicationB_InputReady;
wire wMultiplicationB_OutputReady;
 
 
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_B
(
 
 .Clock( Clock ),
 .Reset( Reset ),
 .A( wMultiplicationB_Ay ),
 .B( wMultiplicationB_By ),
 .R( wMultiplicationB_Result ),
 .iUnscaled( wMultiplcationUnscaled ),
 .iInputReady( wMultiplicationB_InputReady ),
 .OutputReady( wMultiplicationB_OutputReady )
);
 
 
//----------------------------------------------------
 
always @ ( * )
begin
 case (iOperation)
  `CROSS:  wMultiplicationB_Ay = iChannel_Az; // Az * By
  `MAG:  wMultiplicationB_Ay = iChannel_Ay;
  default: wMultiplicationB_Ay = iChannel_Ay; // Ay * By
 endcase
end
//----------------------------------------------------
assign wMultiplicationB_InputReady
 = (iOperation == `CROSS    ||
  iOperation == `DOT ||
  iOperation == `MUL   ||
  iOperation == `IMUL   ||
  iOperation == `MAG ) ? iInputReady : 0;
 
//----------------------------------------------------
always @ ( * )
begin
 case (iOperation)
 `MUL,`IMUL:   wMultiplicationB_By = iChannel_By; //Ay*By
 `MAG:   wMultiplicationB_By = iChannel_Ay; //Ay^2
 `DOT:   wMultiplicationB_By = iChannel_By; //Ay*By
 `CROSS:  wMultiplicationB_By = iChannel_By; // Az * By
 default:  wMultiplicationB_By = 32'b0;
 endcase
end
//----------------------------------------------------
 
//------------------------------------------------------
reg [`WIDTH-1:0] wMultiplicationC_Az;
reg  [`WIDTH-1:0] wMultiplicationC_Bz;
wire [`LONG_WIDTH-1:0] wMultiplicationC_Result;
wire wMultiplicationC_InputReady;
wire wMultiplicationC_OutputReady;
 
 
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_C
(
 
 .Clock( Clock ),
 .Reset( Reset ),
 .A( wMultiplicationC_Az ),
 .B( wMultiplicationC_Bz ),
 .R( wMultiplicationC_Result ),
 .iUnscaled( wMultiplcationUnscaled ),
 .iInputReady( wMultiplicationC_InputReady ),
 .OutputReady( wMultiplicationC_OutputReady )
);
 
 
//----------------------------------------------------
always @ ( * )
begin
 case (iOperation)
  `CROSS:  wMultiplicationC_Az = iChannel_Az;  //Az*Bx
  `MAG:  wMultiplicationC_Az = iChannel_Az;
  default:     wMultiplicationC_Az = iChannel_Az; //Az*Bz
 endcase
end
//----------------------------------------------------
 
assign wMultiplicationC_InputReady
 = (
  iOperation == `CROSS    ||
  iOperation == `DOT ||
  iOperation == `MUL   ||
  iOperation == `IMUL   ||
  iOperation == `MAG
  ) ? iInputReady : 0;
 
//----------------------------------------------------
always @ ( * )
begin
 case (iOperation)
 `MUL,`IMUL:   wMultiplicationC_Bz = iChannel_Bz; //Az*Bz
 `MAG:   wMultiplicationC_Bz = iChannel_Az; //Ay^2
 `DOT:   wMultiplicationC_Bz = iChannel_Bz; //Az*Bz
 `CROSS:  wMultiplicationC_Bz = iChannel_Bx; //Az*Bx
 default:  wMultiplicationC_Bz = 32'b0;
 endcase
end
//---------------------------------------------------- 
 
reg [`WIDTH-1:0] wMultiplicationD_Aw;
reg  [`WIDTH-1:0] wMultiplicationD_Bw;
wire [`LONG_WIDTH-1:0] wMultiplicationD_Result;
wire wMultiplicationD_InputReady;
wire wMultiplicationD_OutputReady;
 
 
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_D
(
 
 .Clock( Clock ),
 .Reset( Reset ),
 .A( wMultiplicationD_Aw ),
 .B( wMultiplicationD_Bw ),
 .R( wMultiplicationD_Result ),
 .iUnscaled( wMultiplcationUnscaled ),
 .iInputReady( wMultiplicationD_InputReady ),
 .OutputReady( wMultiplicationD_OutputReady )
);
 
assign wMultiplicationD_InputReady
 = (iOperation == `CROSS ) ? iInputReady : 0;
 
 
//---------------------------------------------------- 
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationD_Aw = iChannel_Ax; //Ax*Bz
 default:       wMultiplicationD_Aw = 32'b0;
 endcase
end
//---------------------------------------------------- 
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationD_Bw = iChannel_Bz; //Ax*Bz
 default:       wMultiplicationD_Bw = 32'b0;
 endcase
end
//---------------------------------------------------- 
reg [`WIDTH-1:0] wMultiplicationE_Ak;
reg  [`WIDTH-1:0] wMultiplicationE_Bk;
wire [`LONG_WIDTH-1:0] wMultiplicationE_Result;
wire wMultiplicationE_InputReady;
wire wMultiplicationE_OutputReady;
 
 
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_E
(
 
 .Clock( Clock ),
 .Reset( Reset ),
 .A( wMultiplicationE_Ak ),
 .B( wMultiplicationE_Bk ),
 .R( wMultiplicationE_Result ),
 .iUnscaled( wMultiplcationUnscaled ),
 .iInputReady( wMultiplicationE_InputReady ),
 .OutputReady( wMultiplicationE_OutputReady )
);
 
assign wMultiplicationE_InputReady
 = (iOperation == `CROSS ) ? iInputReady : 0;
 
 
//---------------------------------------------------- 
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationE_Ak = iChannel_Ax; //Ax*By
 default:   wMultiplicationE_Ak = 32'b0;
 endcase
end
//---------------------------------------------------- 
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationE_Bk = iChannel_By; //Ax*By
 default:   wMultiplicationE_Bk = 32'b0;
 endcase
end
 
//----------------------------------------------------  
reg [`WIDTH-1:0] wMultiplicationF_Al;
reg  [`WIDTH-1:0] wMultiplicationF_Bl;
wire [`LONG_WIDTH-1:0] wMultiplicationF_Result;
wire wMultiplicationF_InputReady;
wire wMultiplicationF_OutputReady;
 
 
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_F
(
 
 .Clock( Clock ),
 .Reset( Reset ),
 .A( wMultiplicationF_Al ),
 .B( wMultiplicationF_Bl ),
 .R( wMultiplicationF_Result ),
 .iUnscaled( wMultiplcationUnscaled ),
 .iInputReady( wMultiplicationF_InputReady ),
 .OutputReady( wMultiplicationF_OutputReady )
);
assign wMultiplicationF_InputReady
 = (iOperation == `CROSS ) ? iInputReady : 0;
 
 
//---------------------------------------------------- 
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationF_Al = iChannel_Ay; //Ay*Bx
 default:   wMultiplicationF_Al = 32'b0;
 endcase
end
//---------------------------------------------------- 
always @ ( * )
begin
 case (iOperation)
 `CROSS:   wMultiplicationF_Bl = iChannel_Bx; //Ay*Bx
 default:   wMultiplicationF_Bl = 32'b0;
 endcase
end
//------------------------------------------------------
wire [`WIDTH-1:0] wDivisionA_Result;
wire wDivisionA_OutputReady;
wire wDivisionA_InputReady;
 
assign wDivisionA_InputReady =
 ( iOperation == `DIV) ? iInputReady : 0;
 
SignedIntegerDivision DivisionChannel_A
(
.Clock( Clock ),
.Reset( Reset ),
.iDividend( iChannel_Ax ),
.iDivisor(  iChannel_Bx ),
.oQuotient( wDivisionA_Result[`WIDTH-1:0] ),
.iInputReady( wDivisionA_InputReady ),
.OutputReady( wDivisionA_OutputReady )
 
);
//------------------------------------------------------
wire [`WIDTH-1:0] wDivisionB_Result;
wire wDivisionB_OutputReady;
wire wDivisionB_InputReady;
 
assign wDivisionB_InputReady =
 ( iOperation == `DIV) ? iInputReady : 0;
 
SignedIntegerDivision DivisionChannel_B
(
.Clock( Clock ),
.Reset( Reset ),
.iDividend( iChannel_Ay ),
.iDivisor( iChannel_By ),
.oQuotient( wDivisionB_Result[`WIDTH-1:0] ),
.iInputReady( wDivisionB_InputReady ),
.OutputReady( wDivisionB_OutputReady )
 
);
//------------------------------------------------------
wire [`WIDTH-1:0] wDivisionC_Result;
wire wDivisionC_OutputReady;
wire wDivisionC_InputReady;
 
 
assign wDivisionC_InputReady =
 ( iOperation == `DIV) ? iInputReady : 0;
 
SignedIntegerDivision DivisionChannel_C
(
.Clock( Clock ),
.Reset( Reset ),
.iDividend( iChannel_Az ),
.iDivisor( iChannel_Bz ),
.oQuotient( wDivisionC_Result[`WIDTH-1:0] ),
.iInputReady( wDivisionC_InputReady ),
.OutputReady( wDivisionC_OutputReady )
 
);
//--------------------------------------------------------------
/*
 First addtion block instance goes here.
 Note that all inputs/outputs to the block
 are wires. It has two MUXES one for each entry.
*/
reg [`LONG_WIDTH-1:0] wAddSubA_Ax,wAddSubA_Bx;
wire [`LONG_WIDTH-1:0] wAddSubA_Result;
wire wAddSubA_Operation; //Either addition or substraction
reg wAddSubA_InputReady;
wire wAddSubA_OutputReady;
 
assign wAddSubA_Operation
 = (
  iOperation == `SUB
  || iOperation == `CROSS
  || iOperation == `DEC
  || iOperation == `MOD
 ) ? 1 : 0;
 
FixedAddSub AddSubChannel_A
(
.Clock( Clock ),
.Reset( Reset ),
.A( wAddSubA_Ax ),
.B( wAddSubA_Bx ),
.R( wAddSubA_Result ),
.iOperation( wAddSubA_Operation ),
.iInputReady( wAddSubA_InputReady ),
.OutputReady( wAddSubA_OutputReady )
);
//Diego
 
 
//----------------------------
 
//InpuReady Mux A
always @ ( * )
begin
 case (iOperation)
 `ADD:  wAddSubA_InputReady = iInputReady;
 `SUB:  wAddSubA_InputReady = iInputReady;
 `INC,`INCX,`INCY,`INCZ:  wAddSubA_InputReady = iInputReady;
 `DEC:  wAddSubA_InputReady = iInputReady;
 `MOD:  wAddSubA_InputReady = iInputReady;
 
 `MAG:  wAddSubA_InputReady = wMultiplicationOutputReadyA &&
            wMultiplicationOutputReadyB;
          //wMultiplicationA_OutputReady 
          //&& wMultiplicationB_OutputReady;
 
 `DOT:  wAddSubA_InputReady =
           wMultiplicationOutputReadyA &&
           wMultiplicationOutputReadyB;
          //wMultiplicationA_OutputReady 
          //&& wMultiplicationB_OutputReady;
 
 `CROSS: wAddSubA_InputReady =
          wMultiplicationOutputReadyA &&
          wMultiplicationOutputReadyB;
          // wMultiplicationA_OutputReady
          //&& wMultiplicationB_OutputReady;
 
 default: wAddSubA_InputReady = 1'b0;
 endcase
end
//----------------------------
 
//wAddSubA_Bx 2:1 input Mux
always @ ( * )
begin
 case (iOperation)
 
 `ADD:  wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax };
 `SUB:  wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax };
 `INC,`INCX,`INCY,`INCZ:  wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax };
 `DEC:  wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax };
 `MOD:  wAddSubA_Ax = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx };
 
 `MAG:  wAddSubA_Ax = wMultiplicationA_Result;
 `DOT:  wAddSubA_Ax = wMultiplicationA_Result;
 `CROSS: wAddSubA_Ax = wMultiplicationA_Result;
 default: wAddSubA_Ax = 64'b0;
 endcase
end
//----------------------------
//wAddSubA_Bx 2:1 input Mux
always @ ( * )
begin
 case (iOperation)
 `ADD: wAddSubA_Bx = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx };
 `SUB: wAddSubA_Bx = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx };
 `INC,`INCX: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE);
 `INCY,`INCZ: wAddSubA_Bx = `LONG_WIDTH'd0;
 `DEC: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE);
 `MOD: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE);
 
 `MAG:  wAddSubA_Bx = wMultiplicationB_Result;
 `DOT:  wAddSubA_Bx = wMultiplicationB_Result;
 `CROSS: wAddSubA_Bx = wMultiplicationB_Result;
 default: wAddSubA_Bx = 64'b0;
 endcase
end
//--------------------------------------------------------------
/*
 Second addtion block instance goes here.
 Note that all inputs/outputs to the block
 are wires. It has two MUXES one for each entry.
*/
 
wire [`LONG_WIDTH-1:0] wAddSubB_Result;
 
 
wire wAddSubB_Operation; //Either addition or substraction
reg  wAddSubB_InputReady;
wire wAddSubB_OutputReady;
 
reg [`LONG_WIDTH-1:0] wAddSubB_Ay,wAddSubB_By;
 
assign wAddSubB_Operation =
 ( iOperation == `SUB
   || iOperation == `CROSS
   || iOperation == `DEC
   || iOperation == `MOD
   ) ? 1 : 0;
 
FixedAddSub AddSubChannel_B
(
.Clock( Clock ),
.Reset( Reset ),
.A( wAddSubB_Ay ),
.B( wAddSubB_By ),
.R( wAddSubB_Result ),
.iOperation( wAddSubB_Operation ),
.iInputReady( wAddSubB_InputReady ),
.OutputReady( wAddSubB_OutputReady )
);
//----------------------------
wire wMultiplicationOutputReadyC_Dealy1;
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFwMultiplicationOutputReadyC_Dealy1
(
 .Clock( Clock ),
 .Reset( Reset ),
 .Enable(1'b1 ),
 .D( wMultiplicationOutputReadyC ),
 .Q( wMultiplicationOutputReadyC_Dealy1 )
);
 
 
 
 
 
//InpuReady Mux B
always @ ( * )
begin
 case (iOperation)
 `ADD:  wAddSubB_InputReady = iInputReady;
 `SUB:  wAddSubB_InputReady = iInputReady;
 `INC,`INCX,`INCY,`INCZ:  wAddSubB_InputReady = iInputReady;
 `DEC:  wAddSubB_InputReady = iInputReady;
 `MOD:  wAddSubB_InputReady = iInputReady;
 
 `MAG:  wAddSubB_InputReady = wAddSubAOutputReady
           && wMultiplicationOutputReadyC_Dealy1;
          //&& wMultiplicationC_OutputReady;
 
 `DOT:  wAddSubB_InputReady = wAddSubAOutputReady
          && wMultiplicationOutputReadyC_Dealy1;
          //&& wMultiplicationC_OutputReady;
 
 `CROSS: wAddSubB_InputReady = wMultiplicationOutputReadyC &&
            wMultiplicationOutputReadyD;
          // wMultiplicationC_OutputReady
          //&& wMultiplicationD_OutputReady;
 
 default: wAddSubB_InputReady = 1'b0;
 
 endcase
end
//----------------------------
// wAddSubB_Ay 2:1 input Mux
// If the iOperation is ADD or SUB, it will simply take the inputs from
// ALU Channels. If it is a VECTOR_MAGNITUDE, it take the input from the
// previus ADDER_A, same for dot product.
always @ ( * )
begin
 case (iOperation)
 `ADD:  wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay};  //Ay
 `SUB:  wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay};  //Ay
 `INC,`INCX,`INCY,`INCZ:  wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay};  //Ay
 `DEC:  wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay};  //Ay
 `MOD:  wAddSubB_Ay = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_By} : {32'b0,iChannel_By};  //Ay
 `MAG:  wAddSubB_Ay = wAddSubA_Result; //A^2+B^2
 `DOT:  wAddSubB_Ay = wAddSubA_Result;   //Ax*Bx + Ay*By
 `CROSS: wAddSubB_Ay = wMultiplicationC_Result;
 default: wAddSubB_Ay = 64'b0;
 endcase
end
//----------------------------
//wAddSubB_By 2:1 input Mux
always @ ( * )
begin
 case (iOperation)
 `ADD:  wAddSubB_By = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_By } : {32'b0,iChannel_By};    //By
 `SUB:  wAddSubB_By = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_By } : {32'b0,iChannel_By}; //{32'b0,iChannel_By};    //By
 `INC,`INCY:  wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
 `INCX,`INCZ:   wAddSubB_By = `LONG_WIDTH'd0;
 `DEC:  wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
 `MOD:  wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
 `MAG:  wAddSubB_By = wMultiplicationC_Result; //C^2
 `DOT:  wAddSubB_By = wMultiplicationC_Result; //Az * Bz
 `CROSS: wAddSubB_By = wMultiplicationD_Result;
 default: wAddSubB_By = `LONG_WIDTH'b0;
 endcase
end
//--------------------------------------------------------------
wire [`LONG_WIDTH-1:0] wAddSubC_Result;
reg [`LONG_WIDTH-1:0] wAddSubC_Az,wAddSubC_Bz;
 
wire wAddSubC_Operation; //Either addition or substraction
reg wAddSubC_InputReady;
wire wAddSubC_OutputReady;
 
reg [`LONG_WIDTH-1:0] AddSubC_Az,AddSubB_Bz;
 
//-----------------------------------------
always @ ( * )
begin
 case (iOperation)
  `CROSS:  wAddSubC_Az = wMultiplicationE_Result;
  `MOD: wAddSubC_Az = (iChannel_Bz[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Bz} : {32'b0,iChannel_Bz};
  default:     wAddSubC_Az = (iChannel_Az[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Az} : {32'b0,iChannel_Az};
 endcase
end
//-----------------------------------------
always @ ( * )
begin
 case (iOperation)
  `CROSS:  wAddSubC_Bz = wMultiplicationF_Result;
  `INC,`INCZ:  wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE);
  `INCX,`INCY:   wAddSubC_Bz = `LONG_WIDTH'd0;
  `DEC:  wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE);
  `MOD:  wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE);
  default:     wAddSubC_Bz = (iChannel_Bz[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Bz} : {32'b0,iChannel_Bz};
 endcase
end
//-----------------------------------------
 
assign wAddSubC_Operation
 = (
  iOperation == `SUB
  || iOperation == `CROSS
  || iOperation == `DEC
  || iOperation == `MOD
  ) ? 1 : 0;
 
FixedAddSub AddSubChannel_C
(
.Clock( Clock ),
.Reset( Reset ),
.A( wAddSubC_Az ),
.B( wAddSubC_Bz ),
.R( wAddSubC_Result ),
.iOperation( wAddSubC_Operation ),
.iInputReady( wAddSubC_InputReady ),
.OutputReady( wAddSubC_OutputReady )
);
 
 
always @ ( * )
begin
 case (iOperation)
 `CROSS: wAddSubC_InputReady = wMultiplicationE_OutputReady &&
  wMultiplicationF_OutputReady;
 
 default: wAddSubC_InputReady = iInputReady;
 endcase
end
 
//------------------------------------------------------
wire [`WIDTH-1:0] wSquareRoot_Result;
wire wSquareRoot_OutputReady;
 
 
FixedPointSquareRoot SQROOT1
(
 .Clock( Clock ),
 .Reset( Reset ),
 .Operand( wAddSubB_Result ),
 .iInputReady( wAddSubBOutputReady && iOperation == `MAG),
 .OutputReady( wSquareRoot_OutputReady ),
 .Result( wSquareRoot_Result )
);
//------------------------------------------------------
 
assign wModulus2N_ResultA =  ({32'b0,iChannel_Ax}  & wAddSubA_Result );
assign wModulus2N_ResultB =  ({32'b0,iChannel_Ay}  & wAddSubB_Result );
assign wModulus2N_ResultC =  ({32'b0,iChannel_Az}  & wAddSubC_Result );
 
 
 
 
 
 
//&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//
//****Mux for ResultA***
// Notice that the Dot Product or the Magnitud Result will
// output in ResultA.
 
always @ ( *  )
begin
 case ( iOperation )
 `RETURN:    ResultA = iChannel_Ax;
 `ADD:       ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};// & 32'h7FFFFFFF;
 `SUB:       ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};//wAddSubA_Result[31:0];
 `CROSS:    ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};//wAddSubA_Result[31:0];
 `DIV:         ResultA = wDivisionA_Result;
 `MUL:       ResultA = wMultiplicationA_Result[31:0];
 `IMUL:            ResultA = wMultiplicationA_Result[31:0];
 `DOT:     ResultA = (wAddSubB_Result[63] == 1'b1) ? { 1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
 `MAG:     ResultA = wSquareRoot_Result;
 `ZERO:    ResultA = 32'b0;
 `COPY:    ResultA = iChannel_Ax;
 `TMREAD:          ResultA = iTMEMReadData[95:64];
 `LEA:             ResultA = {16'b0,iCurrentIP};
 
 `SWIZZLE3D: ResultA  = wSwizzleOutputX;
 
 //Set Operations
 `UNSCALE:   ResultA  = iChannel_Ax >> `SCALE;
 `RESCALE:   ResultA  = iChannel_Ax << `SCALE;
 `SETX,`RET:    ResultA  = iChannel_Ax;
   `SETY:    ResultA  = iChannel_Bx;
 `SETZ:    ResultA  = iChannel_Bx;
 `INC,`INCX,`INCY,`INCZ:     ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
 `DEC:     ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
 `MOD:     ResultA =  wModulus2N_ResultA[31:0];
 `FRAC:    ResultA = iChannel_Ax & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
 `MULP:      ResultA = iChannel_Ax;
 `NEG:      ResultA = ~iChannel_Ax + 1'b1;
 `XCHANGEX:   ResultA  = iChannel_Bx;
 
 default:
 begin
 `ifdef DEBUG
// $display("%dns ALU: Error Unknown Operation: %d",$time,iOperation);
// $stop();
 `endif
 ResultA =  32'b0;
 end
 endcase
end
//------------------------------------------------------
//****Mux for RB***
always @ ( * )
begin
 case ( iOperation )
 `RETURN:    ResultB = iChannel_Ax;
 `ADD:       ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
 `SUB:       ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; //wAddSubB_Result[31:0];
 `CROSS:    ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
 `DIV:         ResultB = wDivisionB_Result;
 `MUL:       ResultB = wMultiplicationB_Result[31:0];
 `IMUL:            ResultB = wMultiplicationB_Result[31:0];
 `DOT:     ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
 `MAG:     ResultB = wSquareRoot_Result;
 `ZERO:    ResultB = 32'b0;
 `COPY:    ResultB = iChannel_Ay;
 `TMREAD:          ResultB = iTMEMReadData[63:32];
 `LEA:             ResultB = {16'b0,iCurrentIP};
 
 //Set Operations
 `UNSCALE:   ResultB  = iChannel_Ay >> `SCALE;
 `RESCALE:   ResultB  = iChannel_Ay << `SCALE;
 `SETX,`RET:  ResultB  = iChannel_By;  // {Source1[95:64],Source0[63:32],Source0[31:0]}; 
 `SETY:    ResultB  = iChannel_Ax;  // {Source0[95:64],Source1[95:64],Source0[31:0]}; 
 `SETZ:    ResultB  = iChannel_By;  // {Source0[95:64],Source0[63:32],Source1[95:64]}; 
 
 `SWIZZLE3D:   ResultB  = wSwizzleOutputY;
 
 `INC,`INCX,`INCY,`INCZ:       ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
 `DEC:       ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
 `MOD:     ResultB =  wModulus2N_ResultB[31:0];
 `FRAC:    ResultB = iChannel_Ay & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
 `MULP:    ResultB = iChannel_Ay;
 `NEG:     ResultB = ~iChannel_Ay + 1'b1;
 `XCHANGEX:   ResultB = iChannel_Ay;
 
 default:
 begin
 `ifdef DEBUG
 //$display("%dns ALU: Error Unknown Operation: %d",$time,iOperation);
 //$stop();
 `endif
 ResultB =  32'b0;
 end
 endcase
end
//------------------------------------------------------
//****Mux for RC***
always @ ( * )
begin
 case ( iOperation )
 `RETURN:    ResultC = iChannel_Ax;
 `ADD:       ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
 `SUB:       ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];
 `CROSS:    ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]};//wAddSubC_Result[31:0];
 `DIV:         ResultC = wDivisionC_Result;
 `MUL:       ResultC = wMultiplicationC_Result[31:0];
 `IMUL:            ResultC = wMultiplicationC_Result[31:0];
 `DOT:     ResultC = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
 `MAG:     ResultC = wSquareRoot_Result;
 `ZERO:    ResultC = 32'b0;
 `COPY:    ResultC = iChannel_Az;
 `TMREAD:          ResultC = iTMEMReadData[31:0];
 `LEA:             ResultC = {16'b0,iCurrentIP};
 
 `SWIZZLE3D: ResultC  = wSwizzleOutputZ;
 
 //Set Operations
 `UNSCALE:   ResultC  = iChannel_Az >> `SCALE;
 `RESCALE:   ResultC  = iChannel_Az << `SCALE;
 `SETX,`RET:  ResultC  = iChannel_Bz;  // {Source1[95:64],Source0[63:32],Source0[31:0]}; 
 `SETY:    ResultC  = iChannel_Bz;  // {Source0[95:64],Source1[95:64],Source0[31:0]}; 
 `SETZ:    ResultC  = iChannel_Ax;  // {Source0[95:64],Source0[63:32],Source1[95:64]}; 
 
 `INC,`INCX,`INCY,`INCZ:       ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
 `DEC:     ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
 `MOD:     ResultC =  wModulus2N_ResultC[31:0];
 `FRAC:    ResultC = iChannel_Az & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
 `MULP:    ResultC = wMultiplicationA_Result[31:0];
 `NEG:     ResultC = ~iChannel_Az + 1'b1;
 `XCHANGEX:   ResultC = iChannel_Az;
 default:
 begin
 `ifdef DEBUG
 //$display("%dns ALU: Error Unknown Operation: %d",$time,iOperation);
 //$stop();
 `endif
 ResultC =  32'b0;
 end
 endcase
end
//------------------------------------------------------------------------
 
 
always @ ( * )
begin
 case (iOperation)
 `JMP,`CALL,`RET: oBranchTaken = OutputReady;
 `JGX: oBranchTaken = wArithmeticComparison_Result;
 `JGY: oBranchTaken = wArithmeticComparison_Result;
 `JGZ: oBranchTaken = wArithmeticComparison_Result;
 
 `JLX: oBranchTaken = wArithmeticComparison_Result;
 `JLY: oBranchTaken = wArithmeticComparison_Result;
 `JLZ: oBranchTaken = wArithmeticComparison_Result;
 
 `JEQX: oBranchTaken = wArithmeticComparison_Result;
 `JEQY: oBranchTaken = wArithmeticComparison_Result;
 `JEQZ: oBranchTaken = wArithmeticComparison_Result;
 
 `JNEX: oBranchTaken = wArithmeticComparison_Result;
 `JNEY: oBranchTaken = wArithmeticComparison_Result;
 `JNEZ: oBranchTaken = wArithmeticComparison_Result;
 
 `JGEX: oBranchTaken = wArithmeticComparison_Result;
 `JGEY: oBranchTaken = wArithmeticComparison_Result;
 `JGEZ: oBranchTaken = wArithmeticComparison_Result;
 
 `JLEX: oBranchTaken = wArithmeticComparison_Result;
 `JLEY: oBranchTaken = wArithmeticComparison_Result;
 `JLEZ: oBranchTaken = wArithmeticComparison_Result;
 
 default: oBranchTaken = 0;
 endcase
 
end
 
always @ ( * )
begin
 case (iOperation)
 
  `JMP,`CALL,`RET,`JGX,`JGY,`JGZ,`JLX,`JLY,`JLZ,`JEQX,`JEQY,`JEQZ,
  `JNEX,`JNEY,`JNEZ,`JGEX,`JGEY,`JGEZ: oBranchNotTaken = !oBranchTaken && OutputReady;
  `JLEX: oBranchNotTaken = !oBranchTaken && OutputReady;
  `JLEY: oBranchNotTaken = !oBranchTaken && OutputReady;
  `JLEZ: oBranchNotTaken = !oBranchTaken && OutputReady;
 default:
  oBranchNotTaken = 0;
 endcase
end
//------------------------------------------------------------------------
//Output ready logic Stuff for Division...
//Some FFT will hopefully do the trick
 
wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC ;
wire wDivisionOutputReady;
 
 
 
assign wAddSubAOutputReady = wAddSubA_OutputReady;
assign wAddSubBOutputReady = wAddSubB_OutputReady;
assign wAddSubCOutputReady = wAddSubC_OutputReady;
 
wire wDivA_tmp, wDivB_tmp, wDivC_tmp;
UPCOUNTER_POSEDGE # (1) FFT_DivisionA
(
.Clock(Clock),
.Reset(Reset | iInputReady),
.Initial(1'b0),
.Enable(wDivisionA_OutputReady),
.Q(wDivA_tmp)
);
 
assign wDivisionOutputReadyA = ((wDivA_tmp | wDivisionA_OutputReady) & ~iInputReady);
UPCOUNTER_POSEDGE # (1) FFT_DivisionB
(
.Clock(Clock),
.Reset(Reset | iInputReady),
.Initial(1'b0),
.Enable(wDivisionB_OutputReady),
.Q(wDivB_tmp)
);
assign wDivisionOutputReadyB = ((wDivB_tmp | wDivisionB_OutputReady) & ~iInputReady);
 
UPCOUNTER_POSEDGE # (1) FFT_DivisionC
(
.Clock(Clock),
.Reset(Reset | iInputReady),
.Initial(1'b0),
.Enable(wDivisionC_OutputReady),
.Q(wDivC_tmp)
);
assign wDivisionOutputReadyC = ((wDivC_tmp | wDivisionC_OutputReady) & ~iInputReady);
/*
FFT1 FFT_DivisionA
  (
   .D(1'b1),
   .Clock( wDivisionA_OutputReady ),
   .Reset( iInputReady ),
   .Q( wDivisionOutputReadyA )
 );
 
FFT1 FFT_DivisionB
  (
   .D(1'b1),
   .Clock( wDivisionB_OutputReady ),
   .Reset( iInputReady ),
   .Q( wDivisionOutputReadyB )
 );
 
 FFT1 FFT_DivisionC
  (
   .D(1'b1),
   .Clock( wDivisionC_OutputReady ),
   .Reset( iInputReady ),
   .Q( wDivisionOutputReadyC )
 );
 */
 assign wDivisionOutputReady =
 ( wDivisionOutputReadyA && wDivisionOutputReadyB && wDivisionOutputReadyC );
 
assign wMultiplicationOutputReadyA = wMultiplicationA_OutputReady;
assign wMultiplicationOutputReadyB = wMultiplicationB_OutputReady;
assign wMultiplicationOutputReadyC = wMultiplicationC_OutputReady;
assign wMultiplicationOutputReadyD = wMultiplicationD_OutputReady;
 
 assign wMultiplicationOutputReady =
 ( wMultiplicationOutputReadyA && wMultiplicationOutputReadyB && wMultiplicationOutputReadyC );
 
 wire wSquareRootOutputReady;
 FFT1 FFT_Sqrt
  (
   .D(1'b1),
   .Clock( wSquareRoot_OutputReady ),
   .Reset( iInputReady ),
   .Q( wSquareRootOutputReady )
 );
 
 
//------------------------------------------------------------------------
wire wOutputDelay1Cycle,wOutputDelay2Cycle,wOutputDelay3Cycle;
 
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputReadyDelay2
(
 .Clock( Clock ),
 .Reset( Reset ),
 .Enable(1'b1),
 .D( iInputReady ),
 .Q( wOutputDelay1Cycle )
);
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputReadyDelay22
(
 .Clock( Clock  ),
 .Reset( Reset ),
 .Enable(1'b1),
 .D( wOutputDelay1Cycle ),
 .Q( wOutputDelay2Cycle )
);
wire wIsOMWRITE;
assign wIsOMWRITE = (wOperation == `OMWRITE) ? 1'b1: 1'b0;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputReadyDelay222
(
 .Clock( Clock ),
 .Reset( Reset ),
 .Enable(wIsOMWRITE),
 .D( wOutputDelay2Cycle ),
 .Q( wOutputDelay3Cycle )
);
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) SourceZ2
(
 .Clock( Clock ),
 .Reset( Reset ),
 .Enable( iInputReady ),
 .D( iOperation ),
 .Q(wOperation)
);
 
 
//Mux for output ready signal
always @ ( * )
begin
 case ( wOperation )
 `UNSCALE,`RESCALE:   OutputReady  = wOutputDelay1Cycle;
 `RETURN: OutputReady = wOutputDelay1Cycle;
 
 `NOP: OutputReady = wOutputDelay1Cycle;
 `FRAC: OutputReady = wOutputDelay1Cycle;
 `NEG: OutputReady = wOutputDelay1Cycle;
 `OMWRITE: OutputReady = wOutputDelay3Cycle;
 `TMREAD:  OutputReady = wTMReadOutputReady;  //One cycle after TMEM data availale asserted
 
 `ifdef DEBUG
 //Debug Print behaves as a NOP in terms of ALU...
 `DEBUG_PRINT: OutputReady = wOutputDelay1Cycle;
 `endif
 
 `ADD,`INC,`INCX,`INCY,`INCZ:  OutputReady =  wAddSubAOutputReady &&
         wAddSubBOutputReady &&
         wAddSubCOutputReady;
 
 `SUB,`DEC:    OutputReady =  wAddSubAOutputReady &&
         wAddSubBOutputReady &&
         wAddSubCOutputReady;
 
 `DIV:  OutputReady =  wDivisionOutputReady;
 
 
 `MUL,`IMUL:    OutputReady =  wMultiplicationOutputReady;
 `MULP:  OutputReady =  wMultiplicationOutputReadyA;
 
 `DOT:  OutputReady = wAddSubBOutputReady;
 
 `CROSS: OutputReady =  wAddSubAOutputReady &&
         wAddSubBOutputReady &&
         wAddSubCOutputReady;
 
 `MAG:  OutputReady = wSquareRootOutputReady;
 
 `ZERO: OutputReady = wOutputDelay1Cycle;
 
 `COPY: OutputReady = wOutputDelay1Cycle;
 
 `SWIZZLE3D: OutputReady = wOutputDelay1Cycle;
 
 `SETX,`SETY,`SETZ,`JMP,`LEA,`CALL,`RET:  OutputReady = wOutputDelay1Cycle;
 
 
 
 `JGX,`JGY,`JGZ:    OutputReady = ArithmeticComparison_OutputReady;
 `JLX,`JLY,`JLZ:    OutputReady = ArithmeticComparison_OutputReady;
 `JEQX,`JEQY,`JEQZ:   OutputReady = ArithmeticComparison_OutputReady;
 `JNEX,`JNEY,`JNEZ:   OutputReady = ArithmeticComparison_OutputReady;
 `JGEX,`JGEY,`JGEZ:   OutputReady = ArithmeticComparison_OutputReady;
 `JLEX,`JLEY,`JLEZ:   OutputReady = ArithmeticComparison_OutputReady;
 
 `MOD: OutputReady = wAddSubAOutputReady &&    //TODO: wait 1 more cycle
         wAddSubBOutputReady &&
         wAddSubCOutputReady;
 
 `XCHANGEX: OutputReady = wOutputDelay1Cycle;
 
 
 default:
 begin
  OutputReady =  1'b0;
  //`ifdef DEBUG
  //$display("*** ALU ERROR: iOperation = %d ***",iOperation);
  //`endif
 end
 
 endcase
end
 
endmodule
//------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	158	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3	174	diegovalve	`ifdef VERILATOR
4			`include "Module_Swizzle.v"
5			`include "Module_ArithmeticComparison.v"
6			`include "Module_RadixRMul.v"
7			`include "Module_FixedPointDivision.v"
8			`include "Module_FixedPointSquareRoot.v"
9			`endif
10	158	diegovalve	`/**********************************************************************************`
11			`Theia, Ray Cast Programable graphic Processing Unit.`
12			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
13
14			`This program is free software; you can redistribute it and/or`
15			`modify it under the terms of the GNU General Public License`
16			`as published by the Free Software Foundation; either version 2`
17			`of the License, or (at your option) any later version.`
18
19			`This program is distributed in the hope that it will be useful,`
20			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
21			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
22			`GNU General Public License for more details.`
23
24			`You should have received a copy of the GNU General Public License`
25			`along with this program; if not, write to the Free Software`
26			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
27
28			`***********************************************************************************/`
29
30
31
32			`//--------------------------------------------------------------`
33			`module VectorALU`
34			`(`
35	175	diegovalve	`input wire Clock,`
36			`input wire Reset,`
37			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
38			input wire[`WIDTH-1:0] iChannel_Ax,
39			input wire[`WIDTH-1:0] iChannel_Bx,
40			input wire[`WIDTH-1:0] iChannel_Ay,
41			input wire[`WIDTH-1:0] iChannel_By,
42			input wire[`WIDTH-1:0] iChannel_Az,
43			input wire[`WIDTH-1:0] iChannel_Bz,
44			output wire [`WIDTH-1:0] oResultA,
45			output wire [`WIDTH-1:0] oResultB,
46			output wire [`WIDTH-1:0] oResultC,
47			`input wire iInputReady,`
48			`output reg oBranchTaken,`
49			`output reg oBranchNotTaken,`
50			`output reg oReturnFromSub,`
51			input wire [`ROM_ADDRESS_WIDTH-1:0] iCurrentIP,
52
53			`//Connections to the O Memory`
54			output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
55			output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
56			`output wire oOMEM_WriteEnable,`
57			`//Connections to the R Memory`
58			output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
59			input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
60			`input wire iTMEMDataAvailable,`
61			`output wire oTMEMDataRequest,`
62			`output reg OutputReady`
63
64	158	diegovalve	`);`
65
66
67
68
69
70			`wire wMultiplcationUnscaled;`
71			assign wMultiplcationUnscaled = (iOperation == `IMUL) ? 1'b1 : 1'b0;
72
73			`//--------------------------------------------------------------`
74
75	175	diegovalve	`reg [7:0] InputReadyA,InputReadyB,InputReadyC;`
76	158	diegovalve
77			`//------------------------------------------------------`
78			`/*`
79	175	diegovalve	`This is the block that takes care of all tha arithmetic`
80			`comparisons. Supported operations are <,>,<=,>=,==,!=`
81
82	158	diegovalve	`*/`
83			`//------------------------------------------------------`
84			reg [`WIDTH-1:0] wMultiplicationA_Ax;
85			reg [`WIDTH-1:0] wMultiplicationA_Bx;
86			wire [`LONG_WIDTH-1:0] wMultiplicationA_Result;
87			`wire wMultiplicationA_InputReady;`
88			`wire wMultiplicationA_OutputReady;`
89			`wire wMultiplicationOutputReady, wMultiplicationOutputReadyA,`
90			`wMultiplicationOutputReadyB,wMultiplicationOutputReadyC,wMultiplicationOutputReadyD;`
91
92			`wire wAddSubAOutputReady,wAddSubBOutputReady,wAddSubCOutputReady;`
93			wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation;
94			wire [`WIDTH-1:0] wSwizzleOutputX,wSwizzleOutputY,wSwizzleOutputZ;
95
96			`//--------------------------------------------------------------------`
97			reg [`WIDTH-1:0] ResultA,ResultB,ResultC;
98
99			`//Output Flip Flops,`
100			`//This flip flop will control the outputs so that the`
101			`//values of the outputs change ONLY when when there is`
102			`//a positive edge of OutputReady`
103
104			`FFD32_POSEDGE ResultAFFD`
105			`(`
106	175	diegovalve	`.Clock( OutputReady ),`
107			`.D( ResultA ),`
108			`.Q( oResultA )`
109	158	diegovalve	`);`
110
111			`FFD32_POSEDGE ResultBFFD`
112			`(`
113	175	diegovalve	`.Clock( OutputReady ),`
114			`.D( ResultB ),`
115			`.Q( oResultB )`
116	158	diegovalve	`);`
117
118			`FFD32_POSEDGE ResultCFFD`
119			`(`
120	175	diegovalve	`.Clock( OutputReady ),`
121			`.D( ResultC ),`
122			`.Q( oResultC )`
123	158	diegovalve	`);`
124			`//--------------------------------------------------------------------`
125
126
127
128			`Swizzle3D Swizzle1`
129			`(`
130	175	diegovalve	`.Source0_X( iChannel_Bx ),`
131			`.Source0_Y( iChannel_By ),`
132			`.Source0_Z( iChannel_Bz ),`
133			`.iOperation( iChannel_Ax ),`
134
135			`.SwizzleX( wSwizzleOutputX ),`
136			`.SwizzleY( wSwizzleOutputY ),`
137			`.SwizzleZ( wSwizzleOutputZ )`
138	158	diegovalve	`);`
139			`//---------------------------------------------------------------------`
140			wire [`LONG_WIDTH-1:0] wModulus2N_ResultA,wModulus2N_ResultB,wModulus2N_ResultC;
141
142			`//---------------------------------------------------------------------(`
143
144			`wire IOW_Operation,wOMEM_We;`
145			assign IOW_Operation = (iOperation == `OMWRITE);
146
147			`always @ ( * )`
148			`begin`
149	175	diegovalve	if (iOperation == `RET)
150			`oReturnFromSub = OutputReady;`
151			`else`
152			`oReturnFromSub = 1'b0;`
153	158	diegovalve
154			`end`
155
156			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_AWE`
157			`(`
158	175	diegovalve	`.Clock( Clock ),`
159			`.Reset( Reset),`
160			`.Enable( 1'b1 ),`
161			`.D( IOW_Operation ),`
162			`.Q( wOMEM_We )`
163	158	diegovalve	`);`
164
165			`assign oOMEM_WriteEnable = wOMEM_We & IOW_Operation;`
166
167			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD1_A
168			`(`
169	175	diegovalve	`.Clock( Clock ),`
170			`.Reset( Reset),`
171			`.Enable( iInputReady ),`
172			`.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ),`
173			`.Q( oOMEMWriteAddress)`
174	158	diegovalve	`);`
175			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B
176			`(`
177	175	diegovalve	`.Clock( Clock ),`
178			`.Reset( Reset),`
179			`.Enable( iInputReady ),`
180			`.D( {iChannel_Bx,iChannel_By,iChannel_Bz} ),`
181			`.Q( oOMEMWriteData )`
182	158	diegovalve	`);`
183
184
185
186			`wire wTMReadOutputReady;`
187			`assign wTMReadOutputReady = iTMEMDataAvailable;`
188			`/*`
189			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE`
190			`(`
191	175	diegovalve	`.Clock( Clock ),`
192			`.Reset( Reset),`
193			`.Enable( 1'b1 ),`
194			`.D( iTMEMDataAvailable ),`
195			`.Q( wTMReadOutputReady )`
196	158	diegovalve	`);`
197			`*/`
198			`//assign oTMEMReadAddress = {iChannel_Ax,iChannel_Ay,iChannel_Az};`
199
200			`//We wait 1 clock cycle before be send the data read request, because`
201			`//we need to lathc the values at the output`
202
203			`wire wOpTRead;`
204			assign wOpTRead = ( iOperation == `TMREAD ) ? 1'b1 : 1'b0;
205			`wire wTMEMRequest;`
206			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE123`
207			`(`
208	175	diegovalve	`.Clock( Clock ),`
209			`.Reset( Reset),`
210			`.Enable( 1'b1 ),`
211			`.D( wOpTRead ),`
212			`.Q( wTMEMRequest )`
213	158	diegovalve	`);`
214			`assign oTMEMDataRequest = wTMEMRequest & wOpTRead;`
215			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B445
216			`(`
217	175	diegovalve	`.Clock( Clock ),`
218			`.Reset( Reset),`
219			`.Enable( iInputReady & wOpTRead ),`
220			`.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ),`
221			`.Q( oTMEMReadAddress )`
222	158	diegovalve	`);`
223
224			`/*`
225	175	diegovalve	`This MUX will select the apropiated X,Y or Z depending on`
226			`wheter it is XYZ iOperation. This gets defined by the bits 3 and 4`
227			`of iOperation, and only applies for oBranchTaken and Store operations.`
228	158	diegovalve	`*/`
229
230	175	diegovalve	`wire wArithmeticComparison_Result;`
231			`wire ArithmeticComparison_InputReady;`
232			`wire ArithmeticComparison_OutputReady;`
233			reg[`WIDTH-1:0] ArithmeticComparison_A,ArithmeticComparison_B;
234	158	diegovalve
235
236			`always @ ( * )`
237			`begin`
238	175	diegovalve	`case ( {iOperation[4],iOperation[3]} )`
239			`2'b01: ArithmeticComparison_A = iChannel_Ax;`
240			`2'b10: ArithmeticComparison_A = iChannel_Ay;`
241			`2'b11: ArithmeticComparison_A = iChannel_Az;`
242			`default: ArithmeticComparison_A = 0; //Should never happen`
243			`endcase`
244	158	diegovalve	`end`
245			`//---------------------------------------------------------------------`
246			`always @ ( * )`
247			`begin`
248	175	diegovalve	`case ( {iOperation[4],iOperation[3]} )`
249			`2'b01: ArithmeticComparison_B = iChannel_Bx;`
250			`2'b10: ArithmeticComparison_B = iChannel_By;`
251			`2'b11: ArithmeticComparison_B = iChannel_Bz;`
252			`default: ArithmeticComparison_B = 0; //Should never happen`
253			`endcase`
254	158	diegovalve	`end`
255
256			`//---------------------------------------------------------------------`
257			`/*`
258	175	diegovalve	`The onbly instance of Aritmetic comparison in the ALU,`
259			`ArithmeticComparison operations matches the 3 LSB of`
260			`Global ALU iOperation for oBranchTaken Instruction family`
261	158	diegovalve	`*/`
262
263			`assign ArithmeticComparison_InputReady = iInputReady;`
264
265			`wire wArithmeticComparisonResult;`
266
267			`ArithmeticComparison ArithmeticComparison_1`
268			`(`
269	175	diegovalve	`.Clock( Clock ),`
270			`.X( ArithmeticComparison_A ),`
271			`.Y( ArithmeticComparison_B ),`
272			`.iOperation( iOperation[2:0] ),`
273			`.iInputReady( ArithmeticComparison_InputReady ),`
274			`.OutputReady( ArithmeticComparison_OutputReady ),`
275			`.Result( wArithmeticComparisonResult )`
276	158	diegovalve	`);`
277
278
279			`assign wArithmeticComparison_Result = wArithmeticComparisonResult && OutputReady;`
280			`//--------------------------------------------------------------------`
281			`RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_A`
282			`(`
283
284	175	diegovalve	`.Clock( Clock ),`
285			`.Reset( Reset ),`
286			`.A( wMultiplicationA_Ax ),`
287			`.B( wMultiplicationA_Bx ),`
288			`.R( wMultiplicationA_Result ),`
289			`.iUnscaled( wMultiplcationUnscaled ),`
290			`.iInputReady( wMultiplicationA_InputReady ),`
291			`.OutputReady( wMultiplicationA_OutputReady )`
292	158	diegovalve	`);`
293
294			`//--------------------------------------------------------------------`
295			`always @ ( * )`
296			`begin`
297	175	diegovalve	`case (iOperation)`
298			`CROSS: wMultiplicationA_Ax = iChannel_Ay; // Ay * Bz
299			`MAG: wMultiplicationA_Ax = iChannel_Ax;
300			`MULP: wMultiplicationA_Ax = iChannel_Ax; //Az = Ax * Ay
301			`default: wMultiplicationA_Ax = iChannel_Ax; // Ax * Bx`
302			`endcase`
303	158	diegovalve	`end`
304			`//--------------------------------------------------------------------`
305
306			`//assign wMultiplicationA_Ax = iChannel_Ax;`
307
308			`assign wMultiplicationA_InputReady`
309	175	diegovalve	= (iOperation == `CROSS \|\|
310			iOperation == `DOT \|\|
311			iOperation == `MUL \|\|
312			iOperation == `IMUL \|\|
313			iOperation == `MAG \|\|
314			iOperation == `MULP
315			`) ? iInputReady : 0;`
316
317	158	diegovalve	`//--------------------------------------------------------------------`
318			`always @ ( * )`
319			`begin`
320	175	diegovalve	`case (iOperation)`
321			`MUL,`IMUL: wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx
322			`MAG: wMultiplicationA_Bx = iChannel_Ax; //Ax^2
323			`DOT: wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx
324			`CROSS: wMultiplicationA_Bx = iChannel_Bz; // Ay * Bz
325			`MULP: wMultiplicationA_Bx = iChannel_Ay; //Az = Ax * Ay
326			`default: wMultiplicationA_Bx = 32'b0;`
327			`endcase`
328	158	diegovalve	`end`
329			`//--------------------------------------------------------------------`
330
331			`//------------------------------------------------------`
332
333			reg [`WIDTH-1:0] wMultiplicationB_Ay;
334			reg [`WIDTH-1:0] wMultiplicationB_By;
335			wire [`LONG_WIDTH-1:0] wMultiplicationB_Result;
336			`wire wMultiplicationB_InputReady;`
337			`wire wMultiplicationB_OutputReady;`
338
339
340			`RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_B`
341			`(`
342
343	175	diegovalve	`.Clock( Clock ),`
344			`.Reset( Reset ),`
345			`.A( wMultiplicationB_Ay ),`
346			`.B( wMultiplicationB_By ),`
347			`.R( wMultiplicationB_Result ),`
348			`.iUnscaled( wMultiplcationUnscaled ),`
349			`.iInputReady( wMultiplicationB_InputReady ),`
350			`.OutputReady( wMultiplicationB_OutputReady )`
351	158	diegovalve	`);`
352
353
354			`//----------------------------------------------------`
355
356			`always @ ( * )`
357			`begin`
358	175	diegovalve	`case (iOperation)`
359			`CROSS: wMultiplicationB_Ay = iChannel_Az; // Az * By
360			`MAG: wMultiplicationB_Ay = iChannel_Ay;
361			`default: wMultiplicationB_Ay = iChannel_Ay; // Ay * By`
362			`endcase`
363	158	diegovalve	`end`
364			`//----------------------------------------------------`
365			`assign wMultiplicationB_InputReady`
366	175	diegovalve	= (iOperation == `CROSS \|\|
367			iOperation == `DOT \|\|
368			iOperation == `MUL \|\|
369			iOperation == `IMUL \|\|
370			iOperation == `MAG ) ? iInputReady : 0;
371
372	158	diegovalve	`//----------------------------------------------------`
373			`always @ ( * )`
374			`begin`
375	175	diegovalve	`case (iOperation)`
376			`MUL,`IMUL: wMultiplicationB_By = iChannel_By; //Ay*By
377			`MAG: wMultiplicationB_By = iChannel_Ay; //Ay^2
378			`DOT: wMultiplicationB_By = iChannel_By; //Ay*By
379			`CROSS: wMultiplicationB_By = iChannel_By; // Az * By
380			`default: wMultiplicationB_By = 32'b0;`
381			`endcase`
382	158	diegovalve	`end`
383			`//----------------------------------------------------`
384	175	diegovalve
385	158	diegovalve	`//------------------------------------------------------`
386			reg [`WIDTH-1:0] wMultiplicationC_Az;
387			reg [`WIDTH-1:0] wMultiplicationC_Bz;
388			wire [`LONG_WIDTH-1:0] wMultiplicationC_Result;
389			`wire wMultiplicationC_InputReady;`
390			`wire wMultiplicationC_OutputReady;`
391
392
393			`RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_C`
394			`(`
395
396	175	diegovalve	`.Clock( Clock ),`
397			`.Reset( Reset ),`
398			`.A( wMultiplicationC_Az ),`
399			`.B( wMultiplicationC_Bz ),`
400			`.R( wMultiplicationC_Result ),`
401			`.iUnscaled( wMultiplcationUnscaled ),`
402			`.iInputReady( wMultiplicationC_InputReady ),`
403			`.OutputReady( wMultiplicationC_OutputReady )`
404	158	diegovalve	`);`
405
406
407			`//----------------------------------------------------`
408			`always @ ( * )`
409			`begin`
410	175	diegovalve	`case (iOperation)`
411			`CROSS: wMultiplicationC_Az = iChannel_Az; //Az*Bx
412			`MAG: wMultiplicationC_Az = iChannel_Az;
413			`default: wMultiplicationC_Az = iChannel_Az; //Az*Bz`
414			`endcase`
415	158	diegovalve	`end`
416			`//----------------------------------------------------`
417
418			`assign wMultiplicationC_InputReady`
419	175	diegovalve	`= (`
420			iOperation == `CROSS \|\|
421			iOperation == `DOT \|\|
422			iOperation == `MUL \|\|
423			iOperation == `IMUL \|\|
424			iOperation == `MAG
425			`) ? iInputReady : 0;`
426
427	158	diegovalve	`//----------------------------------------------------`
428			`always @ ( * )`
429			`begin`
430	175	diegovalve	`case (iOperation)`
431			`MUL,`IMUL: wMultiplicationC_Bz = iChannel_Bz; //Az*Bz
432			`MAG: wMultiplicationC_Bz = iChannel_Az; //Ay^2
433			`DOT: wMultiplicationC_Bz = iChannel_Bz; //Az*Bz
434			`CROSS: wMultiplicationC_Bz = iChannel_Bx; //Az*Bx
435			`default: wMultiplicationC_Bz = 32'b0;`
436			`endcase`
437	158	diegovalve	`end`
438	175	diegovalve	`//----------------------------------------------------`
439	158	diegovalve
440			reg [`WIDTH-1:0] wMultiplicationD_Aw;
441			reg [`WIDTH-1:0] wMultiplicationD_Bw;
442			wire [`LONG_WIDTH-1:0] wMultiplicationD_Result;
443			`wire wMultiplicationD_InputReady;`
444			`wire wMultiplicationD_OutputReady;`
445
446
447			`RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_D`
448			`(`
449
450	175	diegovalve	`.Clock( Clock ),`
451			`.Reset( Reset ),`
452			`.A( wMultiplicationD_Aw ),`
453			`.B( wMultiplicationD_Bw ),`
454			`.R( wMultiplicationD_Result ),`
455			`.iUnscaled( wMultiplcationUnscaled ),`
456			`.iInputReady( wMultiplicationD_InputReady ),`
457			`.OutputReady( wMultiplicationD_OutputReady )`
458	158	diegovalve	`);`
459
460			`assign wMultiplicationD_InputReady`
461	175	diegovalve	= (iOperation == `CROSS ) ? iInputReady : 0;
462	158	diegovalve
463
464	175	diegovalve	`//----------------------------------------------------`
465	158	diegovalve	`always @ ( * )`
466			`begin`
467	175	diegovalve	`case (iOperation)`
468			`CROSS: wMultiplicationD_Aw = iChannel_Ax; //Ax*Bz
469			`default: wMultiplicationD_Aw = 32'b0;`
470			`endcase`
471	158	diegovalve	`end`
472	175	diegovalve	`//----------------------------------------------------`
473	158	diegovalve	`always @ ( * )`
474			`begin`
475	175	diegovalve	`case (iOperation)`
476			`CROSS: wMultiplicationD_Bw = iChannel_Bz; //Ax*Bz
477			`default: wMultiplicationD_Bw = 32'b0;`
478			`endcase`
479	158	diegovalve	`end`
480	175	diegovalve	`//----------------------------------------------------`
481	158	diegovalve	reg [`WIDTH-1:0] wMultiplicationE_Ak;
482			reg [`WIDTH-1:0] wMultiplicationE_Bk;
483			wire [`LONG_WIDTH-1:0] wMultiplicationE_Result;
484			`wire wMultiplicationE_InputReady;`
485			`wire wMultiplicationE_OutputReady;`
486
487
488			`RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_E`
489			`(`
490
491	175	diegovalve	`.Clock( Clock ),`
492			`.Reset( Reset ),`
493			`.A( wMultiplicationE_Ak ),`
494			`.B( wMultiplicationE_Bk ),`
495			`.R( wMultiplicationE_Result ),`
496			`.iUnscaled( wMultiplcationUnscaled ),`
497			`.iInputReady( wMultiplicationE_InputReady ),`
498			`.OutputReady( wMultiplicationE_OutputReady )`
499	158	diegovalve	`);`
500

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