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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [top.v] - Blame information for rev 178

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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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***********************************************************************************/
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/*******************************************************************************
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Module Description:
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This is the top module that connects the GPU with the HOST and the HUB/SWITCH.
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*******************************************************************************/
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`ifdef VERILATOR
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`include "Theia.v"
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`endif
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module top
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(
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input wire                        Clock,
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input wire                        Reset,
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input wire                        iHostEnable,
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output wire[`WB_WIDTH-1:0]        oHostReadAddress,
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input wire[`WB_WIDTH-1:0]         iMemorySize,
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output wire[1:0]                  oMemSelect,
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input wire [`WB_WIDTH-1:0]        iInstruction,
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input wire [`WB_WIDTH-1:0]        iParameter,
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input wire [`WB_WIDTH-1:0]        iVertex,
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input wire [`WB_WIDTH-1:0]        iControlRegister,
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input wire[`WIDTH-1:0]            iPrimitiveCount,
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input wire [`WB_WIDTH-1:0]        iTMEMAdr,
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input wire [`WB_WIDTH-1:0]        iTMEMData,
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input wire                        iTMEM_WE,
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input wire [`MAX_TMEM_BANKS-1:0]  iTMEM_Sel,
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input wire  [`MAX_CORE_BITS-1:0]  iOMEMBankSelect,
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input  wire [`WB_WIDTH-1:0]       iOMEMReadAddress,
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output wire [`WB_WIDTH-1:0]       oOMEMData,   //Output data bus (Wishbone)
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`ifndef NO_DISPLAY_STATS
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        input wire [`WIDTH-1:0] iWidth,iHeight,
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`endif
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output wire                       oDone
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);
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wire wHost_2__RenderDone;
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assign oDone = wHost_2__RenderDone;
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assign oMemSelect =  wMemSelect;
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 wire [`WB_WIDTH-1:0]       wHost_2__DAT_O;
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 reg                        wHost_2__ACK;
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 wire                       wGPU_2__ACK;
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 wire [`WB_WIDTH-1:0]       ADR_I,wHost_2__ADR_O;
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 wire                       WE_I,STB_I;
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 wire [1:0]                 wHost_2__TGA_O;
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 wire [1:0]                 TGA_I;
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 wire [`MAX_CORES-1:0]      wCoreSelect;
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 wire                       wHost_2__MST_O;
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 wire                       wGPU_2_HOST_Done;
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 wire [`MAX_CORES-1:0]      wHost_2__RENDREN_O;
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 wire                       wGPU_2__HOST_HDL;
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 wire                       wHost_2__WE_O;
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 wire                       wHost_2__STDONE;
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 wire                       wGPUCommitedResults;
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 wire                       wHostDataAvailable;
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 wire                       wHost_2__CYC_O,wHost_2__GACK_O,TGC_O,wHost_2__STB_O;
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//assign oDone = wGPU_2_HOST_Done;
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THEIA GPU
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  (
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  .CLK_I(     Clock              ),
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  .RST_I(     Reset              ),
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  .RENDREN_I( wHost_2__RENDREN_O ),
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  .DAT_I(     wHost_2__DAT_O     ),
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  .ACK_I(     wHost_2__ACK       ),
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  .CYC_I(     wHost_2__CYC_O     ),
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  .MST_I(     wHost_2__MST_O     ),
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  .TGA_I(     wHost_2__TGA_O     ),
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  .ACK_O(     wGPU_2__ACK        ),
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  .ADR_I(     wHost_2__ADR_O     ),
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  .WE_I(      wHost_2__WE_O      ),
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  .SEL_I(     wCoreSelect        ),
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  .STB_I(     wHost_2__STB_O     ),
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  //O-Memory
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  .OMBSEL_I(  iOMEMBankSelect  ),
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  .OMADR_I(   iOMEMReadAddress ),
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  .OMEM_O(    oOMEMData        ),
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  //T-Memory
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  .TMDAT_I(   iTMEMData        ),
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  .TMADR_I(   iTMEMAdr         ),
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  .TMWE_I(    iTMEM_WE         ),
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  .TMSEL_I(   iTMEM_Sel        ),
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  .HDL_O(     wGPU_2__HOST_HDL    ),
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  .HDLACK_I(  wHost_2__GACK_O     ),
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  .STDONE_I(  wHost_2__STDONE     ),
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  .RCOMMIT_O( wGPUCommitedResults ),
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  .HDA_I(     wHostDataAvailable  ),
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  .CREG_I(    iControlRegister[15:0]    ),
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  .DONE_O(    wGPU_2_HOST_Done    )
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 );
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wire[1:0] wMemSelect;
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wire[`WB_WIDTH-1:0] wHostReadData;
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX1
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 (
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.Sel( wMemSelect    ),
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.I1(  iInstruction  ),
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.I2(  iParameter    ),
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.I3(  iVertex       ),
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.I4(  0             ),
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.O1(  wHostReadData )
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 );
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Module_Host HOST
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(
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 .Clock(                  Clock                ),
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 .Reset(                  Reset                ),
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 .iEnable(                iHostEnable          ),
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 .oHostDataAvailable(     wHostDataAvailable   ),
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 .iHostDataReadConfirmed( wGPU_2__HOST_HDL     ),
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 .iMemorySize(            iMemorySize          ),
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 .iPrimitiveCount(        iPrimitiveCount      ),
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 .iGPUCommitedResults(    wGPUCommitedResults  ),
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 .STDONE_O(               wHost_2__STDONE      ),
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 .iGPUDone(               wGPU_2_HOST_Done     ),
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 .oRenderDone(            wHost_2__RenderDone  ),
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 .iWidth(iWidth),
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 .iHeight(iHeight),
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 //To Memory
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.oReadAddress( oHostReadAddress ),
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.iReadData(    wHostReadData ),
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 //To Hub/Switch
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.oCoreSelectMask( wCoreSelect        ),
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.oMemSelect(      wMemSelect         ),
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.DAT_O(           wHost_2__DAT_O     ),
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.ADR_O(           wHost_2__ADR_O     ),
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.TGA_O(           wHost_2__TGA_O     ),
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.RENDREN_O(       wHost_2__RENDREN_O ),
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.CYC_O(           wHost_2__CYC_O     ),
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.STB_O(           wHost_2__STB_O     ),
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.MST_O(           wHost_2__MST_O     ),
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.GRDY_I(          wGPU_2__HOST_HDL   ),
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.GACK_O(          wHost_2__GACK_O    ),
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.WE_O(            wHost_2__WE_O      ),
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.ACK_I(           wGPU_2__ACK        )
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);
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endmodule

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