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diegovalve |
`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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module RegisterFile # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH )
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(
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input wire Clock,
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input wire Reset,
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input wire [ADDR_WIDTH-1:0] iReadAddress0,
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input wire [ADDR_WIDTH-1:0] iReadAddress1,
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input wire [2:0] iWriteEnable,
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input wire [ADDR_WIDTH-1:0] iWriteAddress,
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input wire [DATA_WIDTH-1:0] iData,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oFrameOffset,
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output wire [DATA_WIDTH-1:0] oData0,
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output wire [DATA_WIDTH-1:0] oData1
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);
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parameter DATA_CHANNEL_WIDTH = DATA_WIDTH / 3;
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wire wEnableFrameOffsetOverwrite;
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assign wEnableFrameOffsetOverwrite = (iWriteAddress == `SPR_CONTROL) ? 1'b1 : 1'b0;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) FDD_FRAMEOFFSET
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( Clock, Reset, (wEnableFrameOffsetOverwrite & iWriteEnable[2]) ,iData[`X_RNG], oFrameOffset );
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RAM_DUAL_READ_PORT # ( DATA_CHANNEL_WIDTH, ADDR_WIDTH ) RF_X
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(
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.Clock( Clock ),
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.iWriteEnable( iWriteEnable[2] ),
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.iReadAddress0( iReadAddress0 ),
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.iReadAddress1( iReadAddress1 ),
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.iWriteAddress( iWriteAddress ),
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.iDataIn( iData[`X_RNG] ),
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.oDataOut0( oData0[`X_RNG] ),
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.oDataOut1( oData1[`X_RNG] )
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);
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RAM_DUAL_READ_PORT # ( DATA_CHANNEL_WIDTH, ADDR_WIDTH ) RF_Y
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(
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.Clock( Clock ),
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.iWriteEnable( iWriteEnable[1] ),
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.iReadAddress0( iReadAddress0 ),
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.iReadAddress1( iReadAddress1 ),
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.iWriteAddress( iWriteAddress ),
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.iDataIn( iData[`Y_RNG] ),
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.oDataOut0( oData0[`Y_RNG] ),
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.oDataOut1( oData1[`Y_RNG] )
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);
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RAM_DUAL_READ_PORT # ( DATA_CHANNEL_WIDTH, ADDR_WIDTH ) RF_Z
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(
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.Clock( Clock ),
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.iWriteEnable( iWriteEnable[0] ),
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.iReadAddress0( iReadAddress0 ),
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.iReadAddress1( iReadAddress1 ),
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.iWriteAddress( iWriteAddress ),
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.iDataIn( iData[`Z_RNG] ),
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.oDataOut0( oData0[`Z_RNG] ),
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.oDataOut1( oData1[`Z_RNG] )
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);
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endmodule
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