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[/] [theia_gpu/] [branches/] [new_alu/] [src/] [Module_ReservationStation.v] - Blame information for rev 209

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`include "aDefinitions.v"
 
module ReservationStation
(
        input wire                                                Clock,
        input wire                                                Reset,
        input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
        input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
        input wire [3:0]                                          iMyId,
        input wire                                                iExecutionDone,
        input wire                                                iCommitGranted,
        input wire [`DATA_ROW_WIDTH-1:0]                          iResult,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource1,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource0,
        output wire [`DATA_ADDRESS_WIDTH-1:0]                     oDestination,
        output wire [`DATA_ROW_WIDTH-1:0]                         oResult,
        output wire [2:0]                                         oWE,
        output wire [3:0]                                         oId,
        output wire                                               oBusy,
        output wire                                               oTrigger,
        output wire                                               oCommitRequest
 
);
 
wire                                wStall;
wire                                wLatchRequest;
wire [3:0]                          wSource1_RS;
wire [3:0]                          wSource0_RS;
wire [3:0]                          wMyId;
wire                                wTrigger;
//wire                                wFIFO_Pop;
 
wire [`MOD_ISSUE_PACKET_SIZE-1:0]   wIssue_Latched;
wire [`DATA_ADDRESS_WIDTH-1:0]      wDestination;
wire [3:0]                          wID;
wire [2:0]                          wWE;
wire                                wCommitFifoFull;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
 
 
//assign wFIFO_Pop = iExecutionDone;
assign oCommitRequest = iExecutionDone;
assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
//If there are no dependencies then just trigger execution
//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
assign oTrigger = ( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
 
assign wStall = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
 
wire wLatchData0FromCommitBus;
wire wLatchData1FromCommitBus;
 
 
assign wLatchData0FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
assign wLatchData1FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
 
wire wBusy;
assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
wire wCommitGrantedDelay;
 
UPCOUNTER_POSEDGE # ( 1 ) BUSY
(
        .Clock(    Clock                       ),
        .Reset(    Reset                       ),
        .Enable(   wLatchRequest |  iCommitGranted        ),
        .Initial( 1'b0   ),
        .Q(        wBusy                        )
);
 
 
 
 
 
assign oSource1 =  (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
assign oSource0 =  (wLatchData1FromCommitBus) ? (/*(wDstZero)?`DATA_ROW_WIDTH'b0:*/iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
 
 
wire [`DATA_ROW_WIDTH-1:0]                    wSrc1,wSrc0;
//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
//(     Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
 
wire [3:0] wScale;
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
(       Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
 
sync_fifo  # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
(
 .clk(   Clock          ),
 .reset( Reset          ),
 .din(   {wID,wWE,wDestination,iResult}     ),
 .wr_en( iExecutionDone ),
 .rd_en( iCommitGranted ),
 .dout(  {oId,oWE,oDestination,oResult}        ),
 .full(  wCommitFifoFull          )
 
);
 
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
(       Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
 
*/
endmodule
 
//-------------------------------------------------------------------------------------------------
module ReservationStation_1Cycle
(
        input wire                                                Clock,
        input wire                                                Reset,
        input wire [`MOD_ISSUE_PACKET_SIZE-1:0]                   iIssueBus,
        input wire [`MOD_COMMIT_PACKET_SIZE-1:0]                  iCommitBus,
        input wire [3:0]                                          iMyId,
        input wire                                                iExecutionDone,
        input wire                                                iCommitGranted,
        input wire [`DATA_ROW_WIDTH-1:0]                          iResult,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource1,
        output wire [`DATA_ROW_WIDTH-1:0]                         oSource0,
        output wire [`DATA_ADDRESS_WIDTH-1:0]                     oDestination,
        output wire [`DATA_ROW_WIDTH-1:0]                         oResult,
        output wire [`SCALE_SIZE-1:0]                             oScale,
        output wire [2:0]                                         oWE,
        output wire [3:0]                                         oId,
        output wire                                               oBusy,
        output wire                                               oTrigger,
        output wire                                               oCommitRequest
 
);
 
 
wire [3:0]                          wSource1_RS;
wire [3:0]                          wSource0_RS;
wire [3:0]                          wMyId;
wire                                wTrigger;
wire [`DATA_ADDRESS_WIDTH-1:0]      wDestination;
wire [3:0]                          wID;
wire [2:0]                          wWE;
wire [`DATA_ROW_WIDTH-1:0]          wSrc1,wSrc0,wResult;
//wire                                wDstZero;
wire [`DATA_ROW_WIDTH-1:0]          wSrc1_Fwd;
wire [`DATA_ROW_WIDTH-1:0]          wSrc0_Fwd;
 
wire wSrc0_Dependency_Initial, wSrc0_Dependency;
wire wSrc1_Dependency_Initial, wSrc1_Dependency;
wire wSrc0_DependencyResolved, wSrc0_DependencyLatch;
wire wSrc1_DependencyResolved, wSrc1_DependencyLatch;
wire wWaitingDependency;
wire wHandleCurrentIssue;
wire wDependencyResolved;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
wire wSrc0_DependencyLatch_Pre,wSrc1_DependencyLatch_Pre;
 
assign wHandleCurrentIssue = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
assign wSrc0_Dependency_Initial     = wHandleCurrentIssue & (iIssueBus[96] | iIssueBus[97] | iIssueBus[98] | iIssueBus[99]);
assign wSrc1_Dependency_Initial     = wHandleCurrentIssue & (iIssueBus[196] | iIssueBus[197] | iIssueBus[198] | iIssueBus[199]);
 
 
assign oTrigger =
         (~wWaitingDependency & wHandleCurrentIssue & ~wSrc0_Dependency_Initial & ~wSrc1_Dependency_Initial)
        |(wWaitingDependency  & ~wSrc1_Dependency  &  wSrc0_Dependency  & wSrc0_DependencyResolved )
        |(wWaitingDependency  &  wSrc1_Dependency &  ~wSrc0_Dependency  & wSrc1_DependencyResolved )
        |(wWaitingDependency  &  wSrc1_Dependency  &  wSrc0_Dependency  & wSrc1_DependencyResolved & wSrc0_DependencyResolved );
 
assign wDependencyResolved = wWaitingDependency & ~wSrc1_Dependency & ~wSrc0_Dependency;
 
assign wSrc0_DependencyLatch_Pre = ( wSrc0_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag0)  ) ? 1'b1 : 1'b0;
assign wSrc1_DependencyLatch_Pre = ( wSrc1_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag1)  ) ? 1'b1 : 1'b0;
 
PULSE P1 (      Clock,Reset, 1'b1, wSrc0_DependencyLatch_Pre, wSrc0_DependencyLatch);
PULSE P2 (      Clock,Reset, 1'b1, wSrc1_DependencyLatch_Pre, wSrc1_DependencyLatch);
 
wire wWaitingForCommitGranted;
UPCOUNTER_POSEDGE # ( 1 ) FFD_101
( Clock, Reset,  1'b0, (oBusy & (iCommitGranted ^ wDependencyResolved)  ), wWaitingForCommitGranted );
 
UPCOUNTER_POSEDGE # ( 1 ) FFD_10
( Clock, Reset,  1'b0, wSrc0_DependencyLatch | wDependencyResolved, wSrc0_DependencyResolved );
 
UPCOUNTER_POSEDGE # ( 1 ) FFD_11
( Clock, Reset,  1'b0, wSrc1_DependencyLatch | wDependencyResolved,  wSrc1_DependencyResolved );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP0
( Clock, Reset, wSrc1_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc1_Fwd );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP1
( Clock, Reset, wSrc0_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc0_Fwd );
 
 
//assign oBusy = wWaitingDependency;
UPCOUNTER_POSEDGE # ( 1 ) BUSY
(
        .Clock(    Clock                                                                           ),
        .Reset(    Reset                                                                           ),
        .Enable(   wSrc0_Dependency_Initial | wSrc1_Dependency_Initial |   ((wWaitingForCommitGranted|wDependencyResolved)/*WaitingDependency*/ & iCommitGranted)     ),//***
        .Initial( 1'b0                                                                             ),
        .Q(        oBusy                                                              )
);
 
wire wCommitRequest;
UPCOUNTER_POSEDGE # ( 1 ) CRQ
(
        .Clock(    Clock                                                                           ),
        .Reset(    Reset                                                                           ),
        .Enable(   oTrigger |  iCommitGranted ),
        .Initial( 1'b0                                                                             ),
        .Q(        wCommitRequest                                                              )
);
assign oCommitRequest = oTrigger | (wCommitRequest & ~iCommitGranted);
 
assign oResult      = iResult;
assign oSource1    = (wWaitingDependency) ? ((wSrc1_Dependency)? (wSrc1_Fwd):wSrc1) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
assign oSource0    = (wWaitingDependency) ? ((wSrc0_Dependency)? (wSrc0_Fwd):wSrc0) : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
 
UPCOUNTER_POSEDGE # ( 1 ) DEP
(
        .Clock(    Clock                                                                           ),
        .Reset(    Reset                                                                           ),
        .Enable(   wSrc0_Dependency_Initial | wSrc1_Dependency_Initial |  wDependencyResolved      ),//***
        .Initial( 1'b0                                                                             ),
        .Q(        wWaitingDependency                                                              )
);
 
UPCOUNTER_POSEDGE # ( 1 ) DEPA
(
        .Clock(    Clock                                                     ),
        .Reset(    Reset                                                     ),
        .Enable(   wSrc0_Dependency_Initial |  wSrc0_DependencyResolved      ),
        .Initial(  1'b0                                                      ),
        .Q(        wSrc0_Dependency                                          )
);
 
UPCOUNTER_POSEDGE # ( 1 ) DEPB
(
        .Clock(    Clock                                                     ),
        .Reset(    Reset                                                     ),
        .Enable(   wSrc1_Dependency_Initial |  wSrc1_DependencyResolved      ),
        .Initial(  1'b0                                                      ),
        .Q(        wSrc1_Dependency                                          )
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
(       Clock, Reset, wHandleCurrentIssue , iIssueBus, {oId,oDestination,oWE,oScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
 
endmodule
 
//-------------------------------------------------------------------------------------------------

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[/] [theia_gpu/] [branches/] [new_alu/] [src/] [Module_ReservationStation.v] - Blame information for rev 209

Line No.	Rev	Author	Line
1	209	diegovalve	`include "aDefinitions.v"
2
3			`module ReservationStation`
4			`(`
5			`input wire Clock,`
6			`input wire Reset,`
7			input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
8			input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
9			`input wire [3:0] iMyId,`
10			`input wire iExecutionDone,`
11			`input wire iCommitGranted,`
12			input wire [`DATA_ROW_WIDTH-1:0] iResult,
13			output wire [`DATA_ROW_WIDTH-1:0] oSource1,
14			output wire [`DATA_ROW_WIDTH-1:0] oSource0,
15			output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
16			output wire [`DATA_ROW_WIDTH-1:0] oResult,
17			`output wire [2:0] oWE,`
18			`output wire [3:0] oId,`
19			`output wire oBusy,`
20			`output wire oTrigger,`
21			`output wire oCommitRequest`
22
23			`);`
24
25			`wire wStall;`
26			`wire wLatchRequest;`
27			`wire [3:0] wSource1_RS;`
28			`wire [3:0] wSource0_RS;`
29			`wire [3:0] wMyId;`
30			`wire wTrigger;`
31			`//wire wFIFO_Pop;`
32
33			wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
34			wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
35			`wire [3:0] wID;`
36			`wire [2:0] wWE;`
37			`wire wCommitFifoFull;`
38			wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
39
40
41			`//assign wFIFO_Pop = iExecutionDone;`
42			`assign oCommitRequest = iExecutionDone;`
43			assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
44			`//If there are no dependencies then just trigger execution`
45			//assign oTrigger = (wTrigger /&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)/ ) ? 1'b1 : 0;
46			`assign oTrigger = ( (wLatchRequest \| wLatchData0FromCommitBus \| wLatchData1FromCommitBus) & ~wStall);`
47
48			assign wStall = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 \|\| iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
49			`//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;`
50
51			`wire wLatchData0FromCommitBus;`
52			`wire wLatchData1FromCommitBus;`
53
54
55			assign wLatchData0FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
56			assign wLatchData1FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
57
58			`wire wBusy;`
59			`assign oBusy = wBusy \| wCommitFifoFull & ~iCommitGranted;`
60			`wire wCommitGrantedDelay;`
61
62			`UPCOUNTER_POSEDGE # ( 1 ) BUSY`
63			`(`
64			`.Clock( Clock ),`
65			`.Reset( Reset ),`
66			`.Enable( wLatchRequest \| iCommitGranted ),`
67			`.Initial( 1'b0 ),`
68			`.Q( wBusy )`
69			`);`
70
71
72
73
74
75			assign oSource1 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
76			assign oSource0 = (wLatchData1FromCommitBus) ? (/(wDstZero)?`DATA_ROW_WIDTH'b0:/iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
77			`assign wTrigger = ( wLatchRequest \| wLatchData0FromCommitBus \| wLatchData1FromCommitBus);`
78
79
80			wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
81			//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
82			`//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );`
83
84			`wire [3:0] wScale;`
85			FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
86			`( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );`
87
88			assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
89			assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
90
91			sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
92			`(`
93			`.clk( Clock ),`
94			`.reset( Reset ),`
95			`.din( {wID,wWE,wDestination,iResult} ),`
96			`.wr_en( iExecutionDone ),`
97			`.rd_en( iCommitGranted ),`
98			`.dout( {oId,oWE,oDestination,oResult} ),`
99			`.full( wCommitFifoFull )`
100
101			`);`
102
103			`/*`
104			`FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger`
105			`( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );`
106
107			`*/`
108			`endmodule`
109
110			`//-------------------------------------------------------------------------------------------------`
111			`module ReservationStation_1Cycle`
112			`(`
113			`input wire Clock,`
114			`input wire Reset,`
115			input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
116			input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
117			`input wire [3:0] iMyId,`
118			`input wire iExecutionDone,`
119			`input wire iCommitGranted,`
120			input wire [`DATA_ROW_WIDTH-1:0] iResult,
121			output wire [`DATA_ROW_WIDTH-1:0] oSource1,
122			output wire [`DATA_ROW_WIDTH-1:0] oSource0,
123			output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
124			output wire [`DATA_ROW_WIDTH-1:0] oResult,
125			output wire [`SCALE_SIZE-1:0] oScale,
126			`output wire [2:0] oWE,`
127			`output wire [3:0] oId,`
128			`output wire oBusy,`
129			`output wire oTrigger,`
130			`output wire oCommitRequest`
131
132			`);`
133
134
135			`wire [3:0] wSource1_RS;`
136			`wire [3:0] wSource0_RS;`
137			`wire [3:0] wMyId;`
138			`wire wTrigger;`
139			wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
140			`wire [3:0] wID;`
141			`wire [2:0] wWE;`
142			wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0,wResult;
143			`//wire wDstZero;`
144			wire [`DATA_ROW_WIDTH-1:0] wSrc1_Fwd;
145			wire [`DATA_ROW_WIDTH-1:0] wSrc0_Fwd;
146
147			`wire wSrc0_Dependency_Initial, wSrc0_Dependency;`
148			`wire wSrc1_Dependency_Initial, wSrc1_Dependency;`
149			`wire wSrc0_DependencyResolved, wSrc0_DependencyLatch;`
150			`wire wSrc1_DependencyResolved, wSrc1_DependencyLatch;`
151			`wire wWaitingDependency;`
152			`wire wHandleCurrentIssue;`
153			`wire wDependencyResolved;`
154			wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
155			`wire wSrc0_DependencyLatch_Pre,wSrc1_DependencyLatch_Pre;`
156
157			assign wHandleCurrentIssue = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
158			`assign wSrc0_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[96] \| iIssueBus[97] \| iIssueBus[98] \| iIssueBus[99]);`
159			`assign wSrc1_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[196] \| iIssueBus[197] \| iIssueBus[198] \| iIssueBus[199]);`
160
161
162			`assign oTrigger =`
163			`(~wWaitingDependency & wHandleCurrentIssue & ~wSrc0_Dependency_Initial & ~wSrc1_Dependency_Initial)`
164			`\|(wWaitingDependency & ~wSrc1_Dependency & wSrc0_Dependency & wSrc0_DependencyResolved )`
165			`\|(wWaitingDependency & wSrc1_Dependency & ~wSrc0_Dependency & wSrc1_DependencyResolved )`
166			`\|(wWaitingDependency & wSrc1_Dependency & wSrc0_Dependency & wSrc1_DependencyResolved & wSrc0_DependencyResolved );`
167
168			`assign wDependencyResolved = wWaitingDependency & ~wSrc1_Dependency & ~wSrc0_Dependency;`
169
170			assign wSrc0_DependencyLatch_Pre = ( wSrc0_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag0) ) ? 1'b1 : 1'b0;
171			assign wSrc1_DependencyLatch_Pre = ( wSrc1_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag1) ) ? 1'b1 : 1'b0;
172
173			`PULSE P1 ( Clock,Reset, 1'b1, wSrc0_DependencyLatch_Pre, wSrc0_DependencyLatch);`
174			`PULSE P2 ( Clock,Reset, 1'b1, wSrc1_DependencyLatch_Pre, wSrc1_DependencyLatch);`
175
176			`wire wWaitingForCommitGranted;`
177			`UPCOUNTER_POSEDGE # ( 1 ) FFD_101`
178			`( Clock, Reset, 1'b0, (oBusy & (iCommitGranted ^ wDependencyResolved) ), wWaitingForCommitGranted );`
179
180			`UPCOUNTER_POSEDGE # ( 1 ) FFD_10`
181			`( Clock, Reset, 1'b0, wSrc0_DependencyLatch \| wDependencyResolved, wSrc0_DependencyResolved );`
182
183			`UPCOUNTER_POSEDGE # ( 1 ) FFD_11`
184			`( Clock, Reset, 1'b0, wSrc1_DependencyLatch \| wDependencyResolved, wSrc1_DependencyResolved );`
185
186			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP0
187			( Clock, Reset, wSrc1_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc1_Fwd );
188
189			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP1
190			( Clock, Reset, wSrc0_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc0_Fwd );
191
192
193			`//assign oBusy = wWaitingDependency;`
194			`UPCOUNTER_POSEDGE # ( 1 ) BUSY`
195			`(`
196			`.Clock( Clock ),`
197			`.Reset( Reset ),`
198			`.Enable( wSrc0_Dependency_Initial \| wSrc1_Dependency_Initial \| ((wWaitingForCommitGranted\|wDependencyResolved)/WaitingDependency/ & iCommitGranted) ),//***`
199			`.Initial( 1'b0 ),`
200			`.Q( oBusy )`
201			`);`
202
203			`wire wCommitRequest;`
204			`UPCOUNTER_POSEDGE # ( 1 ) CRQ`
205			`(`
206			`.Clock( Clock ),`
207			`.Reset( Reset ),`
208			`.Enable( oTrigger \| iCommitGranted ),`
209			`.Initial( 1'b0 ),`
210			`.Q( wCommitRequest )`
211			`);`
212			`assign oCommitRequest = oTrigger \| (wCommitRequest & ~iCommitGranted);`
213
214			`assign oResult = iResult;`
215			assign oSource1 = (wWaitingDependency) ? ((wSrc1_Dependency)? (wSrc1_Fwd):wSrc1) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
216			assign oSource0 = (wWaitingDependency) ? ((wSrc0_Dependency)? (wSrc0_Fwd):wSrc0) : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
217
218			`UPCOUNTER_POSEDGE # ( 1 ) DEP`
219			`(`
220			`.Clock( Clock ),`
221			`.Reset( Reset ),`
222			`.Enable( wSrc0_Dependency_Initial \| wSrc1_Dependency_Initial \| wDependencyResolved ),//***`
223			`.Initial( 1'b0 ),`
224			`.Q( wWaitingDependency )`
225			`);`
226
227			`UPCOUNTER_POSEDGE # ( 1 ) DEPA`
228			`(`
229			`.Clock( Clock ),`
230			`.Reset( Reset ),`
231			`.Enable( wSrc0_Dependency_Initial \| wSrc0_DependencyResolved ),`
232			`.Initial( 1'b0 ),`
233			`.Q( wSrc0_Dependency )`
234			`);`
235
236			`UPCOUNTER_POSEDGE # ( 1 ) DEPB`
237			`(`
238			`.Clock( Clock ),`
239			`.Reset( Reset ),`
240			`.Enable( wSrc1_Dependency_Initial \| wSrc1_DependencyResolved ),`
241			`.Initial( 1'b0 ),`
242			`.Q( wSrc1_Dependency )`
243			`);`
244
245
246			FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
247			`( Clock, Reset, wHandleCurrentIssue , iIssueBus, {oId,oDestination,oWE,oScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );`
248
249			assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
250			assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
251
252			`endmodule`
253
254			`//-------------------------------------------------------------------------------------------------`