OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [new_compiler/] [Instruction.cpp] - Blame information for rev 228

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 200 diegovalve
 
2
/**********************************************************************************
3
Theia, Ray Cast Programable graphic Processing Unit.
4
Copyright (C) 2012  Diego Valverde (diego.valverde.g@gmail.com)
5
 
6
This program is free software; you can redistribute it and/or
7
modify it under the terms of the GNU General Public License
8
as published by the Free Software Foundation; either version 2
9
of the License, or (at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19
 
20
***********************************************************************************/
21
 
22
 
23
#include "Instruction.h"
24
#include <sstream>
25
#include <iostream>
26
#include <iomanip>
27
//----------------------------------------------------------------
28
#define OP_SIZE        16            
29
 
30
#define OP_RNG         63,48         
31
#define OP_BIT_IMM     15
32
#define OP_SCALE_RNG   14,11
33
#define OP_EOF         10
34
#define OP_BRANCH      9
35
#define OP_BTYPE_RNG   8,6
36
 
37
#define OP_CODE_RNG    2,0
38
 
39
#define DST_ADDR            7,0
40
#define DST_WE_RNG      10,8
41
#define DST_WE_Z        8
42
#define DST_WE_Y        9
43
#define DST_WE_X        10
44
 
45
#define DST_ZERO            13
46
#define SRC1_DISPLACED      12
47
#define SRC0_DISPLACED      11
48
 
49
#define DST_RNG             47,34
50
#define SCR1_RNG            33,17
51
#define SRC0_RNG            16,0
52
// Source0 structure
53
#define SRC0_SIZE           17
54
#define SRC0_RNG            16,0
55
#define SRC0_ADDR_SIZE      8
56
#define SRC0_SIGN_RNG       16,14
57
#define SRC0_SIGN_X         16
58
#define SRC0_SIGN_Y         15
59
#define SRC0_SIGN_Z         14
60
#define SRC0_SWZX_RNG       13,8  
61
#define SRC0_SWZ_X          13,12  
62
#define SRC0_SWZ_Y          11,10
63
#define SRC0_SWZ_Z          9,8
64
#define SRC0_ADDR_RNG       7,0
65
// Source1 structure 
66
#define SRC1_SIZE           17
67
#define SRC1_RNG            33,17
68
#define SRC1_ADDR_SIZE      8
69
#define SRC1_SIGN_RNG       16,14
70
#define SRC1_SIGN_X         16
71
#define SRC1_SIGN_Y         15
72
#define SRC1_SIGN_Z         14
73
#define SRC1_SWZX_RNG       13,8
74
#define SRC1_SWZ_X          13,12  
75
#define SRC1_SWZ_Y          11,10
76
#define SRC1_SWZ_Z          9,8
77
#define SRC1_ADDR_RNG       7,0
78
 
79
 
80
std::string gOperationStrings[] =
81
{
82
        "NOP",
83
        "ADD",
84
        "DIV",
85
        "MUL",
86
        "SQRT"
87
};
88
 
89
std::string gBranchTypeStrings[] =
90
{
91
"ALWAYS",
92
"ZERO",
93
"NOT_ZERO",
94
"SIGN",
95
"NOT_SIGN",
96
"ZERO_OR_SIGN",
97
"ZERO_OR_NOT_SIGN"
98
};
99
 
100
std::string gSwizzleXTypeStrings[] =
101
{
102
"x",
103
"z",
104
"y"
105
};
106
 
107
std::string gSwizzleYTypeStrings[] =
108
{
109
"y",
110
"z",
111
"x"
112
};
113
 
114
std::string gSwizzleZTypeStrings[] =
115
{
116
"z",
117
"y",
118
"x"
119
};
120
 
121
//--------------------------------------------------------------
122
template <std::size_t N >
123
inline void SetbitRange( std::bitset<N> & aBitset , unsigned int aEnd, unsigned int aStart, unsigned int aValue)
124
{
125
        unsigned long mask = 1;
126
        unsigned long result = 0;
127
        for (int i = aStart; i <= aEnd; ++i)
128
        {
129
                aBitset[i] =  ( mask & aValue );
130
                mask <<= 1;
131
        }
132
 
133
}
134
//--------------------------------------------------------------
135
template <std::size_t N >
136
inline unsigned int GetbitRange( std::bitset<N> & aBitset , unsigned int aEnd, unsigned int aStart)
137
{
138
 
139
        unsigned long Result = 0;
140
        int j = 0;
141
        for (int i = aStart; i <= aEnd; ++i)
142
        {
143
                Result |=  ( aBitset[i] << j++);
144
 
145
        }
146
 
147
        return Result;
148
 
149
}
150
//--------------------------------------------------------------
151
const char lookuparrbin2hex[] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};
152
 
153
char convert_bin2hex(std::string bits)
154
{
155
        unsigned int result = 0;
156
        unsigned int shifter0 = 0;
157
        unsigned int shifter1 = 1;
158
 
159
        for(int n=0; n < bits.length(); n++)
160
        {
161
                result <<= 1; //shift result to the left by 1
162
                if(bits[n] == '1') result = (result | shifter1);
163
                else result = (result | shifter0);
164
        }
165
        return lookuparrbin2hex[result];
166
}
167
//--------------------------------------------------------------
168
 
169
std::string BinStringToHexString(std::string aBinString )
170
{
171
        std::string endresult = "";
172
        for(int i = 0; i < aBinString.length(); i = i+4)
173
        {
174
                endresult += convert_bin2hex(aBinString.substr(i,4));
175
        }
176
        return endresult;
177
}
178
 
179
//--------------------------------------------------------------
180
Instruction::Instruction()
181
{
182
mDestinationIsSymbol = false;
183
mSourceLine = -1;
184
}
185
//--------------------------------------------------------------
186
Instruction::~Instruction()
187
{
188
 
189
}
190
//--------------------------------------------------------------
191
void Instruction::SetFields( unsigned int aOperation, unsigned int aDestination, unsigned int aSrc1, unsigned int aSrc0 )
192
{
193
        SetbitRange<16>(mOperation,16,0,aOperation);
194
        SetbitRange<14>(mDestination,14,0,aDestination);
195
        SetbitRange<17>(mSource1,17,0,aSrc1);
196
        SetbitRange<17>(mSource0,17,0,aSrc0);
197
}
198
//--------------------------------------------------------------
199
void Instruction::Clear()
200
{
201
        mOperation.reset();
202
        mDestination.reset();
203
        mSource1.reset();
204
        mSource0.reset();
205
        mComment.clear();
206
        mDestinationIsSymbol = false;
207
        mSourceLine = -1;
208
}
209
//--------------------------------------------------------------
210
std::string Instruction::PrintHex()
211
{
212
        std::string  I;
213
        if (mDestinationIsSymbol)
214
        {
215
                I = PrintBin();
216
        } else
217
                I =  BinStringToHexString( PrintBin() );
218
        //mOutputFile << I << "\n";
219
        return I;
220
 
221
}
222
//--------------------------------------------------------------
223
std::string Instruction::PrintAssembly()
224
{
225
 
226
        unsigned int Scale = GetbitRange<16>(mOperation,OP_SCALE_RNG);
227
        std::bitset<4> bScale( Scale );
228
 
229
        std::ostringstream oss,oss2;
230
 
231
        oss << std::hex << mOperation.to_ulong() << " ";
232
        if (mDestinationIsSymbol)
233
                oss << mDestinationSymbol;
234
        else
235
                oss << mDestination.to_ulong();
236
 
237
        oss << " " << mSource1.to_ulong() << " " << mSource0.to_ulong();
238
 
239
        std::string tmpString = oss.str();
240
        while (tmpString.size() < 50) tmpString.push_back(' ');
241
 
242
        oss2 << tmpString << "//";
243
 
244
        oss2 << mOperationString << " ";
245
        if (mOperation[OP_BRANCH])
246
        {
247
 
248
                oss2 << "<BRANCH." << gBranchTypeStrings[ GetbitRange<16>(mOperation,OP_BTYPE_RNG) ] << "> ";
249
        }
250
 
251
        if (mDestinationIsSymbol)
252
                oss2 << mDestinationSymbol;
253
        else
254
        {
255
                if (bScale[2] && bScale[3])
256
                        oss2 << "(unscaled) ";
257
                else if (bScale[2])
258
                        oss2 << "(scaled) ";
259
 
260
                if (mOperation[OP_BIT_IMM])
261
                {
262
                        if (mDestination[SRC0_DISPLACED])
263
                                oss2 << ((mOperation[OP_BRANCH])?"@*R[":"R[") <<  GetbitRange<14>(mDestination,DST_ADDR) << "+ offset]";
264
                        else
265
                                oss2 << ((mOperation[OP_BRANCH])?"@*R":"R") <<  GetbitRange<14>(mDestination,DST_ADDR);
266
                }
267
                else
268
                {
269
                        if (mDestination[DST_ZERO])
270
                                oss2 << ((mOperation[OP_BRANCH])?"@[":"R[") <<  GetbitRange<14>(mDestination,DST_ADDR) << "+ offset]";
271
                        else
272
                                oss2 << ((mOperation[OP_BRANCH])?"@":"R") <<  GetbitRange<14>(mDestination,DST_ADDR);
273
                }
274
        }
275
        //Now print the write channels
276
        oss2 << ".";
277
        if (mDestination[DST_WE_X])
278
                oss2 << "x";
279
        else
280
                oss2 << "_";
281
 
282
        if (mDestination[DST_WE_Y])
283
                oss2 << "y";
284
        else
285
                oss2 << "_";
286
 
287
        if (mDestination[DST_WE_Z])
288
                oss2 << "z";
289
        else
290
                oss2 << "_";
291
 
292
        oss2 << " ";
293
 
294
        if (mOperation[OP_BIT_IMM])
295
        {
296
                oss2 << std::hex << (mSource0.to_ulong() + (mSource1.to_ulong() << 17));
297
        } else {
298
 
299
 
300
                if (bScale[0] && bScale[3])
301
                        oss2 << "(unscaled) ";
302
                else if (bScale[0])
303
                        oss2 << "(scaled) ";
304
 
305
 
306
                oss2 << "R";
307
                if (mDestination[SRC1_DISPLACED])
308
                        oss2 << "[" << GetbitRange<17>(mSource1,SRC1_ADDR_RNG) << " + offset]";
309
                else
310
                        oss2 << GetbitRange<17>(mSource1,SRC1_ADDR_RNG);
311
 
312
                oss2 << "."
313
 
314
                << ((mSource1[SRC1_SIGN_X]) ? "-":"") << gSwizzleXTypeStrings[ GetbitRange<17>(mSource1,SRC1_SWZ_X) ]
315
                << ((mSource1[SRC1_SIGN_Y]) ? "-":"") <<gSwizzleYTypeStrings[ GetbitRange<17>(mSource1,SRC1_SWZ_Y) ]
316
                << ((mSource1[SRC1_SIGN_Z]) ? "-":"") <<gSwizzleZTypeStrings[ GetbitRange<17>(mSource1,SRC1_SWZ_Z) ] << " ";
317
 
318
 
319
                if (bScale[1] && bScale[3])
320
                        oss2 << "(unscaled) ";
321
                else if (bScale[1])
322
                        oss2 << "(scaled) ";
323
 
324
                oss2 << "R";
325
                if (mDestination[SRC0_DISPLACED])
326
                        oss2 << "[" << GetbitRange<17>(mSource0,SRC0_ADDR_RNG) << " + offset]";
327
                else
328
                        oss2 << GetbitRange<17>(mSource0,SRC0_ADDR_RNG);
329
 
330
                oss2 << "."
331
 
332
                << ((mSource0[SRC0_SIGN_X]) ? "-":"") << gSwizzleXTypeStrings[ GetbitRange<17>(mSource0,SRC0_SWZ_X) ]
333
                << ((mSource0[SRC0_SIGN_Y]) ? "-":"") << gSwizzleYTypeStrings[ GetbitRange<17>(mSource0,SRC0_SWZ_Y) ]
334
                << ((mSource0[SRC0_SIGN_Z]) ? "-":"") << gSwizzleZTypeStrings[ GetbitRange<17>(mSource0,SRC0_SWZ_Z) ];
335
        }
336
 
337
 
338
        return oss2.str();
339
}
340
//--------------------------------------------------------------
341
void Instruction::PrintFields()
342
{
343
        if (mOperation[OP_BRANCH])
344
        {
345
                //std::cout << "BRANCH to " << mDestination.to_ulong() << "\n";
346
        }
347
        //std::cout << "Imm      :" << mOperation[OP_BIT_IMM] << "\n";
348
        //std::cout << "Branch   :" << mOperation[OP_BRANCH] << "\n";
349
        //std::cout << "WE.x     :" << mDestination[DST_WE_X] << "\n";
350
        //std::cout << "WE.y     :" << mDestination[DST_WE_Y] << "\n";
351
        //std::cout << "WE.z     :" << mDestination[DST_WE_Z] << "\n";
352
        //std::cout << "EOF      :" << mOperation[OP_EOF] << "\n";
353
 
354
        //std::cout << "OP       :" << mOperation.to_string() << "\n";
355
        //if (mDestinationIsSymbol)
356
                //std::cout << "DST      :" << mDestinationSymbol << "\n";
357
        //else
358
                //std::cout << "DST      :" << mDestination.to_string() << "\n";
359
        //std::cout << "SRC1     :" << mSource1.to_string() << "\n";
360
        //std::cout << "SRC0     :" << mSource0.to_string() << "\n";
361
}
362
//--------------------------------------------------------------
363
std::string Instruction::PrintBin()
364
{
365
 
366
        std::bitset<64> Bitset;
367
 
368
 
369
        SetbitRange<64>(Bitset,OP_RNG,mOperation.to_ulong());
370
        SetbitRange<64>(Bitset,DST_RNG,mDestination.to_ulong());
371
        SetbitRange<64>(Bitset,SRC1_RNG,mSource1.to_ulong());
372
        SetbitRange<64>(Bitset,SRC0_RNG,mSource0.to_ulong());
373
        return Bitset.to_string();
374
 
375
}
376
//--------------------------------------------------------------
377
void Instruction::SetEofFlag( bool aEof )
378
{
379
        mOperation[ OP_EOF ] = aEof;
380
}
381
//--------------------------------------------------------------
382
void Instruction::SetCode( EOPERATION aCode )
383
{
384
        SetbitRange<16>(mOperation,OP_CODE_RNG,aCode);
385
        mOperationString = gOperationStrings[aCode];
386
}
387
//--------------------------------------------------------------
388
void Instruction::SetImm( unsigned int aLiteral )
389
{
390
 
391
 
392
        mOperation[OP_BIT_IMM] = true;
393
        mSource0 = aLiteral;
394
        mSource1 = (aLiteral >> SOURCE0_SIZE);
395
}
396
//--------------------------------------------------------------
397
/*void SetAddressingMode( EADDRESSINGTYPE aAddressMode )
398
{
399
        std::bitset<4> AddressingMode( aAddressMode );
400
        AddressingMode[3] = mOperation[OP_BIT_IMM] ;
401
 
402
        switch ( AddressingMode )
403
        {
404
                case EDIRECT_ADDRESSING:
405
                        SetDestZero( false );
406
                        SetSrc1Displace( false );
407
                        SetSrc0Displace( false );
408
                        break;
409
                case EDIRECT_DISP_SRC0:
410
                        SetDestZero( false );
411
                        SetSrc1Displace( false );
412
                        SetSrc0Displace( true );
413
                        break;
414
                EDIRECT_DISP_SRC1:
415
                        SetDestZero( false );
416
                        SetSrc1Displace( true );
417
                        SetSrc0Displace( false );
418
                        break;
419
                EDIRECT_DISP_SRC1_SRC0:
420
                        SetDestZero( false );
421
                        SetSrc1Displace( true );
422
                        SetSrc0Displace( true );
423
                        break;
424
                EDIRECT_DISP_DST:
425
                        SetDestZero( true );
426
                        SetSrc1Displace( false );
427
                        SetSrc0Displace( false );
428
                        break;
429
                EDIRECT_DISP_DST_SRC0:
430
                        SetDestZero( true );
431
                        SetSrc1Displace( false );
432
                        SetSrc0Displace( true );
433
                        break;
434
                case EDIRECT_DISP_DST_SRC1:
435
                        SetDestZero( true );
436
                        SetSrc1Displace( true );
437
                        SetSrc0Displace( false );
438
                        break;
439
                case EDIRECT_DISP_DST_SRC1_SRC0:
440
                        SetDestZero( true );
441
                        SetSrc1Displace( true );
442
                        SetSrc0Displace( true );
443
                        break;
444
                EDIRECT_IMM:                            //R[DSTINDEX ] = IMMV op R[DSTINDEX]
445
                        SetDestZero( false );
446
                        SetSrc1Displace( false );
447
                        SetSrc0Displace( false );
448
                        break;
449
                EDIRECT_IMM_ZERO:                       //R[DSTINDEX ] = IMMV op 32'b0
450
                        SetDestZero( true );
451
                        SetSrc1Displace( false );
452
                        SetSrc0Displace( false );
453
                        break;
454
                EDIRECT_IMM_DISPALCE:           //R[DSTINDEX + offset] = IMMV op R[DSTINDEX]
455
                        SetDestZero( false );
456
                        SetSrc1Displace( false );
457
                        SetSrc0Displace( true );
458
                        break;
459
                EDIRECT_IMM_DISPALCE_ZERO: //R[DSTINDEX + offset] = IMMV op 32'b0
460
                        SetDestZero( true );
461
                        SetSrc1Displace( false );
462
                        SetSrc0Displace( true );
463
                        break;
464
                EINDIRECT_IMM_DISP:             // DST = R[ DSTINDEX ] + OFFSET
465
                        SetDestZero( false );
466
                        SetSrc1Displace( false );
467
                        SetSrc0Displace( false );
468
                        break;
469
                break;
470
                EINDIRECT_IMM_DISP_ZERO:
471
                break;
472
                EINDIRECT_NO_IMM:
473
                break;
474
                EINDIRECT_NO_IMM_DISP:
475
                break;
476
        }
477
}*/
478
//--------------------------------------------------------------
479
void Instruction::SetDestZero(  bool aZero )
480
{
481
        mDestination[DST_ZERO] = aZero;
482
}
483
//--------------------------------------------------------------
484
void Instruction::SetSrc0Displace( bool aDisplace )
485
{
486
        mDestination[SRC0_DISPLACED] = aDisplace;
487
}
488
//--------------------------------------------------------------
489
void Instruction::SetSrc1Displace( bool aDisplace )
490
{
491
        mDestination[SRC1_DISPLACED] = aDisplace;
492
}
493
//--------------------------------------------------------------
494
void Instruction::SetBranchFlag( bool aBranch )
495
{
496
        mOperation[OP_BRANCH] = aBranch;
497
}
498
//--------------------------------------------------------------
499
void Instruction::SetBranchType( EBRANCHTYPE aBranchType )
500
{
501
        SetbitRange<16>(mOperation,OP_BTYPE_RNG,aBranchType);
502
}
503
//--------------------------------------------------------------
504
void Instruction::ClearWriteChannel()
505
{
506
 
507
        mDestination[DST_WE_X] = false;
508
        mDestination[DST_WE_Y] = false;
509
        mDestination[DST_WE_Z] = false;
510
}
511
//--------------------------------------------------------------
512
void Instruction::SetWriteChannel( ECHANNEL aChannel )
513
{
514
 
515
        if (aChannel == ECHANNEL_XYZ)
516
        {
517
                mDestination[DST_WE_X] = true;
518
                mDestination[DST_WE_Y] = true;
519
                mDestination[DST_WE_Z] = true;
520
                return;
521
        }
522
 
523
        switch ( aChannel )
524
        {
525
                case ECHANNEL_X:
526
                mDestination[DST_WE_X] = true;
527
                break;
528
                case ECHANNEL_Y:
529
                mDestination[DST_WE_Y] = true;
530
                break;
531
                case ECHANNEL_Z:
532
                mDestination[DST_WE_Z] = true;
533
                break;
534
        }
535
 
536
}
537
//--------------------------------------------------------------
538
void Instruction::SetDestinationAddress( unsigned int aAddress )
539
{
540
 
541
        SetbitRange<14>(mDestination,DST_ADDR,aAddress);
542
 
543
}
544
//--------------------------------------------------------------
545
void Instruction::SetDestinationSymbol( std::string aSymbol )
546
{
547
        mDestinationIsSymbol = true;
548
        mDestinationSymbol = aSymbol;
549
}
550
//--------------------------------------------------------------
551
void Instruction::SetSrc1SignX( bool aSign )
552
{
553
        mSource1[SRC1_SIGN_X] = aSign;
554
}
555
//--------------------------------------------------------------
556
void Instruction::SetSrc1SignY( bool aSign )
557
{
558
        mSource1[SRC1_SIGN_Y] = aSign;
559
}
560
//--------------------------------------------------------------
561
void Instruction::SetSrc1SignZ( bool aSign )
562
{
563
        mSource1[SRC1_SIGN_Z] = aSign;
564
}
565
//--------------------------------------------------------------
566
void Instruction::SetSrc1SwizzleX(ESWIZZLE_X aChannel)
567
{
568
        SetbitRange<17>(mSource1,SRC1_SWZ_X,aChannel);
569
 
570
}
571
//--------------------------------------------------------------
572
void Instruction::SetSrc1SwizzleY(ESWIZZLE_Y aChannel)
573
{
574
        SetbitRange<17>(mSource1,SRC1_SWZ_Y,aChannel);
575
 
576
}
577
//--------------------------------------------------------------
578
void Instruction::SetSrc1SwizzleZ(ESWIZZLE_Z aChannel)
579
{
580
        SetbitRange<17>(mSource1,SRC1_SWZ_Z,aChannel);
581
 
582
}
583
//--------------------------------------------------------------
584
void Instruction::SetSrc1Address(unsigned int aAddress )
585
{
586
        SetbitRange<17>(mSource1,SRC1_ADDR_RNG,aAddress);
587
}
588
//--------------------------------------------------------------
589
void Instruction::SetSrc1Rotation( EROTATION aRotation )
590
{
591
        unsigned int OldVal = GetbitRange<16>(mOperation,OP_SCALE_RNG);
592
 
593
        SetbitRange<16>(mOperation,OP_SCALE_RNG,(OldVal | aRotation) );
594
}
595
//--------------------------------------------------------------
596
void Instruction::SetSrc0Rotation( EROTATION aRotation )
597
{
598
        unsigned int OldVal = GetbitRange<16>(mOperation,OP_SCALE_RNG);
599
 
600
        SetbitRange<16>(mOperation,OP_SCALE_RNG,(OldVal | aRotation ) );
601
}
602
//--------------------------------------------------------------
603
void Instruction::SetSrc0SignX( bool aSign )
604
{
605
        mSource0[SRC0_SIGN_X] = aSign;
606
}
607
//--------------------------------------------------------------
608
void Instruction::SetSrc0SignY( bool aSign )
609
{
610
        mSource0[SRC0_SIGN_Y] = aSign;
611
}
612
//--------------------------------------------------------------
613
void Instruction::SetSrc0SignZ( bool aSign )
614
{
615
        mSource0[SRC0_SIGN_Z] = aSign;
616
}
617
//--------------------------------------------------------------
618
void Instruction::SetSrc0SwizzleX(ESWIZZLE_X aChannel)
619
{
620
SetbitRange<17>(mSource0,SRC0_SWZ_X,aChannel);
621
 
622
}
623
//--------------------------------------------------------------
624
void Instruction::SetSrc0SwizzleY(ESWIZZLE_Y aChannel)
625
{
626
        SetbitRange<17>(mSource0,SRC0_SWZ_Y,aChannel);
627
 
628
 
629
}
630
//--------------------------------------------------------------
631
void Instruction::SetSrc0SwizzleZ(ESWIZZLE_Z aChannel)
632
{
633
SetbitRange<17>(mSource0,SRC0_SWZ_Z,aChannel);
634
 
635
}
636
//--------------------------------------------------------------
637
void Instruction::SetSrc0Address(unsigned int aAddress )
638
{
639
        SetbitRange<17>(mSource0,SRC0_ADDR_RNG,aAddress);
640
}
641
//--------------------------------------------------------------
642
 std::bitset<DESTINATION_SIZE> Instruction::GetDestination( )
643
{
644
        return mDestination;
645
}
646
//--------------------------------------------------------------
647
ECHANNEL Instruction::GetWriteChannel(  )
648
{
649
        //std::cout << "Ecahhhannel " << GetbitRange<DESTINATION_SIZE>(mDestination,DST_WE_RNG) << "\n";
650
 
651
        return ((ECHANNEL)GetbitRange<DESTINATION_SIZE>(mDestination,DST_WE_RNG));
652
}
653
//--------------------------------------------------------------
654
/*
655
void Instruction::SetDestination( std::bitset<DESTINATION_SIZE> aDestination )
656
{
657
        mDestination = aDestination;
658
}
659
*/
660
//--------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.