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[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [CORES/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 26

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET                                                        0
`define EXEU_INITIAL_STATE                                              1
`define EXEU_WAIT_FOR_DECODE                                            2
`define EXEU_FETCH_DECODED_INST                                 3
`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
`define EXEU_WRITE_BACK_TO_RAM                                  5
`define EXEU_HANDLE_JUMP                                                        7
 
 
 
module ExecutionFSM
(
input wire                                                              Clock,
input wire                                                              Reset,
 
input   wire                                                                            iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
//output        reg                                                                     ReadyForNextInstruction,
output wire                                                                     oJumpFlag                       ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
output  wire                                                                    oRAMWriteEnable         ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
output  wire                                                                    oExeLatchedValues,
output  reg                                                                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
output  wire                                                                                                    oTriggerALU,
 
input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
input wire                                                                                                              iALUOutputReady,
input   wire                                                                                                            iBranchTaken,
input wire                                                                                                              iBranchNotTaken,
 
`ifdef DEBUG
        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[95:64] ),
        .Q( oALUChannelX1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[63:32] ),
        .Q( oALUChannelY1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[31:0] ),
        .Q( oALUChannelZ1 )
);
 
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[95:64] ),
        .Q( oALUChannelX2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[63:32] ),
        .Q( oALUChannelY2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[31:0] ),
        .Q( oALUChannelZ2 )
);
 
//Finally one more latch to store 
//the iOperation and the destination
 
/*
FF6_POSEDGE_SYNCRONOUS_RESET FFOperation
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iOperation  ),
        .Q( oALUOperation )
 
);
*/
 
FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iOperation  ),
        .Q( oALUOperation )
 
);
 
 
FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
(
        .Clock( wLatchNow  ),
        .Clear( Reset ),
        .D( iDestination  ),
        .Q( oRAMWriteAddress )
 
);
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
                CurrentState <= `EXEU_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
                  //------------------------------------------
                  `EXEU_AFTER_RESET:
                  begin
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /**
                        At the same time iDecodeDone goes to 1, our Flops
                        will store the value, so next clock cycle we can
                        tell IDU to go ahead and decode the next instruction
                        in the pipeline.
                  */
                  `EXEU_WAIT_FOR_DECODE:
                  begin
 
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                        if ( iDecodeDone )      //This same thing triggers the ALU
                                NextState       <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /*
                  If the instruction is aritmetic then pass the parameters
                  the ALU, else if it store iOperation then...
                  */
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         //*
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      0;               //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
                                        NextState <= `EXEU_WAIT_FOR_DECODE;
                                else
                                        NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                  end
                  //------------------------------------------
                  `EXEU_WRITE_BACK_TO_RAM:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      1;
 
                        if ( iDecodeDone )
                                NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState <= `EXEU_WAIT_FOR_DECODE;
 
                  end
 
                  //------------------------------------------
                  default:
                  begin
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
                                NextState <= `EXEU_AFTER_RESET;
                  end
                  //------------------------------------------
        endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
        $display("Opening ucode dump file....\n");
        ucode_file = $fopen("Code.log","w");
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
        $display("Opening Register lof file...\n");
        reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
        always @ (posedge iDecodeDone)
        begin
                `LOGME"IP:%d", iDebug_CurrentIP);
        end
 
        always @ (negedge  Clock )
        begin
        if ( iALUOutputReady )
        begin
 
 
                if (iBranchTaken)
                        `LOGME"<BT>");
 
                if (iBranchNotTaken     )
                        `LOGME"<BNT>");
 
                if (oRAMWriteEnable)
                        `LOGME"<WE>");
 
                `LOGME "(%dns ",$time);
                                        case ( oALUOperation )
                                        `RETURN: `LOGME"RETURN");
                                        `ADD:   `LOGME"ADD");
                                        `SUB:           `LOGME"SUB");
                                        `DIV:           `LOGME"DIV");
                                        `MUL:   `LOGME"MUL");
                                        `MAG:           `LOGME"MAG");
                                        `JGX:           `LOGME"JGX");
                                        `JGEX:  `LOGME"JGEX");
                                        `JGEY:  `LOGME"JGEY");
                                        `JGEZ:  `LOGME"JGEZ");
                                        `JLEX:  `LOGME"JLEX");
                                        `JLEY:  `LOGME"JLEY");
                                        `JLEZ:  `LOGME"JLEZ");
                                        `JMP:           `LOGME"JMP");
                                        `ZERO:  `LOGME"ZERO");
                                        `JNEX:  `LOGME"JNEX");
                                        `JNEY:  `LOGME"JNEY");
                                        `JNEZ:  `LOGME"JNEZ");
                                        `JEQX:  `LOGME"JEQX");
                                        `JEQY:  `LOGME"JEQY");
                                        `JEQZ:  `LOGME"JEQZ");
                                        `CROSS: `LOGME"CROSS");
                                        `DOT:           `LOGME"DOT");
                                        `SETX:  `LOGME"SETX");
                                        `SETY:  `LOGME"SETY");
                                        `SETZ:  `LOGME"SETZ");
                                        `NOP:   `LOGME"NOP");
                                        `COPY:  `LOGME"COPY");
                                        `INC:           `LOGME"INC");
                                        `DEC:           `LOGME"DEC");
                                        `MOD:           `LOGME"MOD");
                                        `FRAC:  `LOGME"FRAC");
                                        `NEG:    `LOGME"NEG");
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
                                        `MULP:          `LOGME"MULP");
                                        `XCHANGEX:      `LOGME"XCHANGEX");
                                        `IMUL:      `LOGME"IMUL");
                                        `UNSCALE:      `LOGME"UNSCALE");
                                        `INCX: `LOGME"INCX");
                                        `INCY: `LOGME"INCY");
                                        `INCZ: `LOGME"INCZ");
                                        `DEBUG_PRINT:
                                        begin
                                                `LOGME"DEBUG_PRINT");
 
                                        end
                                        default:
                                        begin
                                                `LOGME"**********ERROR UNKNOWN OP*********");
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
                                        //      $stop();
                                        end
                                        endcase
 
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
                                        oRAMWriteAddress,
                                        oALUChannelX1,oALUChannelY1,oALUChannelZ1,
                                        oALUChannelX2,oALUChannelY2,oALUChannelZ2
 
                                        );
 
                                        if (oALUOperation == `RETURN)
                                                `LOGME"\n\n\n");
 
                end
        end //always
 
        always @ ( negedge Clock )
        begin
        if ( iALUOutputReady )
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
        end //always
`endif
 
endmodule

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[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [CORES/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define EXEU_AFTER_RESET 0
23			`define EXEU_INITIAL_STATE 1
24			`define EXEU_WAIT_FOR_DECODE 2
25			`define EXEU_FETCH_DECODED_INST 3
26			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
27			`define EXEU_WRITE_BACK_TO_RAM 5
28			`define EXEU_HANDLE_JUMP 7
29
30
31
32			`module ExecutionFSM`
33			`(`
34			`input wire Clock,`
35			`input wire Reset,`
36
37			`input wire iDecodeDone,`
38			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
39			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
40			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
41			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
42			`//output reg ReadyForNextInstruction,`
43			`output wire oJumpFlag ,`
44			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
45			`output wire oRAMWriteEnable ,`
46			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
47			`output wire oExeLatchedValues,`
48			`output reg oBusy ,`
49
50			`//ALU ports and control signals`
51			output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
52			output wire [`WIDTH-1:0] oALUChannelX1,
53			output wire [`WIDTH-1:0] oALUChannelY1,
54			output wire [`WIDTH-1:0] oALUChannelZ1,
55			output wire [`WIDTH-1:0] oALUChannelX2,
56			output wire [`WIDTH-1:0] oALUChannelY2,
57			output wire [`WIDTH-1:0] oALUChannelZ2,
58			`output wire oTriggerALU,`
59
60			input wire [`WIDTH-1:0] iALUResultX,
61			input wire [`WIDTH-1:0] iALUResultY,
62			input wire [`WIDTH-1:0] iALUResultZ,
63			`input wire iALUOutputReady,`
64			`input wire iBranchTaken,`
65			`input wire iBranchNotTaken,`
66
67			`ifdef DEBUG
68			input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
69			`endif
70			`//Data forward Signals`
71			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
72
73
74			`);`
75
76			`wire wLatchNow;`
77			`reg rInputLatchesEnabled;`
78
79			`//If ALU says jump, just pass along`
80			`assign oJumpFlag = iBranchTaken;`
81			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
82			`assign oJumpIp = oRAMWriteAddress;`
83
84			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
85			`assign oExeLatchedValues = wLatchNow;`
86			`assign oTriggerALU = wLatchNow;`
87
88			`wire wOperationIsJump;`
89			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
90
91			`//Don't allow me to write back back if the operation is a NOP`
92			`ifdef DEBUG
93			`assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&`
94			(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
95			`else
96			assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
97			`endif
98
99
100			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
101
102			`FF32_POSEDGE_SYNCRONOUS_RESET SourceX1`
103			`(`
104			`.Clock( wLatchNow ),`
105			`.Clear( Reset ),`
106			`.D( iSource1[95:64] ),`
107			`.Q( oALUChannelX1 )`
108			`);`
109
110			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY1`
111			`(`
112			`.Clock( wLatchNow ),`
113			`.Clear( Reset ),`
114			`.D( iSource1[63:32] ),`
115			`.Q( oALUChannelY1 )`
116			`);`
117
118			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1`
119			`(`
120			`.Clock( wLatchNow ),`
121			`.Clear( Reset ),`
122			`.D( iSource1[31:0] ),`
123			`.Q( oALUChannelZ1 )`
124			`);`
125
126
127			`FF32_POSEDGE_SYNCRONOUS_RESET SourceX2`
128			`(`
129			`.Clock( wLatchNow ),`
130			`.Clear( Reset ),`
131			`.D( iSource0[95:64] ),`
132			`.Q( oALUChannelX2 )`
133			`);`
134
135			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY2`
136			`(`
137			`.Clock( wLatchNow ),`
138			`.Clear( Reset ),`
139			`.D( iSource0[63:32] ),`
140			`.Q( oALUChannelY2 )`
141			`);`
142
143			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2`
144			`(`
145			`.Clock( wLatchNow ),`
146			`.Clear( Reset ),`
147			`.D( iSource0[31:0] ),`
148			`.Q( oALUChannelZ2 )`
149			`);`
150
151			`//Finally one more latch to store`
152			`//the iOperation and the destination`
153
154			`/*`
155			`FF6_POSEDGE_SYNCRONOUS_RESET FFOperation`
156			`(`
157			`.Clock( wLatchNow ),`
158			`.Clear( Reset ),`
159			`.D( iOperation ),`
160			`.Q( oALUOperation )`
161
162			`);`
163			`*/`
164
165			`FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation`
166			`(`
167			`.Clock( wLatchNow ),`
168			`.Clear( Reset ),`
169			`.D( iOperation ),`
170			`.Q( oALUOperation )`
171
172			`);`
173
174
175			`FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination`
176			`(`
177			`.Clock( wLatchNow ),`
178			`.Clear( Reset ),`
179			`.D( iDestination ),`
180			`.Q( oRAMWriteAddress )`
181
182			`);`
183			`//Data forwarding`
184			`assign oLastDestination = oRAMWriteAddress;`
185
186			`reg [7:0] CurrentState;`
187			`reg [7:0] NextState;`
188
189
190			`//------------------------------------------------`
191			`always @(posedge Clock or posedge Reset)`
192			`begin`
193
194
195
196			`if (Reset)`
197			CurrentState <= `EXEU_AFTER_RESET;
198			`else`
199			`CurrentState <= NextState;`
200
201			`end`
202			`//------------------------------------------------`
203
204
205			`always @( * )`
206			`begin`
207			`case (CurrentState)`
208			`//------------------------------------------`
209			`EXEU_AFTER_RESET:
210			`begin`
211			`//ReadyForNextInstruction <= 1;`
212			`oBusy <= 0;`
213			`rInputLatchesEnabled <= 1;`
214
215
216			NextState <= `EXEU_WAIT_FOR_DECODE;
217			`end`
218			`//------------------------------------------`
219			`/**`
220			`At the same time iDecodeDone goes to 1, our Flops`
221			`will store the value, so next clock cycle we can`
222			`tell IDU to go ahead and decode the next instruction`
223			`in the pipeline.`
224			`*/`
225			`EXEU_WAIT_FOR_DECODE:
226			`begin`
227
228
229			`//ReadyForNextInstruction <= 1;`
230			`oBusy <= 0;`
231			`rInputLatchesEnabled <= 1;`
232
233
234			`if ( iDecodeDone ) //This same thing triggers the ALU`
235			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
236			`else`
237			NextState <= `EXEU_WAIT_FOR_DECODE;
238			`end`
239			`//------------------------------------------`
240			`/*`
241			`If the instruction is aritmetic then pass the parameters`
242			`the ALU, else if it store iOperation then...`
243			`*/`
244			`EXEU_WAIT_FOR_ALU_EXECUTION:
245			`begin`
246
247			`//ReadyForNextInstruction <= 0; //*`
248			`oBusy <= 1;`
249			`rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
250
251
252
253			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
254			NextState <= `EXEU_WAIT_FOR_DECODE;
255			`else`
256			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
257			`end`
258			`//------------------------------------------`
259			`EXEU_WRITE_BACK_TO_RAM:
260			`begin`
261
262			`//ReadyForNextInstruction <= 0;`
263			`oBusy <= 1;`
264			`rInputLatchesEnabled <= 1;`
265
266			`if ( iDecodeDone )`
267			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
268			`else`
269			NextState <= `EXEU_WAIT_FOR_DECODE;
270
271			`end`
272
273			`//------------------------------------------`
274			`default:`
275			`begin`
276
277			`//ReadyForNextInstruction <= 1;`
278			`oBusy <= 0;`
279			`rInputLatchesEnabled <= 1;`
280
281			NextState <= `EXEU_AFTER_RESET;
282			`end`
283			`//------------------------------------------`
284			`endcase`
285			`end`
286
287			`//-----------------------------------------------------------------------`
288			`ifdef DUMP_CODE
289			`integer ucode_file;`
290			`integer reg_log;`
291			`initial`
292			`begin`
293
294			`$display("Opening ucode dump file....\n");`
295			`ucode_file = $fopen("Code.log","w");`
296			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
297			`$display("Opening Register lof file...\n");`
298			`reg_log = $fopen("Registers.log","w");`
299
300			`end`
301
302			`endif //Ucode dump
303
304			`//-----------------------------------------------------------------------`
305			`ifdef DEBUG
306			`always @ (posedge iDecodeDone)`
307			`begin`
308			`LOGME"IP:%d", iDebug_CurrentIP);
309			`end`
310
311			`always @ (negedge Clock )`
312			`begin`
313			`if ( iALUOutputReady )`
314			`begin`
315
316
317			`if (iBranchTaken)`
318			`LOGME"<BT>");
319
320			`if (iBranchNotTaken )`
321			`LOGME"<BNT>");
322
323			`if (oRAMWriteEnable)`
324			`LOGME"<WE>");
325
326			`LOGME "(%dns ",$time);
327			`case ( oALUOperation )`
328			`RETURN: `LOGME"RETURN");
329			`ADD: `LOGME"ADD");
330			`SUB: `LOGME"SUB");
331			`DIV: `LOGME"DIV");
332			`MUL: `LOGME"MUL");
333			`MAG: `LOGME"MAG");
334			`JGX: `LOGME"JGX");
335			`JGEX: `LOGME"JGEX");
336			`JGEY: `LOGME"JGEY");
337			`JGEZ: `LOGME"JGEZ");
338			`JLEX: `LOGME"JLEX");
339			`JLEY: `LOGME"JLEY");
340			`JLEZ: `LOGME"JLEZ");
341			`JMP: `LOGME"JMP");
342			`ZERO: `LOGME"ZERO");
343			`JNEX: `LOGME"JNEX");
344			`JNEY: `LOGME"JNEY");
345			`JNEZ: `LOGME"JNEZ");
346			`JEQX: `LOGME"JEQX");
347			`JEQY: `LOGME"JEQY");
348			`JEQZ: `LOGME"JEQZ");
349			`CROSS: `LOGME"CROSS");
350			`DOT: `LOGME"DOT");
351			`SETX: `LOGME"SETX");
352			`SETY: `LOGME"SETY");
353			`SETZ: `LOGME"SETZ");
354			`NOP: `LOGME"NOP");
355			`COPY: `LOGME"COPY");
356			`INC: `LOGME"INC");
357			`DEC: `LOGME"DEC");
358			`MOD: `LOGME"MOD");
359			`FRAC: `LOGME"FRAC");
360			`NEG: `LOGME"NEG");
361			`SWIZZLE3D: `LOGME"SWIZZLE3D");
362			`MULP: `LOGME"MULP");
363			`XCHANGEX: `LOGME"XCHANGEX");
364			`IMUL: `LOGME"IMUL");
365			`UNSCALE: `LOGME"UNSCALE");
366			`INCX: `LOGME"INCX");
367			`INCY: `LOGME"INCY");
368			`INCZ: `LOGME"INCZ");
369			`DEBUG_PRINT:
370			`begin`
371			`LOGME"DEBUG_PRINT");
372
373			`end`
374			`default:`
375			`begin`
376			`LOGME"********ERROR UNKNOWN OP*******");
377			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
378			`// $stop();`
379			`end`
380			`endcase`
381
382			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
383			`oRAMWriteAddress,`
384			`oALUChannelX1,oALUChannelY1,oALUChannelZ1,`
385			`oALUChannelX2,oALUChannelY2,oALUChannelZ2`
386
387			`);`
388
389			if (oALUOperation == `RETURN)
390			`LOGME"\n\n\n");
391
392			`end`
393			`end //always`
394
395			`always @ ( negedge Clock )`
396			`begin`
397			`if ( iALUOutputReady )`
398			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
399			`end //always`
400			`endif
401
402			`endmodule`