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[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [CORES/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 72

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET                                                        0
`define EXEU_INITIAL_STATE                                              1
`define EXEU_WAIT_FOR_DECODE                                            2
`define EXEU_FETCH_DECODED_INST                                 3
`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
`define EXEU_WRITE_BACK_TO_RAM                                  5
`define EXEU_HANDLE_JUMP                                                        7
 
 
 
module ExecutionFSM
(
input wire                                                              Clock,
input wire                                                              Reset,
 
input   wire                                                                            iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
//output        reg                                                                     ReadyForNextInstruction,
output wire                                                                     oJumpFlag                       ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
output  wire                                                                    oRAMWriteEnable         ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
output  wire                                                                    oExeLatchedValues,
output  reg                                                                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
output  wire                                                                                                    oTriggerALU,
 
input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
input wire                                                                                                              iALUOutputReady,
input   wire                                                                                                            iBranchTaken,
input wire                                                                                                              iBranchNotTaken,
 
`ifdef DEBUG
        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
assign oALUChannelX1 = iSource1[95:64];
assign oALUChannelY1 = iSource1[63:32];
assign oALUChannelZ1 = iSource1[31:0];
 
assign oALUChannelX2 = iSource0[95:64];
assign oALUChannelY2 = iSource0[63:32];
assign oALUChannelZ2 = iSource0[31:0];
 
/*
FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[95:64] ),
        .Q( oALUChannelX1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[63:32] ),
        .Q( oALUChannelY1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[31:0] ),
        .Q( oALUChannelZ1 )
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[95:64] ),
        .Q(oALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[63:32] ),
        .Q(oALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[31:0] ),
        .Q(oALUChannelZ1)
);
*/
/*
FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[95:64] ),
        .Q( oALUChannelX2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[63:32] ),
        .Q( oALUChannelY2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[31:0] ),
        .Q( oALUChannelZ2 )
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[95:64] ),
        .Q(oALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[63:32] ),
        .Q(oALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[31:0] ),
        .Q(oALUChannelZ2)
);
*/
//Finally one more latch to store 
//the iOperation and the destination
 
 
assign oALUOperation = iOperation;
//assign oRAMWriteAddress = iDestination;
/*
FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iOperation  ),
        .Q( oALUOperation )
 
);
 
 
FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
(
        .Clock( wLatchNow  ),
        .Clear( Reset ),
        .D( iDestination  ),
        .Q( oRAMWriteAddress )
 
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iOperation ),
        .Q(oALUOperation)
);
*/
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iDestination ),
        .Q(oRAMWriteAddress)
);
 
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
                CurrentState <= `EXEU_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
                  //------------------------------------------
                  `EXEU_AFTER_RESET:
                  begin
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /**
                        At the same time iDecodeDone goes to 1, our Flops
                        will store the value, so next clock cycle we can
                        tell IDU to go ahead and decode the next instruction
                        in the pipeline.
                  */
                  `EXEU_WAIT_FOR_DECODE:
                  begin
 
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                        if ( iDecodeDone )      //This same thing triggers the ALU
                                NextState       <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /*
                  If the instruction is aritmetic then pass the parameters
                  the ALU, else if it store iOperation then...
                  */
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         //*
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      0;               //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
                                        NextState <= `EXEU_WAIT_FOR_DECODE;
                                else
                                        NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                  end
                  //------------------------------------------
                  `EXEU_WRITE_BACK_TO_RAM:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      1;
 
                        if ( iDecodeDone )
                                NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState <= `EXEU_WAIT_FOR_DECODE;
 
                  end
 
                  //------------------------------------------
                  default:
                  begin
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
                                NextState <= `EXEU_AFTER_RESET;
                  end
                  //------------------------------------------
        endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
        $display("Opening ucode dump file....\n");
        ucode_file = $fopen("Code.log","w");
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
        $display("Opening Register lof file...\n");
        reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[95:64] ),
        .Q(wALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[63:32] ),
        .Q(wALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[31:0] ),
        .Q(wALUChannelZ1)
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[95:64] ),
        .Q(wALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[63:32] ),
        .Q(wALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[31:0] ),
        .Q(wALUChannelZ2)
);
 
 
        always @ (posedge iDecodeDone)
        begin
                `LOGME"IP:%d", iDebug_CurrentIP);
        end
 
        always @ (negedge  Clock )
        begin
        if ( iALUOutputReady )
        begin
 
 
                if (iBranchTaken)
                        `LOGME"<BT>");
 
                if (iBranchNotTaken     )
                        `LOGME"<BNT>");
 
                if (oRAMWriteEnable)
                        `LOGME"<WE>");
 
                `LOGME "(%dns ",$time);
                                        case ( oALUOperation )
                                        `RETURN: `LOGME"RETURN");
                                        `ADD:   `LOGME"ADD");
                                        `SUB:           `LOGME"SUB");
                                        `DIV:           `LOGME"DIV");
                                        `MUL:   `LOGME"MUL");
                                        `MAG:           `LOGME"MAG");
                                        `JGX:           `LOGME"JGX");
                                        `JLX:           `LOGME"JLX");
                                        `JGEX:  `LOGME"JGEX");
                                        `JGEY:  `LOGME"JGEY");
                                        `JGEZ:  `LOGME"JGEZ");
                                        `JLEX:  `LOGME"JLEX");
                                        `JLEY:  `LOGME"JLEY");
                                        `JLEZ:  `LOGME"JLEZ");
                                        `JMP:           `LOGME"JMP");
                                        `ZERO:  `LOGME"ZERO");
                                        `JNEX:  `LOGME"JNEX");
                                        `JNEY:  `LOGME"JNEY");
                                        `JNEZ:  `LOGME"JNEZ");
                                        `JEQX:  `LOGME"JEQX");
                                        `JEQY:  `LOGME"JEQY");
                                        `JEQZ:  `LOGME"JEQZ");
                                        `CROSS: `LOGME"CROSS");
                                        `DOT:           `LOGME"DOT");
                                        `SETX:  `LOGME"SETX");
                                        `SETY:  `LOGME"SETY");
                                        `SETZ:  `LOGME"SETZ");
                                        `NOP:   `LOGME"NOP");
                                        `COPY:  `LOGME"COPY");
                                        `INC:           `LOGME"INC");
                                        `DEC:           `LOGME"DEC");
                                        `MOD:           `LOGME"MOD");
                                        `FRAC:  `LOGME"FRAC");
                                        `NEG:    `LOGME"NEG");
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
                                        `MULP:          `LOGME"MULP");
                                        `XCHANGEX:      `LOGME"XCHANGEX");
                                        `IMUL:      `LOGME"IMUL");
                                        `UNSCALE:      `LOGME"UNSCALE");
                                        `INCX: `LOGME"INCX");
                                        `INCY: `LOGME"INCY");
                                        `INCZ: `LOGME"INCZ");
                                        `DEBUG_PRINT:
                                        begin
                                                `LOGME"DEBUG_PRINT");
 
                                        end
                                        default:
                                        begin
                                                `LOGME"**********ERROR UNKNOWN OP*********");
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
                                        //      $stop();
                                        end
                                        endcase
 
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
                                        oRAMWriteAddress,
                                        wALUChannelX1,wALUChannelY1,wALUChannelZ1,
                                        wALUChannelX2,wALUChannelY2,wALUChannelZ2
 
                                        );
 
                                        if (oALUOperation == `RETURN)
                                                `LOGME"\n\n\n");
 
                end
        end //always
 
        always @ ( negedge Clock )
        begin
        if ( iALUOutputReady )
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
        end //always
`endif
 
endmodule

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Subversion Repositories theia_gpu

[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [CORES/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 72

Line No.	Rev	Author	Line
1	26	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define EXEU_AFTER_RESET 0
23			`define EXEU_INITIAL_STATE 1
24			`define EXEU_WAIT_FOR_DECODE 2
25			`define EXEU_FETCH_DECODED_INST 3
26			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
27			`define EXEU_WRITE_BACK_TO_RAM 5
28			`define EXEU_HANDLE_JUMP 7
29
30
31
32			`module ExecutionFSM`
33			`(`
34			`input wire Clock,`
35			`input wire Reset,`
36
37			`input wire iDecodeDone,`
38			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
39			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
40			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
41			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
42			`//output reg ReadyForNextInstruction,`
43			`output wire oJumpFlag ,`
44			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
45			`output wire oRAMWriteEnable ,`
46			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
47			`output wire oExeLatchedValues,`
48			`output reg oBusy ,`
49
50			`//ALU ports and control signals`
51			output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
52			output wire [`WIDTH-1:0] oALUChannelX1,
53			output wire [`WIDTH-1:0] oALUChannelY1,
54			output wire [`WIDTH-1:0] oALUChannelZ1,
55			output wire [`WIDTH-1:0] oALUChannelX2,
56			output wire [`WIDTH-1:0] oALUChannelY2,
57			output wire [`WIDTH-1:0] oALUChannelZ2,
58			`output wire oTriggerALU,`
59
60			input wire [`WIDTH-1:0] iALUResultX,
61			input wire [`WIDTH-1:0] iALUResultY,
62			input wire [`WIDTH-1:0] iALUResultZ,
63			`input wire iALUOutputReady,`
64			`input wire iBranchTaken,`
65			`input wire iBranchNotTaken,`
66
67			`ifdef DEBUG
68			input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
69			`endif
70			`//Data forward Signals`
71			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
72
73
74			`);`
75
76			`wire wLatchNow;`
77			`reg rInputLatchesEnabled;`
78
79			`//If ALU says jump, just pass along`
80			`assign oJumpFlag = iBranchTaken;`
81			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
82			`assign oJumpIp = oRAMWriteAddress;`
83
84			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
85			`assign oExeLatchedValues = wLatchNow;`
86			`assign oTriggerALU = wLatchNow;`
87
88			`wire wOperationIsJump;`
89			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
90
91			`//Don't allow me to write back back if the operation is a NOP`
92			`ifdef DEBUG
93			`assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&`
94			(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
95			`else
96			assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
97			`endif
98
99
100			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
101
102	72	diegovalve	`assign oALUChannelX1 = iSource1[95:64];`
103			`assign oALUChannelY1 = iSource1[63:32];`
104			`assign oALUChannelZ1 = iSource1[31:0];`
105
106			`assign oALUChannelX2 = iSource0[95:64];`
107			`assign oALUChannelY2 = iSource0[63:32];`
108			`assign oALUChannelZ2 = iSource0[31:0];`
109
110			`/*`
111	26	diegovalve	`FF32_POSEDGE_SYNCRONOUS_RESET SourceX1`
112			`(`
113			`.Clock( wLatchNow ),`
114			`.Clear( Reset ),`
115			`.D( iSource1[95:64] ),`
116			`.Q( oALUChannelX1 )`
117			`);`
118
119			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY1`
120			`(`
121			`.Clock( wLatchNow ),`
122			`.Clear( Reset ),`
123			`.D( iSource1[63:32] ),`
124			`.Q( oALUChannelY1 )`
125			`);`
126
127			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1`
128			`(`
129			`.Clock( wLatchNow ),`
130			`.Clear( Reset ),`
131			`.D( iSource1[31:0] ),`
132			`.Q( oALUChannelZ1 )`
133			`);`
134	72	diegovalve	`*/`
135			`/*`
136			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
137			`(`
138			`.Clock( Clock ),//wLatchNow ),`
139			`.Reset( Reset),`
140			`.Enable( wLatchNow ),//1'b1 ),`
141			`.D( iSource1[95:64] ),`
142			`.Q(oALUChannelX1)`
143			`);`
144			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
145			`(`
146			`.Clock( Clock ),//wLatchNow ),`
147			`.Reset( Reset),`
148			`.Enable( wLatchNow ),//1'b1 ),`
149			`.D( iSource1[63:32] ),`
150			`.Q(oALUChannelY1)`
151			`);`
152			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
153			`(`
154			`.Clock( Clock ),//wLatchNow ),`
155			`.Reset( Reset),`
156			`.Enable( wLatchNow ),//1'b1 ),`
157			`.D( iSource1[31:0] ),`
158			`.Q(oALUChannelZ1)`
159			`);`
160			`*/`
161			`/*`
162	26	diegovalve	`FF32_POSEDGE_SYNCRONOUS_RESET SourceX2`
163			`(`
164			`.Clock( wLatchNow ),`
165			`.Clear( Reset ),`
166			`.D( iSource0[95:64] ),`
167			`.Q( oALUChannelX2 )`
168			`);`
169
170			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY2`
171			`(`
172			`.Clock( wLatchNow ),`
173			`.Clear( Reset ),`
174			`.D( iSource0[63:32] ),`
175			`.Q( oALUChannelY2 )`
176			`);`
177
178			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2`
179			`(`
180			`.Clock( wLatchNow ),`
181			`.Clear( Reset ),`
182			`.D( iSource0[31:0] ),`
183			`.Q( oALUChannelZ2 )`
184			`);`
185	72	diegovalve	`*/`
186	26	diegovalve	`/*`
187	72	diegovalve	FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
188	26	diegovalve	`(`
189	72	diegovalve	`.Clock( Clock ),//wLatchNow ),`
190			`.Reset( Reset),`
191			`.Enable( wLatchNow ),//1'b1 ),`
192			`.D( iSource0[95:64] ),`
193			`.Q(oALUChannelX2)`
194	26	diegovalve	`);`
195	72	diegovalve	FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
196			`(`
197			`.Clock( Clock ),//wLatchNow ),`
198			`.Reset( Reset),`
199			`.Enable( wLatchNow ),//1'b1 ),`
200			`.D( iSource0[63:32] ),`
201			`.Q(oALUChannelY2)`
202			`);`
203			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
204			`(`
205			`.Clock( Clock ),//wLatchNow ),`
206			`.Reset( Reset),`
207			`.Enable( wLatchNow ),//1'b1 ),`
208			`.D( iSource0[31:0] ),`
209			`.Q(oALUChannelZ2)`
210			`);`
211	26	diegovalve	`*/`
212	72	diegovalve	`//Finally one more latch to store`
213			`//the iOperation and the destination`
214	26	diegovalve
215	72	diegovalve
216			`assign oALUOperation = iOperation;`
217			`//assign oRAMWriteAddress = iDestination;`
218			`/*`
219	26	diegovalve	`FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation`
220			`(`
221			`.Clock( wLatchNow ),`
222			`.Clear( Reset ),`
223			`.D( iOperation ),`
224			`.Q( oALUOperation )`
225
226			`);`
227
228
229			`FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination`
230			`(`
231			`.Clock( wLatchNow ),`
232			`.Clear( Reset ),`
233			`.D( iDestination ),`
234			`.Q( oRAMWriteAddress )`
235
236			`);`
237	72	diegovalve	`*/`
238			`/*`
239			FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
240			`(`
241			`.Clock( Clock ),//wLatchNow ),`
242			`.Reset( Reset),`
243			`.Enable( wLatchNow ),//1'b1 ),`
244			`.D( iOperation ),`
245			`.Q(oALUOperation)`
246			`);`
247			`*/`
248			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
249			`(`
250			`.Clock( Clock ),//wLatchNow ),`
251			`.Reset( Reset),`
252			`.Enable( wLatchNow ),//1'b1 ),`
253			`.D( iDestination ),`
254			`.Q(oRAMWriteAddress)`
255			`);`
256
257	26	diegovalve	`//Data forwarding`
258			`assign oLastDestination = oRAMWriteAddress;`
259
260			`reg [7:0] CurrentState;`
261			`reg [7:0] NextState;`
262
263
264			`//------------------------------------------------`
265			`always @(posedge Clock or posedge Reset)`
266			`begin`
267
268
269
270			`if (Reset)`
271			CurrentState <= `EXEU_AFTER_RESET;
272			`else`
273			`CurrentState <= NextState;`
274
275			`end`
276			`//------------------------------------------------`
277
278
279			`always @( * )`
280			`begin`
281			`case (CurrentState)`
282			`//------------------------------------------`
283			`EXEU_AFTER_RESET:
284			`begin`
285			`//ReadyForNextInstruction <= 1;`
286			`oBusy <= 0;`
287			`rInputLatchesEnabled <= 1;`
288
289
290			NextState <= `EXEU_WAIT_FOR_DECODE;
291			`end`
292			`//------------------------------------------`
293			`/**`
294			`At the same time iDecodeDone goes to 1, our Flops`
295			`will store the value, so next clock cycle we can`
296			`tell IDU to go ahead and decode the next instruction`
297			`in the pipeline.`
298			`*/`
299			`EXEU_WAIT_FOR_DECODE:
300			`begin`
301
302
303			`//ReadyForNextInstruction <= 1;`
304			`oBusy <= 0;`
305			`rInputLatchesEnabled <= 1;`
306
307
308			`if ( iDecodeDone ) //This same thing triggers the ALU`
309			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
310			`else`
311			NextState <= `EXEU_WAIT_FOR_DECODE;
312			`end`
313			`//------------------------------------------`
314			`/*`
315			`If the instruction is aritmetic then pass the parameters`
316			`the ALU, else if it store iOperation then...`
317			`*/`
318			`EXEU_WAIT_FOR_ALU_EXECUTION:
319			`begin`
320
321			`//ReadyForNextInstruction <= 0; //*`
322			`oBusy <= 1;`
323			`rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
324
325
326
327			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
328			NextState <= `EXEU_WAIT_FOR_DECODE;
329			`else`
330			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
331			`end`
332			`//------------------------------------------`
333			`EXEU_WRITE_BACK_TO_RAM:
334			`begin`
335
336			`//ReadyForNextInstruction <= 0;`
337			`oBusy <= 1;`
338			`rInputLatchesEnabled <= 1;`
339
340			`if ( iDecodeDone )`
341			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
342			`else`
343			NextState <= `EXEU_WAIT_FOR_DECODE;
344
345			`end`
346
347			`//------------------------------------------`
348			`default:`
349			`begin`
350
351			`//ReadyForNextInstruction <= 1;`
352			`oBusy <= 0;`
353			`rInputLatchesEnabled <= 1;`
354
355			NextState <= `EXEU_AFTER_RESET;
356			`end`
357			`//------------------------------------------`
358			`endcase`
359			`end`
360
361			`//-----------------------------------------------------------------------`
362			`ifdef DUMP_CODE
363			`integer ucode_file;`
364			`integer reg_log;`
365			`initial`
366			`begin`
367
368			`$display("Opening ucode dump file....\n");`
369			`ucode_file = $fopen("Code.log","w");`
370			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
371			`$display("Opening Register lof file...\n");`
372			`reg_log = $fopen("Registers.log","w");`
373
374			`end`
375
376			`endif //Ucode dump
377
378			`//-----------------------------------------------------------------------`
379			`ifdef DEBUG
380	72	diegovalve	wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
381			wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
382
383			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
384			`(`
385			`.Clock( Clock ),`
386			`.Reset( Reset),`
387			`.Enable( wLatchNow ),`
388			`.D( iSource1[95:64] ),`
389			`.Q(wALUChannelX1)`
390			`);`
391			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
392			`(`
393			`.Clock( Clock ),`
394			`.Reset( Reset),`
395			`.Enable( wLatchNow ),`
396			`.D( iSource1[63:32] ),`
397			`.Q(wALUChannelY1)`
398			`);`
399			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
400			`(`
401			`.Clock( Clock ),`
402			`.Reset( Reset),`
403			`.Enable( wLatchNow ),`
404			`.D( iSource1[31:0] ),`
405			`.Q(wALUChannelZ1)`
406			`);`
407
408
409			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
410			`(`
411			`.Clock( Clock ),`
412			`.Reset( Reset),`
413			`.Enable( wLatchNow ),`
414			`.D( iSource0[95:64] ),`
415			`.Q(wALUChannelX2)`
416			`);`
417			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
418			`(`
419			`.Clock( Clock ),`
420			`.Reset( Reset),`
421			`.Enable( wLatchNow ),`
422			`.D( iSource0[63:32] ),`
423			`.Q(wALUChannelY2)`
424			`);`
425			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
426			`(`
427			`.Clock( Clock ),`
428			`.Reset( Reset),`
429			`.Enable( wLatchNow ),`
430			`.D( iSource0[31:0] ),`
431			`.Q(wALUChannelZ2)`
432			`);`
433
434
435	26	diegovalve	`always @ (posedge iDecodeDone)`
436			`begin`
437			`LOGME"IP:%d", iDebug_CurrentIP);
438			`end`
439
440			`always @ (negedge Clock )`
441			`begin`
442			`if ( iALUOutputReady )`
443			`begin`
444
445
446			`if (iBranchTaken)`
447			`LOGME"<BT>");
448
449			`if (iBranchNotTaken )`
450			`LOGME"<BNT>");
451
452			`if (oRAMWriteEnable)`
453			`LOGME"<WE>");
454
455			`LOGME "(%dns ",$time);
456			`case ( oALUOperation )`
457			`RETURN: `LOGME"RETURN");
458			`ADD: `LOGME"ADD");
459			`SUB: `LOGME"SUB");
460			`DIV: `LOGME"DIV");
461			`MUL: `LOGME"MUL");
462			`MAG: `LOGME"MAG");
463	63	diegovalve	`JGX: `LOGME"JGX");
464			`JLX: `LOGME"JLX");
465	26	diegovalve	`JGEX: `LOGME"JGEX");
466			`JGEY: `LOGME"JGEY");
467			`JGEZ: `LOGME"JGEZ");
468			`JLEX: `LOGME"JLEX");
469			`JLEY: `LOGME"JLEY");
470			`JLEZ: `LOGME"JLEZ");
471			`JMP: `LOGME"JMP");
472			`ZERO: `LOGME"ZERO");
473			`JNEX: `LOGME"JNEX");
474			`JNEY: `LOGME"JNEY");
475			`JNEZ: `LOGME"JNEZ");
476			`JEQX: `LOGME"JEQX");
477			`JEQY: `LOGME"JEQY");
478			`JEQZ: `LOGME"JEQZ");
479			`CROSS: `LOGME"CROSS");
480			`DOT: `LOGME"DOT");
481			`SETX: `LOGME"SETX");
482			`SETY: `LOGME"SETY");
483			`SETZ: `LOGME"SETZ");
484			`NOP: `LOGME"NOP");
485			`COPY: `LOGME"COPY");
486			`INC: `LOGME"INC");
487			`DEC: `LOGME"DEC");
488			`MOD: `LOGME"MOD");
489			`FRAC: `LOGME"FRAC");
490			`NEG: `LOGME"NEG");
491			`SWIZZLE3D: `LOGME"SWIZZLE3D");
492			`MULP: `LOGME"MULP");
493			`XCHANGEX: `LOGME"XCHANGEX");
494			`IMUL: `LOGME"IMUL");
495			`UNSCALE: `LOGME"UNSCALE");
496			`INCX: `LOGME"INCX");
497			`INCY: `LOGME"INCY");
498			`INCZ: `LOGME"INCZ");
499			`DEBUG_PRINT:
500			`begin`
501			`LOGME"DEBUG_PRINT");
502
503			`end`
504			`default:`
505			`begin`
506			`LOGME"********ERROR UNKNOWN OP*******");
507			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
508			`// $stop();`
509			`end`
510			`endcase`
511
512			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
513			`oRAMWriteAddress,`
514	72	diegovalve	`wALUChannelX1,wALUChannelY1,wALUChannelZ1,`
515			`wALUChannelX2,wALUChannelY2,wALUChannelZ2`
516	26	diegovalve
517			`);`
518
519			if (oALUOperation == `RETURN)
520			`LOGME"\n\n\n");
521
522			`end`
523			`end //always`
524
525			`always @ ( negedge Clock )`
526			`begin`
527			`if ( iALUOutputReady )`
528			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
529			`end //always`
530			`endif
531
532			`endmodule`