OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [CORES/] [TOP/] [Theia_Core.v] - Blame information for rev 143

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 76 diegovalve
/**********************************************************************************
2
Theia, Ray Cast Programable graphic Processing Unit.
3
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
4
 
5
This program is free software; you can redistribute it and/or
6
modify it under the terms of the GNU General Public License
7
as published by the Free Software Foundation; either version 2
8
of the License, or (at your option) any later version.
9
 
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14
 
15
You should have received a copy of the GNU General Public License
16
along with this program; if not, write to the Free Software
17
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18
 
19
***********************************************************************************/
20
 
21
/**********************************************************************************
22
Description:
23
 This is the top level block for THEIA.
24
 THEIA core has 5 main logical blocks called Units.
25
 This module implements the interconections between the Units.
26
 
27
 Units:
28
  > EXE: Mananges execution logic for the SHADERS.
29
  > GEO: Manages geometry data structures.
30
  > IO: Input/Output (Wishbone).
31
  > MEM: Internal memory, separate for Instructions and data.
32
  > CONTROL: Main control Finite state machine.
33
 
34
 Internal Buses:
35
        THEIA has separate instruction and data buses.
36
        THEIA avoids using tri-state buses by having separate input/output
37
        for each bus.
38
        There are 2 separate data buses since the Data memory
39
        has a Dual read channel.
40
   Please see the MEM unit chapter in the documentation for more details.
41
 
42
 External Buses:
43
        External buses are managed by the IO Unit.
44
        External buses follow the wishbone protocol.
45
        Please see the IO unit chapter in the documentation for more details.
46
**********************************************************************************/
47
 
48
`timescale 1ns / 1ps
49
`include "aDefinitions.v"
50
 
51
module THEIACORE
52
(
53
 
54
input wire                    CLK_I,    //Input clock
55
input wire                    RST_I,    //Input reset
56
//Theia Interfaces
57
input wire                    MST_I,    //Master signal, THEIA enters configuration mode
58
                                       //when this gets asserted (see documentation)
59
//Wish Bone Interface
60
input wire [`WB_WIDTH-1:0]    DAT_I,     //Input data bus  (Wishbone)
61
output wire [`WB_WIDTH-1:0]   DAT_O,     //Output data bus (Wishbone)
62
input wire                    ACK_I,    //Input ack
63
output wire                   ACK_O,    //Output ack
64
output wire [`WB_WIDTH-1:0]   ADR_O,     //Output address
65
input wire [`WB_WIDTH-1:0]    ADR_I,     //Input address
66
output wire                   WE_O,             //Output write enable
67
input wire                    WE_I,    //Input write enable
68
output wire                   STB_O,    //Strobe signal, see wishbone documentation
69
input wire                    STB_I,    //Strobe signal, see wishbone documentation
70
output wire                   CYC_O,    //Bus cycle signal, see wishbone documentation
71
input wire                    CYC_I,   //Bus cycle signal, see wishbone documentation
72
output wire     [1:0]             TGC_O,   //Bus cycle tag, see THEAI documentation
73
input wire [1:0]              TGA_I,   //Input address tag, see THEAI documentation
74
output wire [1:0]             TGA_O,   //Output address tag, see THEAI documentation
75 105 diegovalve
input wire      [1:0]             TGC_I,   //Bus cycle tag, see THEAI documentation
76
input wire                    GNT_I,   //Bus arbiter 'Granted' signal, see THEAI documentation
77 76 diegovalve
input wire                    RENDREN_I,
78 105 diegovalve
 
79 143 diegovalve
output wire                  HDL_O,             //Data Latched
80
input wire                   HDLACK_I, //Data Latched ACK
81 105 diegovalve
input wire                   STDONE_I,          //Scene traverse complete
82
input wire                   HDA_I,
83
output wire                  RCOMMIT_O,
84
 
85
output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
86
output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
87
output wire                                              OMEM_WE_O,
88
 
89
input wire                  TMEM_ACK_I,
90
input wire [`WB_WIDTH-1:0]  TMEM_DAT_I ,
91
output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
92
output wire                 TMEM_WE_O,
93
output wire                 TMEM_STB_O,
94
output wire                 TMEM_CYC_O,
95
input wire                  TMEM_GNT_I,
96
 
97
`ifdef DEBUG
98
input wire[`MAX_CORES-1:0]    iDebug_CoreID,
99 76 diegovalve
`endif
100
//Control Register
101 105 diegovalve
input wire [15:0]                         CREG_I,
102 76 diegovalve
output wire                   DONE_O
103
 
104
 
105
);
106 105 diegovalve
 
107
//When we flip the SMEM, this means we are ready to receive more data
108 143 diegovalve
assign HDL_O = wCU2_FlipMem;
109 76 diegovalve
 
110
//Alias this signals
111
wire Clock,Reset;
112
assign Clock = CLK_I;
113
assign Reset = RST_I;
114 105 diegovalve
 
115 82 diegovalve
wire                              wIO_Busy;
116 76 diegovalve
wire [`DATA_ROW_WIDTH-1:0]                        wEXE_2__MEM_WriteData;
117
wire [`DATA_ROW_WIDTH-1:0]                        wUCODE_RAMBus;
118
wire [`DATA_ADDRESS_WIDTH-1:0]    wEXE_2__MEM_wDataWriteAddress;
119
wire                              w2IO__AddrIsImm;
120
wire [`DATA_ADDRESS_WIDTH-1:0]    wUCODE_RAMAddress;
121
wire [`DATA_ADDRESS_WIDTH-1:0]    w2IO__Adr_O_Pointer;
122
wire [`DATA_ADDRESS_WIDTH-1:0]    wGEO2_IO__Adr_O_Pointer;
123
wire                                                                             wEXE_2__DataWriteEnable;
124
wire                                                                             wUCODE_RAMWriteEnable;
125 117 diegovalve
//wire [2:0]                                                             RamBusOwner;
126 76 diegovalve
//Unit intercoanection wires
127
 
128
wire                                                                            wCU2__MicrocodeExecutionDone;
129
wire [`ROM_ADDRESS_WIDTH-1:0]            InitialCodeAddress;
130
wire [`ROM_ADDRESS_WIDTH-1:0]            wInstructionPointer1,wInstructionPointer2;
131
wire [`INSTRUCTION_WIDTH-1:0]    wEncodedInstruction1,wEncodedInstruction2,wIO2_MEM__ExternalInstruction;
132
wire                                                                            wCU2__ExecuteMicroCode;
133
wire  [`ROM_ADDRESS_WIDTH-1:0]   wIO2_MEM__InstructionWriteAddr;
134
wire [95:0]                                                      wMEM_2__EXE_DataRead0, wMEM_2__EXE_DataRead1,wMEM_2__IO_DataRead0, wMEM_2__IO_DataRead1;
135
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE_2__MEM_DataReadAddress0,wEXE_2__MEM_DataReadAddress1;
136
wire [`DATA_ADDRESS_WIDTH-1:0]   wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
137
 
138
 
139
wire [`WIDTH-1:0]                                        w2IO__AddressOffset;
140
wire [`DATA_ADDRESS_WIDTH-1:0]   w2IO__DataWriteAddress;
141
wire                                                                            w2IO__Store;
142
wire                                                                            w2IO__EnableWBMaster;
143
 
144
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO2_MEM__DataWriteAddress;
145
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO_2_MEM__DataReadAddress0;
146
wire [`DATA_ROW_WIDTH-1:0]               wIO2_MEM__Bus;
147
wire [`WIDTH-1:0]                                        wIO2_MEM__Data;
148
wire [`WIDTH-1:0]                                        wIO2_WBM__Address;
149
wire                                                                            wIO2_MEM__DataWriteEnable;
150
wire                                                                            wIO2__Done;
151
wire                                                                            wCU2_GEO__GeometryFetchEnable;
152
wire                                                                            wIFU2__MicroCodeReturnValue;
153
wire                                                                            wCU2_BCU__ACK;
154
wire                                                                            wGEO2_CU__RequestAABBIU;
155
wire                                                                            wGEO2_CU__RequestBIU;
156
wire                             wGEO2_CU__RequestTCC;
157
wire                                                                            wGEO2_CU__GeometryUnitDone;
158
wire                                                                            wGEO2_CU__Sync;
159
wire                                                                            wEXE2__uCodeDone;
160
wire                                                                            wEXE2_IFU__EXEBusy;
161
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE2_IDU_DataFordward_LastDestination;
162
wire                                                                            wALU2_EXE__BranchTaken;
163
wire                                                                            wALU2_IFU_BranchNotTaken;
164
wire                                                                            w2IO__SetAddress;
165
wire                                                                            wIDU2_IFU__IDUBusy;
166
//Control Registe wires
167
wire[15:0]                                                               wCR2_ControlRegister;
168
wire                                                                            wCR2_TextureMappingEnabled;
169
wire                             wGEO2_CU__TFFDone;
170
wire                             wCU2_GEO__TriggerTFF;
171
wire                             wIO2_MEM_InstructionWriteEnable;
172
wire                             wCU2_IO__WritePixel;
173
wire                             wGEO2_IO__AddrIsImm;
174
wire[31:0]                       wGEO2_IO__AddressOffset;
175
wire                             wGEO2_IO__EnableWBMaster;
176
wire                             wGEO2_IO__SetAddress;
177
wire[`WIDTH-1:0]                 wGEO2__CurrentPitch,wCU2_GEO_Pitch;
178
wire                             wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
179 105 diegovalve
 
180
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteAddress;
181
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteData;
182
wire wEXE_2__IO_OMEMWriteEnable;
183
 
184
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_TMEMAddress;
185
wire [`DATA_ROW_WIDTH-1:0] wIO_2_EXE__TMEMData;
186
wire wIO_2_EXE__DataAvailable;
187
wire wEXE_2_IO__DataRequest;
188
 
189 76 diegovalve
wire wCU2_FlipMemEnabled;
190
wire w2MEM_FlipMemory;
191
 
192
`ifdef DEBUG
193
        wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
194
`endif
195
//--------------------------------------------------------
196
 
197
 
198
assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
199
wire wCU2_FlipMem;
200
//--------------------------------------------------------
201
//Control Unit Instance
202
        ControlUnit CU
203
        (
204
           .Clock(Clock),
205
                .Reset(Reset),
206
                .oFlipMemEnabled(                   wCU2_FlipMemEnabled            ),
207
                .oFlipMem(                          wCU2_FlipMem                   ),
208
                .iControlRegister(                  wCR2_ControlRegister           ),
209 117 diegovalve
                //.oRamBusOwner(                      RamBusOwner                    ),
210 76 diegovalve
                .oGFUEnable(                        wCU2_GEO__GeometryFetchEnable  ),
211
                .iTriggerAABBIURequest(             wGEO2_CU__RequestAABBIU        ),
212
                .iTriggerBIURequest(                wGEO2_CU__RequestBIU           ),
213
                .iTriggertTCCRequest(               wGEO2_CU__RequestTCC           ),
214
                .oUCodeEnable(                      wCU2__ExecuteMicroCode         ),
215
                .oCodeInstructioPointer(           InitialCodeAddress             ),
216
                .iUCodeDone(                        wCU2__MicrocodeExecutionDone   ),
217
                .iIODone(                           wIO2__Done                     ),
218
                .oIOWritePixel(                     wCU2_IO__WritePixel            ),
219
                .iUCodeReturnValue(                 wIFU2__MicroCodeReturnValue    ),
220
                .iGEOSync(                          wGEO2_CU__Sync                 ),
221
                .iTFFDone(                          wGEO2_CU__TFFDone              ),
222
                .oTriggerTFF(                       wCU2_GEO__TriggerTFF           ),
223
                .MST_I(                             MST_I                          ),
224
                .oSetCurrentPitch(                  wCU2_GEO__SetPitch             ),
225 105 diegovalve
                .iGFUDone(                          wGEO2_CU__GeometryUnitDone     ),
226 76 diegovalve
                .iRenderEnable(                     RENDREN_I                      ),
227 105 diegovalve
                .iSceneTraverseComplete(            STDONE_I                       ),
228
                .oResultCommited(                   RCOMMIT_O                      ),
229
                .iHostDataAvailable(                HDA_I                                                                        ),
230 143 diegovalve
                .iHostAckDataRead(                  HDLACK_I                       ),
231 105 diegovalve
 
232
 
233
                `ifdef DEBUG
234
                .iDebug_CoreID( iDebug_CoreID ),
235
                `endif
236 76 diegovalve
                .oDone(                             DONE_O                         )
237
 
238
        );
239
 
240
 
241
 
242
 
243
//--------------------------------------------------------      
244
 
245
//assign w2MEM_FlipMemory =  (wCU2__ExecuteMicroCode | wCU2_FlipMem ) & wCU2_FlipMemEnabled;
246
assign w2MEM_FlipMemory =  wCU2_FlipMem  & wCU2_FlipMemEnabled;
247
MemoryUnit MEM
248
(
249
.Clock(Clock),
250
.Reset(Reset),
251
 
252
.iFlipMemory( w2MEM_FlipMemory ),
253
 
254
//Data Bus to/from EXE
255
.iDataReadAddress1_EXE(       wEXE_2__MEM_DataReadAddress0        ),
256
.iDataReadAddress2_EXE(       wEXE_2__MEM_DataReadAddress1        ),
257
.oData1_EXE(                  wMEM_2__EXE_DataRead0               ),
258
.oData2_EXE(                  wMEM_2__EXE_DataRead1               ),
259
.iDataWriteEnable_EXE(        wEXE_2__DataWriteEnable          ),
260
.iDataWriteAddress_EXE(       wEXE_2__MEM_wDataWriteAddress        ),
261
.iData_EXE(                   wEXE_2__MEM_WriteData          ),
262
 
263
//Data Bus to/from IO
264
 
265
.iDataReadAddress1_IO(       wIO_2_MEM__DataReadAddress0        ),
266
.iDataReadAddress2_IO(       wIO_2_MEM__DataReadAddress1        ),
267
.oData1_IO(                  wMEM_2__IO_DataRead0               ),
268
.oData2_IO(                  wMEM_2__IO_DataRead1               ),
269
.iDataWriteEnable_IO(        wIO2_MEM__DataWriteEnable          ),
270
.iDataWriteAddress_IO(       wIO2_MEM__DataWriteAddress        ),
271 105 diegovalve
.iData_IO(                   wIO2_MEM__Bus          ),
272
 
273
`ifdef DEBUG
274
.iDebug_CoreID( iDebug_CoreID ),
275
`endif
276 76 diegovalve
 
277
 
278
//Instruction Bus
279
.iInstructionReadAddress1(  wInstructionPointer1             ),
280
.iInstructionReadAddress2(  wInstructionPointer2             ),
281
.oInstruction1(             wEncodedInstruction1             ),
282
.oInstruction2(             wEncodedInstruction2             ),
283
.iInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
284
.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr  ),
285
.iInstruction(             wIO2_MEM__ExternalInstruction   ),
286
.iControlRegister(         CREG_I                          ),
287
.oControlRegister(         wCR2_ControlRegister            )
288
 
289
);
290
 
291
////--------------------------------------------------------
292
 
293
 
294
ExecutionUnit EXE
295
(
296
 
297
.Clock( Clock),
298
.Reset( Reset ),
299
.iInitialCodeAddress(    InitialCodeAddress     ),
300
.iInstruction1(          wEncodedInstruction1      ),
301
.iInstruction2(          wEncodedInstruction2      ),
302
.oInstructionPointer1(   wInstructionPointer1    ),
303
.oInstructionPointer2(   wInstructionPointer2    ),
304
.iDataRead0(             wMEM_2__EXE_DataRead0             ),
305
.iDataRead1(             wMEM_2__EXE_DataRead1             ),
306
.iTrigger(               wCU2__ExecuteMicroCode ),
307
.oDataReadAddress0( wEXE_2__MEM_DataReadAddress0 ),
308
.oDataReadAddress1( wEXE_2__MEM_DataReadAddress1 ),
309
.oDataWriteEnable(  wEXE_2__DataWriteEnable  ),
310
.oDataWriteAddress( wEXE_2__MEM_wDataWriteAddress      ),
311
.oDataBus(          wEXE_2__MEM_WriteData          ),
312 105 diegovalve
.oReturnCode(       wIFU2__MicroCodeReturnValue ),
313
/**************/
314
.oOMEMWriteAddress(   wEXE_2__IO_WriteAddress ),
315
.oOMEMWriteData(      wEXE_2__IO_WriteData    ),
316
.oOMEMWriteEnable(  wEXE_2__IO_OMEMWriteEnable ),
317
 
318
.oTMEMReadAddress(   wEXE_2__IO_TMEMAddress   ),
319
.iTMEMReadData(      wIO_2_EXE__TMEMData      ),
320
.iTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
321
.oTMEMDataRequest(   wEXE_2_IO__DataRequest   ),
322
/**************/
323
`ifdef DEBUG
324
.iDebug_CoreID( iDebug_CoreID ),
325 76 diegovalve
`endif
326
.oDone(             wCU2__MicrocodeExecutionDone )
327
 
328
);
329
 
330
////--------------------------------------------------------
331
wire wGEO2__RequestingTextures;
332
wire w2IO_WriteBack_Set;
333
 
334
assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
335
//---------------------------------------------------------------------------------------------------
336
wire[`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress1;
337
assign wEXE_2__MEM_DataReadAddress1 = (wCU2_IO__WritePixel == 0) ?  wUCODE_RAMReadAddress1 : wIO_2_MEM__DataReadAddress1;
338
assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
339 105 diegovalve
assign w2IO__AddrIsImm       = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm       : 1'b0;
340
assign w2IO__AddressOffset   = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset   : 32'b0;
341
assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_ADDR_O;
342
//assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `CREG_PIXEL_2D_INITIAL_POSITION; 
343 76 diegovalve
 
344
wire w2IO_MasterCycleType;
345
assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
346
 
347 105 diegovalve
 
348
 
349
assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
350
 
351
 
352 76 diegovalve
IO_Unit IO
353
(
354
 .Clock(               Clock                            ),
355
 .Reset(               Reset                            ),
356 143 diegovalve
 .iEnable(           1'b0 ),// w2IO__EnableWBMaster              ),
357 76 diegovalve
 .iBusCyc_Type(         w2IO_MasterCycleType            ),
358
 
359 143 diegovalve
 .iStore(              1'b1),//w2IO__Store                      ),
360 76 diegovalve
 .iAdr_DataWriteBack(    w2IO__DataWriteAddress         ),
361
 .iAdr_O_Set(      w2IO__SetAddress                     ),
362
 .iAdr_O_Imm(       w2IO__AddressOffset                 ),
363
 .iAdr_O_Type(      w2IO__AddrIsImm                     ),
364 105 diegovalve
 .iAdr_O_Pointer(  w2IO__Adr_O_Pointer                  ),
365 76 diegovalve
 .iReadDataBus(        wMEM_2__IO_DataRead0                       ),
366 105 diegovalve
 .iReadDataBus2(        wMEM_2__IO_DataRead1                       ),
367
 .iDat_O_Pointer(     `OREG_PIXEL_COLOR                 ),
368 76 diegovalve
 
369 105 diegovalve
 
370 76 diegovalve
 .oDataReadAddress(    wIO_2_MEM__DataReadAddress0      ),
371
 .oDataReadAddress2(   wIO_2_MEM__DataReadAddress1       ),
372
 .oDataWriteAddress(   wIO2_MEM__DataWriteAddress    ),
373
 .oDataBus(               wIO2_MEM__Bus                 ),
374
 .oInstructionBus(     wIO2_MEM__ExternalInstruction    ),
375
 
376
 .oDataWriteEnable(         wIO2_MEM__DataWriteEnable    ),
377
 .oData(                    wIO2_MEM__Data                       ),
378
 .oInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
379
 .oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
380
 .iWriteBack_Set( w2IO_WriteBack_Set ),
381 82 diegovalve
 .oBusy(                      wIO_Busy                  ),
382 76 diegovalve
 .oDone(               wIO2__Done                       ),
383 105 diegovalve
 /**********/
384
 .iOMEM_WriteAddress(   wEXE_2__IO_WriteAddress         ),
385
 .iOMEM_WriteData(      wEXE_2__IO_WriteData            ),
386
 .iOMEM_WriteEnable(    wEXE_2__IO_OMEMWriteEnable    ),
387
 .OMEM_DAT_O( OMEM_DAT_O ),
388
 .OMEM_ADR_O( OMEM_ADR_O ),
389
 .OMEM_WE_O( OMEM_WE_O ),
390
 
391
 
392
 .oTMEMReadData(      wIO_2_EXE__TMEMData      ),
393
 .iTMEMDataRequest(   wEXE_2_IO__DataRequest   ),
394
 .iTMEMReadAddress(   wEXE_2__IO_TMEMAddress   ),
395
 .oTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
396
 
397
.TMEM_ACK_I( TMEM_ACK_I ),
398
.TMEM_DAT_I( TMEM_DAT_I ),
399
.TMEM_ADR_O( TMEM_ADR_O ),
400
.TMEM_WE_O(  TMEM_WE_O  ),
401
.TMEM_STB_O( TMEM_STB_O ),
402
.TMEM_CYC_O( TMEM_CYC_O ),
403
.TMEM_GNT_I( TMEM_GNT_I ),
404
 
405
 /**********/
406 76 diegovalve
 .MST_I( MST_I ),
407
  //Wish Bone Interface
408
.DAT_I( DAT_I ),
409
.DAT_O( DAT_O ),
410
.ACK_I( ACK_I & GNT_I ),
411
.ACK_O( ACK_O ),
412
.ADR_O( ADR_O ),
413
.ADR_I( ADR_I ),
414
.WE_O(  WE_O  ),
415
.WE_I(  WE_I  ),
416
.STB_O( STB_O ),
417
.STB_I( STB_I ),
418
.CYC_O( CYC_O ),
419
.TGA_I( TGA_I ),
420 105 diegovalve
.CYC_I( CYC_I ),
421 76 diegovalve
.GNT_I( GNT_I ),
422
.TGC_O( TGC_O )
423
 
424
 
425
);
426
//---------------------------------------------------------------------------------------------------
427
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.