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[/] [theia_gpu/] [trunk/] [rtl/] [Collaterals.v] - Blame information for rev 154

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
//------------------------------------------------
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
        (
        input wire Clock,
        input wire Clear,
        input wire [SIZE-1:0] D,
        output reg [SIZE-1:0] Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 0;
      else
        Q = D;
    end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Enable,
        input wire [SIZE-1:0]    D,
        output reg [SIZE-1:0]    Q
);
 
 
always @ (posedge Clock)
begin
        if ( Reset )
                Q <= `WIDTH'b0;
        else
        begin
                if (Enable)
                        Q <= D;
        end
 
end//always
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
 
  always @(posedge Clock )
  begin
      if (Reset)
        Q <= Initial;
      else
                begin
                if (Enable)
                        Q <= Q + 1;
 
                end
  end
 
endmodule
 
//----------------------------------------------------------------------
 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
 (
 input wire [SEL_WIDTH-1:0] Sel,
 input wire  En,
 output wire [OUTPUT_WIDTH-1:0] O
 );
 
reg[OUTPUT_WIDTH-1:0] shift;
 
always @ ( * )
begin
        if (~En)
                shift = 1;
        else
                shift = (1 <<   Sel);
 
 
end
 
assign O = ( ~En ) ? 0 : shift ;
 
//assign O = En & (1 << Sel);
 
endmodule
 
//----------------------------------------------------------------------
 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 (
 input wire [1:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,I4,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                2'b11: O1 = I4;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
 
//--------
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                begin
                        if (tmp[SIZE-1])
                        begin
                                tmp <= Initial;
                        end
                        else
                        begin
                                tmp <= tmp << 1;
                        end
                end
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
 (
 input wire [2:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      3'b001: O1 = I1;
      3'b010: O1 = I2;
                3'b100: O1 = I3;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
//------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset || tmp[SIZE-1])
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//-----------------------------------------------------------
/*
        Sorry forgot how this flop is called.
        Any way Truth table is this
 
        Q       S       Q_next R
 
 
        1       0        1                0
        1       1       1                0
        X       X       0                 1
 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
        gets another S = 1, it keeps the output to 1.
*/
module FFToggleOnce_1Bit
(
        input wire Clock,
        input wire Reset,
        input wire Enable,
        input wire S,
        output reg Q
 
);
 
 
reg Q_next;
 
always @ (negedge Clock)
begin
        Q <= Q_next;
end
 
always @ ( posedge Clock )
begin
        if (Reset)
                Q_next <= 0;
        else if (Enable)
                Q_next <= (S && !Q) || Q;
        else
                Q_next <= Q;
end
endmodule
 
//-----------------------------------------------------------
module UpCounter_16E
(
input wire Clock,
input wire Reset,
input wire [15:0] Initial,
input wire Enable,
output wire [15:0] Q
);
        reg [15:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 1'b1;
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_32
(
input wire Clock,
input wire Reset,
input wire [31:0] Initial,
input wire Enable,
output wire [31:0] Q
);
        reg [31:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
                begin
         Temp = Initial;
                end
      else
                begin
                        if (Enable)
                        begin
                                Temp =  Temp + 1'b1;
                        end
                end
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_3
(
input wire Clock,
input wire Reset,
input wire [2:0] Initial,
input wire Enable,
output wire [2:0] Q
);
        reg [2:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 3'b1;
  end
        assign Q = Temp;
 
endmodule
 
 
module FFD32_POSEDGE
(
        input wire Clock,
        input wire[31:0] D,
        output reg[31:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
 
//------------------------------------------------
module MUXFULLPARALELL_96bits_2SEL
 (
 input wire Sel,
 input wire [95:0]I1, I2,
 output reg [95:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
 
module MUXFULLPARALELL_16bits_2SEL_X
 (
 input wire [1:0] Sel,
 input wire [15:0]I1, I2, I3,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                default: O1 = 16'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
 (
 input wire Sel,
 input wire [15:0]I1, I2,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
//--------------------------------------------------------------
 
  module FFT1
  (
   input wire D,
   input wire Clock,
   input wire Reset ,
   output reg Q
 );
 
  always @ ( posedge Clock or posedge Reset )
  begin
 
        if (Reset)
        begin
    Q <= 1'b0;
   end
        else
        begin
                if (D)
                        Q <=  ! Q;
        end
 
  end//always
 
 endmodule
//--------------------------------------------------------------

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[/] [theia_gpu/] [trunk/] [rtl/] [Collaterals.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	152	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`//------------------------------------------------`
23			module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
24			`(`
25			`input wire Clock,`
26			`input wire Clear,`
27			`input wire [SIZE-1:0] D,`
28			`output reg [SIZE-1:0] Q`
29			`);`
30
31			`always @(posedge Clock or posedge Clear)`
32			`begin`
33			`if (Clear)`
34			`Q = 0;`
35			`else`
36			`Q = D;`
37			`end`
38			`endmodule`
39			`//----------------------------------------------------`
40			module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
41			`(`
42			`input wire Clock,`
43			`input wire Reset,`
44			`input wire Enable,`
45			`input wire [SIZE-1:0] D,`
46			`output reg [SIZE-1:0] Q`
47			`);`
48
49
50			`always @ (posedge Clock)`
51			`begin`
52			`if ( Reset )`
53			Q <= `WIDTH'b0;
54			`else`
55			`begin`
56			`if (Enable)`
57			`Q <= D;`
58			`end`
59
60			`end//always`
61
62			`endmodule`
63			`//------------------------------------------------`
64			module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
65			`(`
66			`input wire Clock, Reset,`
67			`input wire [SIZE-1:0] Initial,`
68			`input wire Enable,`
69			`output reg [SIZE-1:0] Q`
70			`);`
71
72
73			`always @(posedge Clock )`
74			`begin`
75			`if (Reset)`
76			`Q <= Initial;`
77			`else`
78			`begin`
79			`if (Enable)`
80			`Q <= Q + 1;`
81
82			`end`
83			`end`
84
85			`endmodule`
86
87			`//----------------------------------------------------------------------`
88
89			`module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )`
90			`(`
91			`input wire [SEL_WIDTH-1:0] Sel,`
92			`input wire En,`
93			`output wire [OUTPUT_WIDTH-1:0] O`
94			`);`
95
96			`reg[OUTPUT_WIDTH-1:0] shift;`
97
98			`always @ ( * )`
99			`begin`
100			`if (~En)`
101			`shift = 1;`
102			`else`
103			`shift = (1 << Sel);`
104
105
106			`end`
107
108			`assign O = ( ~En ) ? 0 : shift ;`
109
110			`//assign O = En & (1 << Sel);`
111
112			`endmodule`
113
114			`//----------------------------------------------------------------------`
115
116			module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
117			`(`
118			`input wire [1:0] Sel,`
119			`input wire [SIZE-1:0]I1, I2, I3,I4,`
120			`output reg [SIZE-1:0] O1`
121			`);`
122
123			`always @( * )`
124
125			`begin`
126
127			`case (Sel)`
128
129			`2'b00: O1 = I1;`
130			`2'b01: O1 = I2;`
131			`2'b10: O1 = I3;`
132			`2'b11: O1 = I4;`
133			`default: O1 = SIZE-1'b0;`
134
135			`endcase`
136
137			`end`
138
139			`endmodule`
140
141			`//--------`
142			module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
143			`( input wire Clock,`
144			`input wire Reset,`
145			`input wire[SIZE-1:0] Initial,`
146			`input wire Enable,`
147			`output wire[SIZE-1:0] O`
148			`);`
149
150			`reg [SIZE-1:0] tmp;`
151
152
153			`always @(posedge Clock)`
154			`begin`
155			`if (Reset)`
156			`tmp <= Initial;`
157			`else`
158			`begin`
159			`if (Enable)`
160			`begin`
161			`if (tmp[SIZE-1])`
162			`begin`
163			`tmp <= Initial;`
164			`end`
165			`else`
166			`begin`
167			`tmp <= tmp << 1;`
168			`end`
169			`end`
170			`end`
171			`end`
172
173
174			`assign O = tmp;`
175			`endmodule`
176			`//------------------------------------------------`
177			module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
178			`(`
179			`input wire [2:0] Sel,`
180			`input wire [SIZE-1:0]I1, I2, I3,`
181			`output reg [SIZE-1:0] O1`
182			`);`
183
184			`always @( * )`
185
186			`begin`
187
188			`case (Sel)`
189
190			`3'b001: O1 = I1;`
191			`3'b010: O1 = I2;`
192			`3'b100: O1 = I3;`
193			`default: O1 = SIZE-1'b0;`
194
195			`endcase`
196
197			`end`
198
199			`endmodule`
200			`//------------------------------------------------`
201			module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
202			`( input wire Clock,`
203			`input wire Reset,`
204			`input wire[SIZE-1:0] Initial,`
205			`input wire Enable,`
206			`output wire[SIZE-1:0] O`
207			`);`
208
209			`reg [SIZE-1:0] tmp;`
210
211
212			`always @(posedge Clock)`
213			`begin`
214			`if (Reset)`
215			`tmp <= Initial;`
216			`else`
217			`begin`
218			`if (Enable)`
219			`tmp <= tmp << 1;`
220			`end`
221			`end`
222
223
224			`assign O = tmp;`
225			`endmodule`
226			`//------------------------------------------------`
227			`//------------------------------------------------`
228			module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
229			`( input wire Clock,`
230			`input wire Reset,`
231			`input wire[SIZE-1:0] Initial,`
232			`input wire Enable,`
233			`output wire[SIZE-1:0] O`
234			`);`
235
236			`reg [SIZE-1:0] tmp;`
237
238
239			`always @(posedge Clock)`
240			`begin`
241			`if (Reset \|\| tmp[SIZE-1])`
242			`tmp <= Initial;`
243			`else`
244			`begin`
245			`if (Enable)`
246			`tmp <= tmp << 1;`
247			`end`
248			`end`
249
250
251			`assign O = tmp;`
252			`endmodule`
253			`//-----------------------------------------------------------`
254			`/*`
255			`Sorry forgot how this flop is called.`
256			`Any way Truth table is this`
257
258			`Q S Q_next R`
259
260
261			`1 0 1 0`
262			`1 1 1 0`
263			`X X 0 1`
264
265			`The idea is that it toggles from 0 to 1 when S = 1, but if it`
266			`gets another S = 1, it keeps the output to 1.`
267			`*/`
268			`module FFToggleOnce_1Bit`
269			`(`
270			`input wire Clock,`
271			`input wire Reset,`
272			`input wire Enable,`
273			`input wire S,`
274			`output reg Q`
275
276			`);`
277
278
279			`reg Q_next;`
280
281			`always @ (negedge Clock)`
282			`begin`
283			`Q <= Q_next;`
284			`end`
285
286			`always @ ( posedge Clock )`
287			`begin`
288			`if (Reset)`
289			`Q_next <= 0;`
290			`else if (Enable)`
291			`Q_next <= (S && !Q) \|\| Q;`
292			`else`
293			`Q_next <= Q;`
294			`end`
295			`endmodule`
296
297			`//-----------------------------------------------------------`
298			`module UpCounter_16E`
299			`(`
300			`input wire Clock,`
301			`input wire Reset,`
302			`input wire [15:0] Initial,`
303			`input wire Enable,`
304			`output wire [15:0] Q`
305			`);`
306			`reg [15:0] Temp;`
307
308
309			`always @(posedge Clock or posedge Reset)`
310			`begin`
311			`if (Reset)`
312			`Temp = Initial;`
313			`else`
314			`if (Enable)`
315			`Temp = Temp + 1'b1;`
316			`end`
317			`assign Q = Temp;`
318
319			`endmodule`
320			`//-----------------------------------------------------------`
321			`module UpCounter_32`
322			`(`
323			`input wire Clock,`
324			`input wire Reset,`
325			`input wire [31:0] Initial,`
326			`input wire Enable,`
327			`output wire [31:0] Q`
328			`);`
329			`reg [31:0] Temp;`
330
331
332			`always @(posedge Clock or posedge Reset)`
333			`begin`
334			`if (Reset)`
335			`begin`
336			`Temp = Initial;`
337			`end`
338			`else`
339			`begin`
340			`if (Enable)`
341			`begin`
342			`Temp = Temp + 1'b1;`
343			`end`
344			`end`
345			`end`
346			`assign Q = Temp;`
347
348			`endmodule`
349			`//-----------------------------------------------------------`
350			`module UpCounter_3`
351			`(`
352			`input wire Clock,`
353			`input wire Reset,`
354			`input wire [2:0] Initial,`
355			`input wire Enable,`
356			`output wire [2:0] Q`
357			`);`
358			`reg [2:0] Temp;`
359
360
361			`always @(posedge Clock or posedge Reset)`
362			`begin`
363			`if (Reset)`
364			`Temp = Initial;`
365			`else`
366			`if (Enable)`
367			`Temp = Temp + 3'b1;`
368			`end`
369			`assign Q = Temp;`
370
371			`endmodule`
372
373
374			`module FFD32_POSEDGE`
375			`(`
376			`input wire Clock,`
377			`input wire[31:0] D,`
378			`output reg[31:0] Q`
379			`);`
380
381			`always @ (posedge Clock)`
382			`Q <= D;`
383
384			`endmodule`
385
386			`//------------------------------------------------`
387			`module MUXFULLPARALELL_96bits_2SEL`
388			`(`
389			`input wire Sel,`
390			`input wire [95:0]I1, I2,`
391			`output reg [95:0] O1`
392			`);`
393
394
395
396			`always @( * )`
397
398			`begin`
399
400			`case (Sel)`
401
402			`1'b0: O1 = I1;`
403			`1'b1: O1 = I2;`
404
405			`endcase`
406
407			`end`
408
409			`endmodule`
410			`//------------------------------------------------`
411
412			`module MUXFULLPARALELL_16bits_2SEL_X`
413			`(`
414			`input wire [1:0] Sel,`
415			`input wire [15:0]I1, I2, I3,`
416			`output reg [15:0] O1`
417			`);`
418
419
420
421			`always @( * )`
422
423			`begin`
424
425			`case (Sel)`
426
427			`2'b00: O1 = I1;`
428			`2'b01: O1 = I2;`
429			`2'b10: O1 = I3;`
430			`default: O1 = 16'b0;`
431
432			`endcase`
433
434			`end`
435
436			`endmodule`
437			`//------------------------------------------------`
438			`module MUXFULLPARALELL_16bits_2SEL`
439			`(`
440			`input wire Sel,`
441			`input wire [15:0]I1, I2,`
442			`output reg [15:0] O1`
443			`);`
444
445
446
447			`always @( * )`
448
449			`begin`
450
451			`case (Sel)`
452
453			`1'b0: O1 = I1;`
454			`1'b1: O1 = I2;`
455
456			`endcase`
457
458			`end`
459
460			`endmodule`
461
462			`//--------------------------------------------------------------`
463
464			`module FFT1`
465			`(`
466			`input wire D,`
467			`input wire Clock,`
468			`input wire Reset ,`
469			`output reg Q`
470			`);`
471
472			`always @ ( posedge Clock or posedge Reset )`
473			`begin`
474
475			`if (Reset)`
476			`begin`
477			`Q <= 1'b0;`
478			`end`
479			`else`
480			`begin`
481			`if (D)`
482			`Q <= ! Q;`
483			`end`
484
485			`end//always`
486
487			`endmodule`
488			`//--------------------------------------------------------------`