URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [trunk/] [rtl/] [Module_ExecutionFSM.v] - Blame information for rev 210

Go to most recent revision | Details | Compare with Previous | View Log


`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define EXEU_AFTER_RESET                                                        0
`define EXEU_INITIAL_STATE                                              1
`define EXEU_WAIT_FOR_DECODE                                            2
`define EXEU_FETCH_DECODED_INST                                 3
`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
`define EXEU_WRITE_BACK_TO_RAM                                  5
`define EXEU_HANDLE_JUMP                                                        7
 
 
 
module ExecutionFSM
(
input wire                                                              Clock,
input wire                                                              Reset,
 
input   wire                                                                            iDecodeDone,
input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
//output        reg                                                                     ReadyForNextInstruction,
output wire                                                                     oJumpFlag                       ,
output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
output  wire                                                                    oRAMWriteEnable         ,
output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
output  wire                                                                    oExeLatchedValues,
output  reg                                                                             oBusy ,
 
//ALU ports and control signals
output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
output  wire                                                                                                    oTriggerALU,
 
input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
input wire                                                                                                              iALUOutputReady,
input   wire                                                                                                            iBranchTaken,
input wire                                                                                                              iBranchNotTaken,
 
 
`ifdef DEBUG
        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
        input wire [`MAX_CORES-1:0]         iDebug_CoreID,
`endif
//Data forward Signals
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
 
 
);
 
wire wLatchNow;
reg rInputLatchesEnabled;
 
//If ALU says jump, just pass along
assign oJumpFlag = iBranchTaken;
//JumpIP is the instruction destination (= oRAMWriteAddress)
assign oJumpIp = oRAMWriteAddress;
 
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
assign oExeLatchedValues = wLatchNow;
assign oTriggerALU = wLatchNow;
 
wire wOperationIsJump;
assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
`endif
 
 
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
 
assign oALUChannelX1 = iSource1[95:64];
assign oALUChannelY1 = iSource1[63:32];
assign oALUChannelZ1 = iSource1[31:0];
 
assign oALUChannelX2 = iSource0[95:64];
assign oALUChannelY2 = iSource0[63:32];
assign oALUChannelZ2 = iSource0[31:0];
 
/*
FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[95:64] ),
        .Q( oALUChannelX1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[63:32] ),
        .Q( oALUChannelY1 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource1[31:0] ),
        .Q( oALUChannelZ1 )
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[95:64] ),
        .Q(oALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[63:32] ),
        .Q(oALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource1[31:0] ),
        .Q(oALUChannelZ1)
);
*/
/*
FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[95:64] ),
        .Q( oALUChannelX2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[63:32] ),
        .Q( oALUChannelY2 )
);
 
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iSource0[31:0] ),
        .Q( oALUChannelZ2 )
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[95:64] ),
        .Q(oALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[63:32] ),
        .Q(oALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iSource0[31:0] ),
        .Q(oALUChannelZ2)
);
*/
//Finally one more latch to store 
//the iOperation and the destination
 
 
assign oALUOperation = iOperation;
//assign oRAMWriteAddress = iDestination;
/*
FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
(
        .Clock( wLatchNow ),
        .Clear( Reset ),
        .D( iOperation  ),
        .Q( oALUOperation )
 
);
 
 
FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
(
        .Clock( wLatchNow  ),
        .Clear( Reset ),
        .D( iDestination  ),
        .Q( oRAMWriteAddress )
 
);
*/
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iOperation ),
        .Q(oALUOperation)
);
*/
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
(
        .Clock( Clock ),//wLatchNow ),
        .Reset( Reset),
        .Enable( wLatchNow ),//1'b1 ),
        .D( iDestination ),
        .Q(oRAMWriteAddress)
);
 
//Data forwarding
assign oLastDestination = oRAMWriteAddress;
 
reg [7:0] CurrentState;
reg [7:0] NextState;
 
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
 
 
    if (Reset)
                CurrentState <= `EXEU_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
//------------------------------------------------
 
 
always @( * )
   begin
        case (CurrentState)
                  //------------------------------------------
                  `EXEU_AFTER_RESET:
                  begin
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /**
                        At the same time iDecodeDone goes to 1, our Flops
                        will store the value, so next clock cycle we can
                        tell IDU to go ahead and decode the next instruction
                        in the pipeline.
                  */
                  `EXEU_WAIT_FOR_DECODE:
                  begin
 
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
 
                        if ( iDecodeDone )      //This same thing triggers the ALU
                                NextState       <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
                  end
                  //------------------------------------------
                  /*
                  If the instruction is aritmetic then pass the parameters
                  the ALU, else if it store iOperation then...
                  */
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         //*
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      0;               //NO INTERRUPTIONS WHILE WE WAIT!!
 
 
 
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
                                        NextState <= `EXEU_WAIT_FOR_DECODE;
                                else
                                        NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                  end
                  //------------------------------------------
                  `EXEU_WRITE_BACK_TO_RAM:
                  begin
 
                                //ReadyForNextInstruction <= 0;                                         
                                oBusy                                                   <= 1;
                                rInputLatchesEnabled            <=      1;
 
                        if ( iDecodeDone )
                                NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
                        else
                                NextState <= `EXEU_WAIT_FOR_DECODE;
 
                  end
 
                  //------------------------------------------
                  default:
                  begin
 
                                //ReadyForNextInstruction <= 1;
                                oBusy                                                   <= 0;
                                rInputLatchesEnabled            <=      1;
 
                                NextState <= `EXEU_AFTER_RESET;
                  end
                  //------------------------------------------
        endcase
end
 
//-----------------------------------------------------------------------
`ifdef DUMP_CODE
integer ucode_file;
integer reg_log;
initial
begin
 
        $display("Opening ucode dump file....\n");
        ucode_file = $fopen("Code.log","w");
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
        $display("Opening Register lof file...\n");
        reg_log = $fopen("Registers.log","w");
 
end
 
`endif //Ucode dump
 
//-----------------------------------------------------------------------
`ifdef DEBUG
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[95:64] ),
        .Q(wALUChannelX1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[63:32] ),
        .Q(wALUChannelY1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource1[31:0] ),
        .Q(wALUChannelZ1)
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[95:64] ),
        .Q(wALUChannelX2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[63:32] ),
        .Q(wALUChannelY2)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
(
        .Clock( Clock ),
        .Reset( Reset),
        .Enable( wLatchNow ),
        .D( iSource0[31:0] ),
        .Q(wALUChannelZ2)
);
 
 
        always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
        begin
                `LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
        end
 
        always @ (negedge  Clock && iDebug_CoreID == `DEBUG_CORE)
        begin
        if ( iALUOutputReady )
        begin
 
 
                if (iBranchTaken)
                        `LOGME"<BT>");
 
                if (iBranchNotTaken     )
                        `LOGME"<BNT>");
 
                if (oRAMWriteEnable)
                        `LOGME"<WE>");
 
                `LOGME "(%dns ",$time);
                                        case ( oALUOperation )
                                        `RETURN: `LOGME"RETURN");
                                        `ADD:   `LOGME"ADD");
                                        `SUB:           `LOGME"SUB");
                                        `DIV:           `LOGME"DIV");
                                        `MUL:   `LOGME"MUL");
                                        `MAG:           `LOGME"MAG");
                                        `JGX:           `LOGME"JGX");
                                        `JLX:           `LOGME"JLX");
                                        `JGEX:  `LOGME"JGEX");
                                        `JGEY:  `LOGME"JGEY");
                                        `JGEZ:  `LOGME"JGEZ");
                                        `JLEX:  `LOGME"JLEX");
                                        `JLEY:  `LOGME"JLEY");
                                        `JLEZ:  `LOGME"JLEZ");
                                        `JMP:           `LOGME"JMP");
                                        `ZERO:  `LOGME"ZERO");
                                        `JNEX:  `LOGME"JNEX");
                                        `JNEY:  `LOGME"JNEY");
                                        `JNEZ:  `LOGME"JNEZ");
                                        `JEQX:  `LOGME"JEQX");
                                        `JEQY:  `LOGME"JEQY");
                                        `JEQZ:  `LOGME"JEQZ");
                                        `CROSS: `LOGME"CROSS");
                                        `DOT:           `LOGME"DOT");
                                        `SETX:  `LOGME"SETX");
                                        `SETY:  `LOGME"SETY");
                                        `SETZ:  `LOGME"SETZ");
                                        `NOP:   `LOGME"NOP");
                                        `COPY:  `LOGME"COPY");
                                        `INC:           `LOGME"INC");
                                        `DEC:           `LOGME"DEC");
                                        `MOD:           `LOGME"MOD");
                                        `FRAC:  `LOGME"FRAC");
                                        `NEG:    `LOGME"NEG");
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
                                        `MULP:          `LOGME"MULP");
                                        `XCHANGEX:      `LOGME"XCHANGEX");
                                        `IMUL:      `LOGME"IMUL");
                                        `UNSCALE:      `LOGME"UNSCALE");
                                        `INCX: `LOGME"INCX");
                                        `INCY: `LOGME"INCY");
                                        `INCZ: `LOGME"INCZ");
                                        `OMWRITE: `LOGME"OMWRITE");
                                        `TMREAD: `LOGME"TMREAD");
                                        `LEA:     `LOGME"LEA");
                                        `CALL:    `LOGME"CALL");
                                        `RET:     `LOGME"RET");
                                        `DEBUG_PRINT:
                                        begin
                                                `LOGME"DEBUG_PRINT");
 
                                        end
                                        default:
                                        begin
                                                `LOGME"**********ERROR UNKNOWN OP*********");
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
                                        //      $stop();
                                        end
                                        endcase
 
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
                                        oRAMWriteAddress,
                                        wALUChannelX1,wALUChannelY1,wALUChannelZ1,
                                        wALUChannelX2,wALUChannelY2,wALUChannelZ2
 
                                        );
 
                                        if (oALUOperation == `RETURN)
                                                `LOGME"\n\n\n");
 
                end
        end //always
 
        always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
        begin
        if ( iALUOutputReady )
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
        end //always
`endif
 
endmodule

Browse

Tools

Subversion Repositories theia_gpu

[/] [theia_gpu/] [trunk/] [rtl/] [Module_ExecutionFSM.v] - Blame information for rev 210

Line No.	Rev	Author	Line
1	152	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define EXEU_AFTER_RESET 0
23			`define EXEU_INITIAL_STATE 1
24			`define EXEU_WAIT_FOR_DECODE 2
25			`define EXEU_FETCH_DECODED_INST 3
26			`define EXEU_WAIT_FOR_ALU_EXECUTION 4
27			`define EXEU_WRITE_BACK_TO_RAM 5
28			`define EXEU_HANDLE_JUMP 7
29
30
31
32			`module ExecutionFSM`
33			`(`
34			`input wire Clock,`
35			`input wire Reset,`
36
37			`input wire iDecodeDone,`
38			input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
39			input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
40			input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
41			inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
42			`//output reg ReadyForNextInstruction,`
43			`output wire oJumpFlag ,`
44			output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
45			`output wire oRAMWriteEnable ,`
46			output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
47			`output wire oExeLatchedValues,`
48			`output reg oBusy ,`
49
50			`//ALU ports and control signals`
51			output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
52			output wire [`WIDTH-1:0] oALUChannelX1,
53			output wire [`WIDTH-1:0] oALUChannelY1,
54			output wire [`WIDTH-1:0] oALUChannelZ1,
55			output wire [`WIDTH-1:0] oALUChannelX2,
56			output wire [`WIDTH-1:0] oALUChannelY2,
57			output wire [`WIDTH-1:0] oALUChannelZ2,
58			`output wire oTriggerALU,`
59
60			input wire [`WIDTH-1:0] iALUResultX,
61			input wire [`WIDTH-1:0] iALUResultY,
62			input wire [`WIDTH-1:0] iALUResultZ,
63			`input wire iALUOutputReady,`
64			`input wire iBranchTaken,`
65			`input wire iBranchNotTaken,`
66
67
68			`ifdef DEBUG
69			input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
70			input wire [`MAX_CORES-1:0] iDebug_CoreID,
71			`endif
72			`//Data forward Signals`
73			output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
74
75
76			`);`
77
78			`wire wLatchNow;`
79			`reg rInputLatchesEnabled;`
80
81			`//If ALU says jump, just pass along`
82			`assign oJumpFlag = iBranchTaken;`
83			`//JumpIP is the instruction destination (= oRAMWriteAddress)`
84			`assign oJumpIp = oRAMWriteAddress;`
85
86			`assign wLatchNow = iDecodeDone & rInputLatchesEnabled;`
87			`assign oExeLatchedValues = wLatchNow;`
88			`assign oTriggerALU = wLatchNow;`
89
90			`wire wOperationIsJump;`
91			`assign wOperationIsJump = iBranchTaken \|\| iBranchNotTaken;`
92
93			`//Don't allow me to write back back if the operation is a NOP`
94			`ifdef DEBUG
95			`assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&`
96			(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
97			`else
98			assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
99			`endif
100
101
102			assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
103
104			`assign oALUChannelX1 = iSource1[95:64];`
105			`assign oALUChannelY1 = iSource1[63:32];`
106			`assign oALUChannelZ1 = iSource1[31:0];`
107
108			`assign oALUChannelX2 = iSource0[95:64];`
109			`assign oALUChannelY2 = iSource0[63:32];`
110			`assign oALUChannelZ2 = iSource0[31:0];`
111
112			`/*`
113			`FF32_POSEDGE_SYNCRONOUS_RESET SourceX1`
114			`(`
115			`.Clock( wLatchNow ),`
116			`.Clear( Reset ),`
117			`.D( iSource1[95:64] ),`
118			`.Q( oALUChannelX1 )`
119			`);`
120
121			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY1`
122			`(`
123			`.Clock( wLatchNow ),`
124			`.Clear( Reset ),`
125			`.D( iSource1[63:32] ),`
126			`.Q( oALUChannelY1 )`
127			`);`
128
129			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1`
130			`(`
131			`.Clock( wLatchNow ),`
132			`.Clear( Reset ),`
133			`.D( iSource1[31:0] ),`
134			`.Q( oALUChannelZ1 )`
135			`);`
136			`*/`
137			`/*`
138			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
139			`(`
140			`.Clock( Clock ),//wLatchNow ),`
141			`.Reset( Reset),`
142			`.Enable( wLatchNow ),//1'b1 ),`
143			`.D( iSource1[95:64] ),`
144			`.Q(oALUChannelX1)`
145			`);`
146			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
147			`(`
148			`.Clock( Clock ),//wLatchNow ),`
149			`.Reset( Reset),`
150			`.Enable( wLatchNow ),//1'b1 ),`
151			`.D( iSource1[63:32] ),`
152			`.Q(oALUChannelY1)`
153			`);`
154			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
155			`(`
156			`.Clock( Clock ),//wLatchNow ),`
157			`.Reset( Reset),`
158			`.Enable( wLatchNow ),//1'b1 ),`
159			`.D( iSource1[31:0] ),`
160			`.Q(oALUChannelZ1)`
161			`);`
162			`*/`
163			`/*`
164			`FF32_POSEDGE_SYNCRONOUS_RESET SourceX2`
165			`(`
166			`.Clock( wLatchNow ),`
167			`.Clear( Reset ),`
168			`.D( iSource0[95:64] ),`
169			`.Q( oALUChannelX2 )`
170			`);`
171
172			`FF32_POSEDGE_SYNCRONOUS_RESET SourceY2`
173			`(`
174			`.Clock( wLatchNow ),`
175			`.Clear( Reset ),`
176			`.D( iSource0[63:32] ),`
177			`.Q( oALUChannelY2 )`
178			`);`
179
180			`FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2`
181			`(`
182			`.Clock( wLatchNow ),`
183			`.Clear( Reset ),`
184			`.D( iSource0[31:0] ),`
185			`.Q( oALUChannelZ2 )`
186			`);`
187			`*/`
188			`/*`
189			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
190			`(`
191			`.Clock( Clock ),//wLatchNow ),`
192			`.Reset( Reset),`
193			`.Enable( wLatchNow ),//1'b1 ),`
194			`.D( iSource0[95:64] ),`
195			`.Q(oALUChannelX2)`
196			`);`
197			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
198			`(`
199			`.Clock( Clock ),//wLatchNow ),`
200			`.Reset( Reset),`
201			`.Enable( wLatchNow ),//1'b1 ),`
202			`.D( iSource0[63:32] ),`
203			`.Q(oALUChannelY2)`
204			`);`
205			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
206			`(`
207			`.Clock( Clock ),//wLatchNow ),`
208			`.Reset( Reset),`
209			`.Enable( wLatchNow ),//1'b1 ),`
210			`.D( iSource0[31:0] ),`
211			`.Q(oALUChannelZ2)`
212			`);`
213			`*/`
214			`//Finally one more latch to store`
215			`//the iOperation and the destination`
216
217
218			`assign oALUOperation = iOperation;`
219			`//assign oRAMWriteAddress = iDestination;`
220			`/*`
221			`FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation`
222			`(`
223			`.Clock( wLatchNow ),`
224			`.Clear( Reset ),`
225			`.D( iOperation ),`
226			`.Q( oALUOperation )`
227
228			`);`
229
230
231			`FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination`
232			`(`
233			`.Clock( wLatchNow ),`
234			`.Clear( Reset ),`
235			`.D( iDestination ),`
236			`.Q( oRAMWriteAddress )`
237
238			`);`
239			`*/`
240			`/*`
241			FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
242			`(`
243			`.Clock( Clock ),//wLatchNow ),`
244			`.Reset( Reset),`
245			`.Enable( wLatchNow ),//1'b1 ),`
246			`.D( iOperation ),`
247			`.Q(oALUOperation)`
248			`);`
249			`*/`
250			FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
251			`(`
252			`.Clock( Clock ),//wLatchNow ),`
253			`.Reset( Reset),`
254			`.Enable( wLatchNow ),//1'b1 ),`
255			`.D( iDestination ),`
256			`.Q(oRAMWriteAddress)`
257			`);`
258
259			`//Data forwarding`
260			`assign oLastDestination = oRAMWriteAddress;`
261
262			`reg [7:0] CurrentState;`
263			`reg [7:0] NextState;`
264
265
266			`//------------------------------------------------`
267			`always @(posedge Clock or posedge Reset)`
268			`begin`
269
270
271
272			`if (Reset)`
273			CurrentState <= `EXEU_AFTER_RESET;
274			`else`
275			`CurrentState <= NextState;`
276
277			`end`
278			`//------------------------------------------------`
279
280
281			`always @( * )`
282			`begin`
283			`case (CurrentState)`
284			`//------------------------------------------`
285			`EXEU_AFTER_RESET:
286			`begin`
287			`//ReadyForNextInstruction <= 1;`
288			`oBusy <= 0;`
289			`rInputLatchesEnabled <= 1;`
290
291
292			NextState <= `EXEU_WAIT_FOR_DECODE;
293			`end`
294			`//------------------------------------------`
295			`/**`
296			`At the same time iDecodeDone goes to 1, our Flops`
297			`will store the value, so next clock cycle we can`
298			`tell IDU to go ahead and decode the next instruction`
299			`in the pipeline.`
300			`*/`
301			`EXEU_WAIT_FOR_DECODE:
302			`begin`
303
304
305			`//ReadyForNextInstruction <= 1;`
306			`oBusy <= 0;`
307			`rInputLatchesEnabled <= 1;`
308
309
310			`if ( iDecodeDone ) //This same thing triggers the ALU`
311			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
312			`else`
313			NextState <= `EXEU_WAIT_FOR_DECODE;
314			`end`
315			`//------------------------------------------`
316			`/*`
317			`If the instruction is aritmetic then pass the parameters`
318			`the ALU, else if it store iOperation then...`
319			`*/`
320			`EXEU_WAIT_FOR_ALU_EXECUTION:
321			`begin`
322
323			`//ReadyForNextInstruction <= 0; //*`
324			`oBusy <= 1;`
325			`rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!`
326
327
328
329			`if ( iALUOutputReady ) /////This same thing enables writing th results to RAM`
330			NextState <= `EXEU_WAIT_FOR_DECODE;
331			`else`
332			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
333			`end`
334			`//------------------------------------------`
335			`EXEU_WRITE_BACK_TO_RAM:
336			`begin`
337
338			`//ReadyForNextInstruction <= 0;`
339			`oBusy <= 1;`
340			`rInputLatchesEnabled <= 1;`
341
342			`if ( iDecodeDone )`
343			NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
344			`else`
345			NextState <= `EXEU_WAIT_FOR_DECODE;
346
347			`end`
348
349			`//------------------------------------------`
350			`default:`
351			`begin`
352
353			`//ReadyForNextInstruction <= 1;`
354			`oBusy <= 0;`
355			`rInputLatchesEnabled <= 1;`
356
357			NextState <= `EXEU_AFTER_RESET;
358			`end`
359			`//------------------------------------------`
360			`endcase`
361			`end`
362
363			`//-----------------------------------------------------------------------`
364			`ifdef DUMP_CODE
365			`integer ucode_file;`
366			`integer reg_log;`
367			`initial`
368			`begin`
369
370			`$display("Opening ucode dump file....\n");`
371			`ucode_file = $fopen("Code.log","w");`
372			`$fwrite(ucode_file,"\n\n********** Theia UCODE DUMP *****\n\n\n\n");`
373			`$display("Opening Register lof file...\n");`
374			`reg_log = $fopen("Registers.log","w");`
375
376			`end`
377
378			`endif //Ucode dump
379
380			`//-----------------------------------------------------------------------`
381			`ifdef DEBUG
382			wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
383			wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
384
385			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
386			`(`
387			`.Clock( Clock ),`
388			`.Reset( Reset),`
389			`.Enable( wLatchNow ),`
390			`.D( iSource1[95:64] ),`
391			`.Q(wALUChannelX1)`
392			`);`
393			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
394			`(`
395			`.Clock( Clock ),`
396			`.Reset( Reset),`
397			`.Enable( wLatchNow ),`
398			`.D( iSource1[63:32] ),`
399			`.Q(wALUChannelY1)`
400			`);`
401			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
402			`(`
403			`.Clock( Clock ),`
404			`.Reset( Reset),`
405			`.Enable( wLatchNow ),`
406			`.D( iSource1[31:0] ),`
407			`.Q(wALUChannelZ1)`
408			`);`
409
410
411			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
412			`(`
413			`.Clock( Clock ),`
414			`.Reset( Reset),`
415			`.Enable( wLatchNow ),`
416			`.D( iSource0[95:64] ),`
417			`.Q(wALUChannelX2)`
418			`);`
419			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
420			`(`
421			`.Clock( Clock ),`
422			`.Reset( Reset),`
423			`.Enable( wLatchNow ),`
424			`.D( iSource0[63:32] ),`
425			`.Q(wALUChannelY2)`
426			`);`
427			FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
428			`(`
429			`.Clock( Clock ),`
430			`.Reset( Reset),`
431			`.Enable( wLatchNow ),`
432			`.D( iSource0[31:0] ),`
433			`.Q(wALUChannelZ2)`
434			`);`
435
436
437			always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
438			`begin`
439			`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
440			`end`
441
442			always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
443			`begin`
444			`if ( iALUOutputReady )`
445			`begin`
446
447
448			`if (iBranchTaken)`
449			`LOGME"<BT>");
450
451			`if (iBranchNotTaken )`
452			`LOGME"<BNT>");
453
454			`if (oRAMWriteEnable)`
455			`LOGME"<WE>");
456
457			`LOGME "(%dns ",$time);
458			`case ( oALUOperation )`
459			`RETURN: `LOGME"RETURN");
460			`ADD: `LOGME"ADD");
461			`SUB: `LOGME"SUB");
462			`DIV: `LOGME"DIV");
463			`MUL: `LOGME"MUL");
464			`MAG: `LOGME"MAG");
465			`JGX: `LOGME"JGX");
466			`JLX: `LOGME"JLX");
467			`JGEX: `LOGME"JGEX");
468			`JGEY: `LOGME"JGEY");
469			`JGEZ: `LOGME"JGEZ");
470			`JLEX: `LOGME"JLEX");
471			`JLEY: `LOGME"JLEY");
472			`JLEZ: `LOGME"JLEZ");
473			`JMP: `LOGME"JMP");
474			`ZERO: `LOGME"ZERO");
475			`JNEX: `LOGME"JNEX");
476			`JNEY: `LOGME"JNEY");
477			`JNEZ: `LOGME"JNEZ");
478			`JEQX: `LOGME"JEQX");
479			`JEQY: `LOGME"JEQY");
480			`JEQZ: `LOGME"JEQZ");
481			`CROSS: `LOGME"CROSS");
482			`DOT: `LOGME"DOT");
483			`SETX: `LOGME"SETX");
484			`SETY: `LOGME"SETY");
485			`SETZ: `LOGME"SETZ");
486			`NOP: `LOGME"NOP");
487			`COPY: `LOGME"COPY");
488			`INC: `LOGME"INC");
489			`DEC: `LOGME"DEC");
490			`MOD: `LOGME"MOD");
491			`FRAC: `LOGME"FRAC");
492			`NEG: `LOGME"NEG");
493			`SWIZZLE3D: `LOGME"SWIZZLE3D");
494			`MULP: `LOGME"MULP");
495			`XCHANGEX: `LOGME"XCHANGEX");
496			`IMUL: `LOGME"IMUL");
497			`UNSCALE: `LOGME"UNSCALE");
498			`INCX: `LOGME"INCX");
499			`INCY: `LOGME"INCY");
500			`INCZ: `LOGME"INCZ");
501			`OMWRITE: `LOGME"OMWRITE");
502			`TMREAD: `LOGME"TMREAD");
503			`LEA: `LOGME"LEA");
504			`CALL: `LOGME"CALL");
505			`RET: `LOGME"RET");
506			`DEBUG_PRINT:
507			`begin`
508			`LOGME"DEBUG_PRINT");
509
510			`end`
511			`default:`
512			`begin`
513			`LOGME"********ERROR UNKNOWN OP*******");
514			`$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);`
515			`// $stop();`
516			`end`
517			`endcase`
518
519			`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
520			`oRAMWriteAddress,`
521			`wALUChannelX1,wALUChannelY1,wALUChannelZ1,`
522			`wALUChannelX2,wALUChannelY2,wALUChannelZ2`
523
524			`);`
525
526			if (oALUOperation == `RETURN)
527			`LOGME"\n\n\n");
528
529			`end`
530			`end //always`
531
532			always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
533			`begin`
534			`if ( iALUOutputReady )`
535			`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
536			`end //always`
537			`endif
538
539			`endmodule`