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[/] [theia_gpu/] [trunk/] [rtl/] [Module_Host.v] - Blame information for rev 211

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Line No. Rev Author Line
1 152 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
3
 
4
 
5
 
6
/**********************************************************************************
7
Theia, Ray Cast Programable graphic Processing Unit.
8
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
9
 
10
This program is free software; you can redistribute it and/or
11
modify it under the terms of the GNU General Public License
12
as published by the Free Software Foundation; either version 2
13
of the License, or (at your option) any later version.
14
 
15
This program is distributed in the hope that it will be useful,
16
but WITHOUT ANY WARRANTY; without even the implied warranty of
17
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
GNU General Public License for more details.
19
 
20
You should have received a copy of the GNU General Public License
21
along with this program; if not, write to the Free Software
22
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
23
 
24
***********************************************************************************/
25
 
26
 
27
/*******************************************************************************
28
Module Description:
29
 
30
WIP
31
 
32
*******************************************************************************/
33
 
34
 
35
 
36
`define MAX_VERTEX_IN_FRAME      `WIDTH'd7 // WAS 8'd6
37
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
38
`define TAG_DATA_ADDRESS_TYPE        2'b10
39
`define SELECT_INST_MEM              3'b00
40
`define SELECT_SCENE_MEM             3'b01
41
`define SELECT_GEO_MEM               3'b10
42
 
43
 
44
`define HOST_IDLE                       0
45
`define HOST_WRITE_INSTRUCTION          1
46
`define HOST_WAIT_INSTRUCTION           2
47
`define HOST_WRITE_SCENE_PARAMS         3
48
`define HOST_WAIT_SCENE_PARAMS          4
49
`define HOST_PREPARE_CORE_CONFIG        5
50
`define HOST_UNICAST_CORE_CONFIG        6
51
`define HOST_WAIT_CORE_CONFIG           7
52
`define HOST_PREPARE_NEXT_CORE_CONFIG   8
53
`define HOST_WAIT_DATA_READ_CONFIRMATION       10
54
`define HOST_BROADCAST_NEXT_VERTEX   11
55
`define HOST_WAIT_FOR_VERTEX    12
56
`define HOST_INITIAL_SCENE_PARAMS_STAGE 13
57
`define HOST_PREPARE_FOR_GEO_REQUESTS   14
58
`define HOST_ACK_GEO_REQUEST            15
59
`define HOST_GET_PRIMITIVE_COUNT    16
60
`define HOST_LAST_PRIMITIVE_REACHED 17
61
`define HOST_GPU_EXECUTION_DONE 18
62
 
63
//---------------------------------------------------------------
64
module Module_Host
65
(
66
        input wire Clock,
67
        input wire Reset,
68
        input wire iEnable,
69
        input wire iHostDataReadConfirmed,
70
        input wire [`WB_WIDTH-1:0] iMemorySize,
71
        input wire [`WB_WIDTH-1:0] iPrimitiveCount,
72
 
73
        //To Memory
74
        output wire [`WB_WIDTH-1:0] oReadAddress,
75
        input wire [`WB_WIDTH-1:0]  iReadData,
76
        input wire iGPUCommitedResults,
77
 
78
        //To Hub/Switch
79
        output wire [`MAX_CORES-1:0]     oCoreSelectMask,
80
        output reg [2:0]                 oMemSelect,
81
        output wire [`WB_WIDTH-1:0]      DAT_O,
82
        output wire [`WB_WIDTH-1:0]      ADR_O,
83
        output reg[1:0]                  TGA_O,
84
        output reg[`MAX_CORES-1:0]       RENDREN_O,
85
        output wire                      CYC_O,
86
        output wire                      STB_O,
87
        output reg                       MST_O,
88
        output wire                      WE_O,
89
        input  wire                                                     GRDY_I, //This means all the cores are done rading the primitive we send
90
   output reg                       GACK_O,     //We set this to ACK that the cored read the primitive
91
        output wire                       STDONE_O,
92
        output reg                       oHostDataAvailable,
93
        input wire                       iGPUDone,
94
        `ifndef NO_DISPLAY_STATS
95
        input wire [`WIDTH-1:0] iDebugWidth,
96
        `endif
97
        input wire                       ACK_I
98
);
99
//---------------------------------------------------------------
100
wire wLastPrimitive;
101
assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
102
assign STDONE_O = wLastPrimitive;
103
 
104
wire  wWBMDone;
105
reg rWBMEnable,rWBMReset,rCoreBroadCast;
106
reg [`WB_WIDTH-1:0] rInitiaReadAddr;
107
wire [`MAX_CORES-1:0] wCoreSelect;
108
wire wLastValidReadAddress;
109
wire [`WB_WIDTH-1:0] wWriteAddress;
110
wire [`WIDTH-1:0] wVertexCount;
111
reg [`WB_WIDTH-1:0] rInitialWriteAddress;
112
reg rSetWriteAddr;
113
reg rIncCoreSelect,rResetVertexCount;
114
//--------------------------------------------------------
115
 
116
assign WE_O = MST_O;
117
 
118
assign oCoreSelectMask =
119
        (rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
120
 
121
assign wLastValidReadAddress =
122
        (oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
123
 
124
wire wLastParameter;
125
assign wLastParameter = (oReadAddress >= 32'h12) ? 1'b1 : 1'b0;
126
//--------------------------------------------------------
127
UPCOUNTER_POSEDGE # (`WB_WIDTH ) UPWADDR
128
        (
129
        .Clock(  Clock                   ),
130
        .Reset(   Reset | rSetWriteAddr  ),
131
        .Enable(  iEnable & wWBMDone     ),
132
        .Initial( rInitialWriteAddress   ),
133
        .Q(       wWriteAddress          )
134
        );
135
 
136
 
137
UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
138
        (
139
        .Clock(  Clock                   ),
140
        .Reset(   Reset | rResetVertexCount  ),
141
        .Enable(  iEnable & wWBMDone     ),
142
        .Initial( `WIDTH'b1   ),
143
        .Q(       wVertexCount          )
144
        );
145
//--------------------------------------------------------
146
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
147
(
148
        .Clock(    Clock             ),
149
        .Reset(    Reset             ),
150
        .Initial( `MAX_CORES'b1      ),
151
        .Enable(   rIncCoreSelect    ),
152
        .O(        wCoreSelect       )
153
);
154
//--------------------------------------------------------
155
wire wShortCycle;
156
//For instruction we send 2 packets per cycle
157
//for the other we send 3 packets per cycle
158
assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
159
 
160
WBMaster WBM
161
(
162
.Clock(            Clock             ),
163
.Reset(            Reset | rWBMReset ),
164
.iEnable(          rWBMEnable        ),
165
.iInitialReadAddr( rInitiaReadAddr   ),
166
.iWriteAddr(       wWriteAddress     ),
167
.oReadAddress(     oReadAddress      ),
168
.iReadData(        iReadData         ),
169
.iShortFlow(        wShortCycle     ),
170
 
171
 
172
.STB_O( STB_O ),
173
.ACK_I( ACK_I ),
174
.CYC_O( CYC_O ),
175
.DAT_O( DAT_O ),
176
.ADR_O( ADR_O ),
177
.oDone( wWBMDone )
178
);
179
 
180
//--------------------------------------------------------
181
// Current State Logic //
182
reg [7:0]                        rHostCurrentState,rHostNextState;
183
always @(posedge Clock or posedge Reset)
184
begin
185
     if( Reset!=1 )
186
        rHostCurrentState <= rHostNextState;
187
          else
188
                  rHostCurrentState <= `HOST_IDLE;
189
end
190
//--------------------------------------------------------
191
 
192
reg [63:0] i;
193
reg [63:0] RenderedPixels;
194
wire wLastVertexInFrame;
195
assign wLastVertexInFrame =
196
(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
197
 
198
// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
199
 
200
reg [31:0] StartTime;
201
 
202
// Host Finite State Machine //
203
always @( * )
204
        begin
205
 
206
                case (rHostCurrentState)
207
                //----------------------------------------
208
                //Wait for reset sequence to complete,
209
                //Or until we are enabled
210
                `HOST_IDLE:
211
                begin
212
                RenderedPixels = 0;
213
 
214
                        rWBMEnable            = 0;
215
                   rInitiaReadAddr       = 1;   //Start reading from 1, because 0 is the size
216
                        rWBMReset             = 0;
217
                        oMemSelect            = 0;
218
                        TGA_O                 = 0;
219
                        MST_O                   = 0;
220
                        rInitialWriteAddress  = 0;
221
         rSetWriteAddr         = 0;
222
                        rCoreBroadCast        = 0;
223
                        rIncCoreSelect        = 0;
224
                        RENDREN_O                                = 0;
225
                        rResetVertexCount  = 0;
226
                        GACK_O                                   = 0;
227
                        //STDONE_O                                       = 0;
228
                        oHostDataAvailable    = 0;
229
 
230
                        if ( ~Reset & iEnable )
231
                        begin
232
                                $display("-I- HOST: Broadcasting User code to all Cores\n"); $fflush;
233
                                rHostNextState = `HOST_WRITE_INSTRUCTION;
234
                        end
235
                        else
236
                                rHostNextState = `HOST_IDLE;
237
                end
238
                //----------------------------------------
239
                //Broadcast the instructions to all the cores
240
                `HOST_WRITE_INSTRUCTION:
241
                begin
242
 
243
                        StartTime = $time;
244
 
245
                        rWBMEnable            = 1;                                                                              //Enable Wish bone master
246
                   rInitiaReadAddr       = 1;                                                                           //Start reading from 1, because 0 is the size
247
                        rWBMReset             = 0;                                                                               //No need to reset since we just came from reset
248
                        oMemSelect            = `SELECT_INST_MEM;                                       //Start by sending the instructions
249
                        TGA_O                 = `TAG_INSTRUCTION_ADDRESS_TYPE;
250
                        MST_O                   = 1;
251
                        rInitialWriteAddress  = 0;
252
         rSetWriteAddr         = 0;
253
                        rCoreBroadCast        = 1;
254
                        rIncCoreSelect        = 0;
255
                        RENDREN_O                                = 0;
256
                        rResetVertexCount  = 0;
257
                        GACK_O                                   = 0;
258
                        //STDONE_O                                       = 0;
259
                        oHostDataAvailable    = 0;
260
 
261
                        rHostNextState = `HOST_WAIT_INSTRUCTION;
262
                end
263
                //----------------------------------------
264
                `HOST_WAIT_INSTRUCTION:
265
                begin
266
                        rWBMEnable            = ~wWBMDone;
267
                   rInitiaReadAddr       = 0;
268
                        rWBMReset             = 0;
269
                        oMemSelect            = `SELECT_INST_MEM;
270
                        TGA_O                 = `TAG_INSTRUCTION_ADDRESS_TYPE;
271
                        MST_O                   = 1;
272
                        rInitialWriteAddress  = 0;
273
         rSetWriteAddr         = 0;
274
                        rCoreBroadCast        = 1;
275
                        rIncCoreSelect        = 0;
276
                        RENDREN_O                                = 0;
277
                        rResetVertexCount  = 0;
278
                        GACK_O                                   = 0;
279
                        //STDONE_O                                       = 0;
280
                        oHostDataAvailable    = 0;
281
 
282
                        if ( wWBMDone && ~wLastValidReadAddress )
283
                                rHostNextState = `HOST_WRITE_INSTRUCTION;
284
                        else if (wWBMDone && wLastValidReadAddress )
285
                                rHostNextState = `HOST_INITIAL_SCENE_PARAMS_STAGE;
286
                        else
287
                                rHostNextState = `HOST_WAIT_INSTRUCTION;
288
                end
289
                //----------------------------------------
290
                /*
291
                        Make sure to read-pointer points to the
292
                        first memory address at te params memory
293
                */
294
                `HOST_INITIAL_SCENE_PARAMS_STAGE:
295
                begin
296
                        rWBMEnable            = 0;
297
                   rInitiaReadAddr       = 1;                                                                                   //Start reading from 1, because 0 is the size
298
                        rWBMReset             = 1;
299
                        oMemSelect            = `SELECT_SCENE_MEM;                                              //We are reading from the scene memory
300
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;                         //We will write to the DATA section of the core MEM
301
                        MST_O                   = 1;                                                                                    //Keep master signal in 1 for now
302
                        rInitialWriteAddress  = 0;                                                                                       //We start writing from address zero now
303
         rSetWriteAddr         = 1;
304
                        rCoreBroadCast        = 1;                                                                                      //Set to zero to unicast, starting from core 0
305
                        rIncCoreSelect        = 0;                                                                                       //Set to unicast to the next core
306
                        RENDREN_O                                = 0;
307
                        rResetVertexCount  = 0;
308
                        GACK_O                                   = 0;
309
                        //STDONE_O                                       = 0;
310
                        oHostDataAvailable    = 0;
311
 
312
                        $display("-I- HOST: Configuring Core Mask %b\n",oCoreSelectMask); $fflush;
313
 
314
                        rHostNextState = `HOST_WRITE_SCENE_PARAMS;
315
                end
316
 
317
                //----------------------------------------
318
                //Broadcast the instructions to all the cores
319
                `HOST_WRITE_SCENE_PARAMS:
320
                begin
321
                        rWBMEnable            = 1;
322
                   rInitiaReadAddr       = 0;
323
                        rWBMReset             = 0;
324
                        oMemSelect            = `SELECT_SCENE_MEM;
325
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
326
                        MST_O                   = 1;
327
                        rInitialWriteAddress  = 0;
328
         rSetWriteAddr         = 0;
329
                        rCoreBroadCast        = 1;
330
                        rIncCoreSelect        = 0;
331
                        RENDREN_O                                = 0;
332
                        rResetVertexCount  = 0;
333
                        GACK_O                                   = 0;
334
                        //STDONE_O                                       = 0;
335
                        oHostDataAvailable    = 0;
336
 
337
                        rHostNextState = `HOST_WAIT_SCENE_PARAMS;
338
                end
339
                //----------------------------------------
340
                `HOST_WAIT_SCENE_PARAMS:
341
                begin
342
                        rWBMEnable            = ~wWBMDone;
343
                   rInitiaReadAddr       = 0;
344
                        rWBMReset             = 0;
345
                        oMemSelect            = `SELECT_SCENE_MEM;
346
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
347
                        MST_O                   = 1;
348
                        rInitialWriteAddress  = 0;
349
         rSetWriteAddr         = 0;
350
                        rCoreBroadCast        = 1;
351
                        rIncCoreSelect        = 0;
352
                        RENDREN_O                                = 0;
353
                        rResetVertexCount  = 0;
354
                        GACK_O                                   = 0;
355
                        //STDONE_O                                       = 0;
356
                        oHostDataAvailable    = 0;
357
 
358
                        if ( wWBMDone && ~wLastParameter )
359
                                rHostNextState = `HOST_WRITE_SCENE_PARAMS;
360
                        else if (wWBMDone && wLastParameter )
361
                                rHostNextState = `HOST_PREPARE_CORE_CONFIG;
362
                        else
363
                                rHostNextState = `HOST_WAIT_SCENE_PARAMS;
364
                end
365
                //----------------------------------------
366
                /*
367
                        This state set the read Write Address pointer to
368
                        CREG_PIXEL_2D_INITIAL_POSITION memory position,
369
                        also selects the scene MEM from the external MEM
370
                        MUX.
371
                */
372
                `HOST_PREPARE_CORE_CONFIG:
373
                begin
374
                        rWBMEnable            = 0;
375
                   rInitiaReadAddr       = 0;
376
                        rWBMReset             = 0;
377
                        oMemSelect            = `SELECT_SCENE_MEM;                                              //We are reading from the scene memory
378
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;                         //We will write to the DATA section of the core MEM
379
                        MST_O                   = 1;                                                                                    //Keep master signal in 1 for now
380
                        rInitialWriteAddress  = `CREG_PIXEL_2D_INITIAL_POSITION;        //The address from which to start wrting @ the cores
381
         rSetWriteAddr         = 1;                                                                                     //Set to use the initial write address bellow
382
                        rCoreBroadCast        = 0;                                                                                       //Set to zero to unicast, starting from core 0
383
                        rIncCoreSelect        = 0;                                                                                       //Set to unicast to the next core
384
                        RENDREN_O                                = 0;
385
                        rResetVertexCount  = 0;
386
                        GACK_O                                   = 0;
387
                        //STDONE_O                                       = 0;
388
                        oHostDataAvailable    = 0;
389
 
390
 
391
                        rHostNextState = `HOST_UNICAST_CORE_CONFIG;
392
                end
393
 
394
                //----------------------------------------
395
                `HOST_UNICAST_CORE_CONFIG:
396
                begin
397
                        rWBMEnable            = 1;
398
                   rInitiaReadAddr       = 0;
399
                        rWBMReset             = 0;
400
                        oMemSelect            = `SELECT_SCENE_MEM;
401
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
402
                        MST_O                   = 1;
403
                        rInitialWriteAddress  = 0;
404
         rSetWriteAddr         = 0;
405
                        rCoreBroadCast        = 0;
406
                        rIncCoreSelect        = 0;
407
                        RENDREN_O                                = 0;
408
                        rResetVertexCount  = 0;
409
                        GACK_O                                   = 0;
410
                        //STDONE_O                                       = 0;
411
                        oHostDataAvailable    = 0;
412
 
413
                        rHostNextState = `HOST_WAIT_CORE_CONFIG;
414
                end
415
                //----------------------------------------
416
                `HOST_WAIT_CORE_CONFIG:
417
                begin
418
                        rWBMEnable            = ~wWBMDone;
419
                   rInitiaReadAddr       = 0;
420
                        rWBMReset             = 0;
421
                        oMemSelect            = `SELECT_SCENE_MEM;
422
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
423
                        MST_O                   = 1;
424
                        rInitialWriteAddress  = 0;
425
         rSetWriteAddr         = 0;
426
                        rCoreBroadCast        = 0;
427
                        rIncCoreSelect        = 0;
428
                        RENDREN_O                                = 0;
429
                        rResetVertexCount  = 0;
430
                        GACK_O                                   = 0;
431
                        //STDONE_O                                       = 0;
432
                        oHostDataAvailable    = 0;
433 156 diegovalve
 
434 152 diegovalve
                        if (wWBMDone && !(oReadAddress % 2))
435
                                rHostNextState = `HOST_UNICAST_CORE_CONFIG;
436
                        else if (wWBMDone && (oReadAddress % 2) )
437
                                rHostNextState = `HOST_PREPARE_NEXT_CORE_CONFIG;
438
                        else
439
                                rHostNextState = `HOST_WAIT_CORE_CONFIG;
440
 
441
                end
442
                //----------------------------------------
443
                /*
444
                        Reset the WBM to tell it to start reading
445
                        from address 0 at the Geometry memory.
446
                */
447
                `HOST_PREPARE_NEXT_CORE_CONFIG:
448
                begin
449
                        rWBMEnable            = 0;
450
                   rInitiaReadAddr       = 0;
451
                        rWBMReset             = 0;
452
                        oMemSelect            = `SELECT_GEO_MEM;
453
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
454
                        MST_O                   = 0;                                                                                     //The master signal goes to zero until request
455
                        rInitialWriteAddress  = `CREG_PIXEL_2D_INITIAL_POSITION;        //Write starting from this location on the cores
456
         rSetWriteAddr         = 1;                                                                                     //Set to use the initial write address bellow
457
                        rCoreBroadCast        = 0;
458
                        rIncCoreSelect        = 1;                                                                                      //Moving to configure the next core now
459
                        RENDREN_O                                = 0;
460
                        rResetVertexCount  = 0;
461
                        GACK_O                                   = 0;
462
                        //STDONE_O                                       = 0;
463
                        oHostDataAvailable    = 0;
464
 
465
                        if (wCoreSelect[`MAX_CORES-1] == 1)
466
                                rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
467
                        else
468
                                rHostNextState = `HOST_UNICAST_CORE_CONFIG;
469
                end
470
                //----------------------------------------
471
                /*
472
                        Prepare the write address for the next primitive.
473
 
474
                */
475
                `HOST_PREPARE_FOR_GEO_REQUESTS:
476
                begin
477
                        rWBMEnable            = 0;                                                               //Do not enable until we are resquested
478
                   rInitiaReadAddr       = 32'hA;                                                       //Start reading from addr 0 @ GEO MEM
479
                        rWBMReset             = 1;                                                              //Tell WBM to start reading from the addr bellow
480
                        oMemSelect            = `SELECT_GEO_MEM;                        //Use external GEO mem for reading
481
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
482
                        MST_O                   = 0;                                                             //The master signal goes to zero until request
483
                        rInitialWriteAddress  = `CREG_V0;                                               //Write starting from this location on the cores
484
         rSetWriteAddr         = 1;                                                             //Set to use the initial write address bellow
485
                        rCoreBroadCast        = 1;                                                              //From now on we only broadcast                                 
486
                        rIncCoreSelect        = 0;                                                               //Ignored during broadcasts     
487
                        RENDREN_O                                = 0;
488
                        rResetVertexCount  = 1;
489
                        GACK_O                                   = 0;
490
                        //STDONE_O                                       = 0;
491
                        oHostDataAvailable    = 0;
492
 
493
                        if (iGPUDone)
494
                                rHostNextState = `HOST_GPU_EXECUTION_DONE;
495
                        else
496
                                rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
497
 
498
                end
499
                //----------------------------------------
500
                `HOST_ACK_GEO_REQUEST:
501
                begin
502
                        rWBMEnable            = 0;                                                               //Do not enable until we are resquested
503
                   rInitiaReadAddr       = 0;                                                            //Ignored
504
                        rWBMReset             = 0;                                                               //Ignored
505
                        oMemSelect            = `SELECT_GEO_MEM;                        //Use external GEO mem for reading
506
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
507
                        MST_O                   = 0;                                                             //The master signal goes to zero until request
508
                        rInitialWriteAddress  = `CREG_V0;                                               //Write starting from this location on the cores
509
         rSetWriteAddr         = 1;                                                             //Set to use the initial write address bellow
510
                        rCoreBroadCast        = 1;                                                              //From now on we only broadcast                                 
511
                        rIncCoreSelect        = 0;                                                               //Ignored during broadcasts     
512
                        RENDREN_O                                = 0;
513
                        rResetVertexCount       = 0;
514
                        GACK_O                                   = 1;
515
                        //STDONE_O                                       = 0;
516
                        oHostDataAvailable    = 0;
517
 
518
 
519
                        rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
520
 
521
                end
522
                //----------------------------------------
523
                /*
524
                        Send the next primitive to the HUB/SWITCH unit
525
                        so that it gets broadcasted to all the cores
526
                */
527
                `HOST_BROADCAST_NEXT_VERTEX:
528
                begin
529
                        rWBMEnable            = 1;                                                              //Start the Transmition                                         
530
                   rInitiaReadAddr       = 0;
531
                        rWBMReset             = 0;
532
                        oMemSelect            = `SELECT_GEO_MEM;
533
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
534
                        MST_O                   = 1;                                                            //Start the Transmition
535
                        rInitialWriteAddress  = 0;
536
         rSetWriteAddr         = 0;
537
                        rCoreBroadCast        = 1;
538
                        rIncCoreSelect        = 0;
539
                        RENDREN_O                                = `SELECT_ALL_CORES;
540
                        rResetVertexCount  = 0;
541
                        GACK_O                                   = 0;
542
                        //STDONE_O                                       = 0;
543
                        oHostDataAvailable    = 0;
544
 
545
                        rHostNextState = `HOST_WAIT_FOR_VERTEX;
546
 
547
                end
548
                //----------------------------------------
549
                `HOST_WAIT_FOR_VERTEX:
550
                begin
551
                        rWBMEnable            = ~wWBMDone;                                              //Disable WBM when it is donw                                           
552
                   rInitiaReadAddr       = 0;
553
                        rWBMReset             = 0;
554
                        oMemSelect            = `SELECT_GEO_MEM;
555
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
556
                        MST_O                   = 1;                                                            //Start the Transmition
557
                        rInitialWriteAddress  = 0;
558
         rSetWriteAddr         = 0;
559
                        rCoreBroadCast        = 1;
560
                        rIncCoreSelect        = 0;
561
                        RENDREN_O                                = `SELECT_ALL_CORES;
562
                        rResetVertexCount  = 0;
563
                        GACK_O                                   = 0;
564
                        //STDONE_O                                       = 0;
565
                        oHostDataAvailable    = 0;
566
 
567
 
568
                        if (wWBMDone & ~wLastVertexInFrame )
569
                                rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
570
                        else if (wWBMDone & wLastVertexInFrame )
571
                                rHostNextState = `HOST_GET_PRIMITIVE_COUNT;
572
                        else
573
                                rHostNextState = `HOST_WAIT_FOR_VERTEX;
574
 
575
 
576
                        /*
577
                        if (wWBMDone)
578
                                rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
579
                        else
580
                                rHostNextState = `HOST_WAIT_FOR_VERTEX;
581
                                */
582
                end
583
                //----------------------------------------
584
                `HOST_GET_PRIMITIVE_COUNT:
585
                begin
586
                        rWBMEnable            = 0;                                               //Disable WBM when it is donw                                           
587
                   rInitiaReadAddr       = 0;
588
                        rWBMReset             = 0;
589
                        oMemSelect            = `SELECT_GEO_MEM;
590
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
591
                        MST_O                   = 1;                                                            //Start the Transmition
592
                        rInitialWriteAddress  = 0;
593
         rSetWriteAddr         = 0;
594
                        rCoreBroadCast        = 1;
595
                        rIncCoreSelect        = 0;
596
                        RENDREN_O                                = `SELECT_ALL_CORES;
597
                        rResetVertexCount  = 0;
598
                        GACK_O                                   = 0;
599
                        //STDONE_O                                       = 0;
600
                        oHostDataAvailable    = 0;//1;
601
 
602
                        if (wVertexCount >= iPrimitiveCount)
603
                                rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
604
                        else
605
                                rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
606
 
607
                end
608
                //----------------------------------------
609
                /*
610
                        we wait until all the cores are ready for the next primitive,
611
                        this happens when the iHostDataReadConfirmed signal
612
                        gets asserted
613
                */
614
                `HOST_WAIT_DATA_READ_CONFIRMATION:
615
                begin
616
                        rWBMEnable            = 0;                                                               //Do not enable until we are resquested
617
                   rInitiaReadAddr       = 0;                                                            //Ignored
618
                        rWBMReset             = 0;                                                               //Continue from previous read address
619
                        oMemSelect            = `SELECT_GEO_MEM;                        //Use external GEO mem for reading
620
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
621
                        MST_O                   = 0;                                                             //The master signal goes to zero until request
622
                        rInitialWriteAddress  = `CREG_V0;                                               //Write starting from this location on the cores
623
         rSetWriteAddr         = 1;                                                             //Set to use the initial write address bellow
624
                        rCoreBroadCast        = 1;                                                              //From now on we only broadcast                                 
625
                        rIncCoreSelect        = 0;                                                               //Ignored during broadcasts     
626
                        RENDREN_O                                = `SELECT_ALL_CORES;
627
                        rResetVertexCount  = 0;
628
                        GACK_O                                   = 0;
629
                        //STDONE_O                                       = 0;
630
                        oHostDataAvailable    = 1;
631
 
632
                        if ( iHostDataReadConfirmed )
633
                                rHostNextState = `HOST_ACK_GEO_REQUEST;
634
                        else
635
                                rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
636
                end
637
                //----------------------------------------
638
                `HOST_LAST_PRIMITIVE_REACHED:
639
                begin
640
                        rWBMEnable            = 0;                                                               //Disable WBM when it is donw                                           
641
                   rInitiaReadAddr       = 32'hA;                                                       //Reset primitive counter to first primitive                                            
642
                        rWBMReset             = 1;                                                              //Reset primitive counter to first primitive            
643
                        oMemSelect            = `SELECT_GEO_MEM;
644
                        TGA_O                 = `TAG_DATA_ADDRESS_TYPE;
645
                        MST_O                   = 1;
646
                        rInitialWriteAddress  = 0;
647
         rSetWriteAddr         = 0;
648
                        rCoreBroadCast        = 1;
649
                        rIncCoreSelect        = 0;
650
                        RENDREN_O                                = `SELECT_ALL_CORES;
651
                        rResetVertexCount     = 0;                                                       //Reset the vertex count to zero
652
                        GACK_O                                   = 0;
653
                        //STDONE_O                                       = 1;
654
                        oHostDataAvailable    = 0;
655
 
656
 
657
 
658
                        if (iGPUCommitedResults)
659
                        begin
660
 
661
                        `ifndef NO_DISPLAY_STATS
662
                        for (i = 0; i < `MAX_CORES; i = i + 1)
663
                        begin
664
                                $write(".");
665
                        end
666
                        RenderedPixels = RenderedPixels + `MAX_CORES;
667
                        if ( RenderedPixels % iDebugWidth == 0)
668
                                $write("]%d\n[",RenderedPixels / iDebugWidth);
669
                        `endif
670
 
671
                                rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
672
                        end
673
                        else
674
                                rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
675
                end
676
                //----------------------------------------
677
                `HOST_GPU_EXECUTION_DONE:
678
                begin
679
                        $display("THEIA Execution done in %dns\n",$time-StartTime);
680
                  rWBMEnable            = 0;
681
                   rInitiaReadAddr       = 0;
682
                        rWBMReset             = 0;
683
                        oMemSelect            = 0;
684
                        TGA_O                 = 0;
685
                        MST_O                   = 0;
686
                        rInitialWriteAddress  = 0;
687
         rSetWriteAddr         = 0;
688
                        rCoreBroadCast        = 0;
689
                        rIncCoreSelect        = 0;
690
                        RENDREN_O                                = 0;
691
                        rResetVertexCount  = 0;
692
                        GACK_O                                   = 0;
693
                        //STDONE_O                                       = 0;
694
                        oHostDataAvailable    = 0;
695
 
696
                        rHostNextState = `HOST_GPU_EXECUTION_DONE;
697
                end
698
                //----------------------------------------
699
                default:
700
                begin
701
 
702
                        rWBMEnable            = 0;
703
                   rInitiaReadAddr       = 0;
704
                        rWBMReset             = 0;
705
                        oMemSelect            = 0;
706
                        TGA_O                 = 0;
707
                        MST_O                   = 0;
708
                        rInitialWriteAddress  = 0;
709
         rSetWriteAddr         = 0;
710
                        rCoreBroadCast        = 0;
711
                        rIncCoreSelect        = 0;
712
                        RENDREN_O                                = 0;
713
                        rResetVertexCount  = 0;
714
                        GACK_O                                   = 0;
715
                        //STDONE_O                                       = 0;
716
                        oHostDataAvailable    = 0;
717
 
718
                        rHostNextState = `HOST_IDLE;
719
                end
720
                //----------------------------------------
721
                endcase
722
end
723
 
724
endmodule

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