OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [trunk/] [rtl/] [Module_HostWBM.v] - Blame information for rev 211

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 152 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
3
 
4
//---------------------------------------------------------------
5
module WBMaster
6
(
7
        input wire Clock,
8
        input wire Reset,
9
        input wire iEnable,
10
        input wire iShortFlow,
11
        input wire [`WB_WIDTH-1:0]  iInitialReadAddr,
12
        input wire [`WB_WIDTH-1:0]  iWriteAddr,
13
        output wire [`WB_WIDTH-1:0] oReadAddress,
14
        input wire [`WB_WIDTH-1:0]  iReadData,
15
 
16
        output reg  STB_O,
17
        input wire   ACK_I,
18
        output wire  CYC_O,
19
        output wire [`WB_WIDTH-1:0] DAT_O,
20
        output wire [`WB_WIDTH-1:0] ADR_O,
21
        output wire oDone
22
);
23
 
24
        assign ADR_O = iWriteAddr;
25
        wire [3:0] wXYZSel_Long;
26
        wire [2:0] wXYZSel_Short;
27
 
28
        UPCOUNTER_POSEDGE # (`WB_WIDTH) WBM_O_READ_ADDRESS
29
        (
30
        .Clock(Clock),
31
        .Reset( Reset ),
32
        .Enable(iEnable & ACK_I),
33
        .Initial(iInitialReadAddr),
34
        .Q(oReadAddress)
35
        );
36
 
37
        CIRCULAR_SHIFTLEFT_POSEDGE #(4) SHL
38
        (
39
  .Clock(Clock),
40
  .Enable(ACK_I & iEnable),
41
  .Reset( Reset ),
42
  .Initial(4'b1),
43
  .O(wXYZSel_Long)
44
 
45
        );
46
        CIRCULAR_SHIFTLEFT_POSEDGE #(3) SHL2
47
        (
48
  .Clock(Clock),
49
  .Enable(ACK_I & iEnable),
50
  .Reset( Reset ),
51
  .Initial(3'b1),
52
  .O(wXYZSel_Short)
53
 
54
        );
55
 
56
        assign oDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
57
        assign DAT_O = iReadData;
58
 
59
        assign CYC_O = iEnable;
60
 
61
        always @ (posedge Clock)
62
        begin
63
        if (iEnable )
64
                STB_O <= ~ACK_I;
65
        else
66
                STB_O <= 0;
67
        end
68
 
69
 
70
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.