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diegovalve |
`timescale 1ns / 1ps
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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//--------------------------------------------------------
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//Dual port RAM.
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module RAM_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 )
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(
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input wire Clock,
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input wire iWriteEnable,
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input wire[ADDR_WIDTH-1:0] iReadAddress0,
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input wire[ADDR_WIDTH-1:0] iReadAddress1,
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input wire[ADDR_WIDTH-1:0] iWriteAddress,
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input wire[DATA_WIDTH-1:0] iDataIn,
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output reg [DATA_WIDTH-1:0] oDataOut0,
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output reg [DATA_WIDTH-1:0] oDataOut1
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);
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reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0];
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always @(posedge Clock)
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begin
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if (iWriteEnable)
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Ram[iWriteAddress] <= iDataIn;
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oDataOut0 <= Ram[iReadAddress0];
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oDataOut1 <= Ram[iReadAddress1];
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end
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endmodule
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//--------------------------------------------------------
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module RAM_SINGLE_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 )
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(
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input wire Clock,
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input wire iWriteEnable,
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input wire[ADDR_WIDTH-1:0] iReadAddress0,
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input wire[ADDR_WIDTH-1:0] iWriteAddress,
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input wire[DATA_WIDTH-1:0] iDataIn,
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output reg [DATA_WIDTH-1:0] oDataOut0
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);
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reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0];
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always @(posedge Clock)
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begin
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if (iWriteEnable)
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Ram[iWriteAddress] <= iDataIn;
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oDataOut0 <= Ram[iReadAddress0];
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end
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endmodule
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