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[/] [theia_gpu/] [trunk/] [rtl/] [Module_Swizzle.v] - Blame information for rev 208

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`timescale 1ns / 1ps
 `include "aDefinitions.v"
 //---------------------------------------------------------------------------
 module Swizzle3D
(
        input wire [`WIDTH-1:0] Source0_X,
        input wire [`WIDTH-1:0] Source0_Y,
        input wire [`WIDTH-1:0] Source0_Z,
        input wire [`WIDTH-1:0] iOperation,
 
        output reg [`WIDTH-1:0] SwizzleX,
        output reg [`WIDTH-1:0] SwizzleY,
        output reg [`WIDTH-1:0] SwizzleZ
 
 );
 
 //wire [31:0] SwizzleX,SwizzleY,SwizzleZ;
 //-----------------------------------------------------
 always @ ( * )
 begin
        case (iOperation)
                        `SWIZZLE_XXX:   SwizzleX = Source0_X;
                        `SWIZZLE_YYY:   SwizzleX = Source0_Y;
                        `SWIZZLE_ZZZ:   SwizzleX = Source0_Z;
                        `SWIZZLE_YXZ:   SwizzleX = Source0_Y;
                        default:                SwizzleX =  `DATA_ROW_WIDTH'd0;
        endcase
end
//-----------------------------------------------------
 always @ ( * )
 begin
        case (iOperation)
                        `SWIZZLE_XXX:   SwizzleY = Source0_X;
                        `SWIZZLE_YYY:   SwizzleY = Source0_Y;
                        `SWIZZLE_ZZZ:   SwizzleY = Source0_Z;
                        `SWIZZLE_YXZ:  SwizzleY = Source0_X;
                        default:                SwizzleY =  `DATA_ROW_WIDTH'd0;
        endcase
end
//-----------------------------------------------------
 always @ ( * )
 begin
        case (iOperation)
                        `SWIZZLE_XXX:   SwizzleZ = Source0_X;
                        `SWIZZLE_YYY:   SwizzleZ = Source0_Y;
                        `SWIZZLE_ZZZ:   SwizzleZ = Source0_Z;
                        `SWIZZLE_YXZ:  SwizzleZ = Source0_Z;
                        default:                SwizzleZ =  `DATA_ROW_WIDTH'd0;
        endcase
 end
 //-----------------------------------------------------
 endmodule
//---------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	152	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`//---------------------------------------------------------------------------`
4			`module Swizzle3D`
5			`(`
6			input wire [`WIDTH-1:0] Source0_X,
7			input wire [`WIDTH-1:0] Source0_Y,
8			input wire [`WIDTH-1:0] Source0_Z,
9			input wire [`WIDTH-1:0] iOperation,
10
11			output reg [`WIDTH-1:0] SwizzleX,
12			output reg [`WIDTH-1:0] SwizzleY,
13			output reg [`WIDTH-1:0] SwizzleZ
14
15			`);`
16
17			`//wire [31:0] SwizzleX,SwizzleY,SwizzleZ;`
18			`//-----------------------------------------------------`
19			`always @ ( * )`
20			`begin`
21			`case (iOperation)`
22			`SWIZZLE_XXX: SwizzleX = Source0_X;
23			`SWIZZLE_YYY: SwizzleX = Source0_Y;
24			`SWIZZLE_ZZZ: SwizzleX = Source0_Z;
25			`SWIZZLE_YXZ: SwizzleX = Source0_Y;
26			default: SwizzleX = `DATA_ROW_WIDTH'd0;
27			`endcase`
28			`end`
29			`//-----------------------------------------------------`
30			`always @ ( * )`
31			`begin`
32			`case (iOperation)`
33			`SWIZZLE_XXX: SwizzleY = Source0_X;
34			`SWIZZLE_YYY: SwizzleY = Source0_Y;
35			`SWIZZLE_ZZZ: SwizzleY = Source0_Z;
36			`SWIZZLE_YXZ: SwizzleY = Source0_X;
37			default: SwizzleY = `DATA_ROW_WIDTH'd0;
38			`endcase`
39			`end`
40			`//-----------------------------------------------------`
41			`always @ ( * )`
42			`begin`
43			`case (iOperation)`
44			`SWIZZLE_XXX: SwizzleZ = Source0_X;
45			`SWIZZLE_YYY: SwizzleZ = Source0_Y;
46			`SWIZZLE_ZZZ: SwizzleZ = Source0_Z;
47			`SWIZZLE_YXZ: SwizzleZ = Source0_Z;
48			default: SwizzleZ = `DATA_ROW_WIDTH'd0;
49			`endcase`
50			`end`
51			`//-----------------------------------------------------`
52			`endmodule`
53			`//---------------------------------------------------------------------------`

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[/] [theia_gpu/] [trunk/] [rtl/] [Module_Swizzle.v] - Blame information for rev 208