OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [trunk/] [rtl/] [Theia_Core.v] - Blame information for rev 193

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 152 diegovalve
/**********************************************************************************
2
Theia, Ray Cast Programable graphic Processing Unit.
3
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
4
 
5
This program is free software; you can redistribute it and/or
6
modify it under the terms of the GNU General Public License
7
as published by the Free Software Foundation; either version 2
8
of the License, or (at your option) any later version.
9
 
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14
 
15
You should have received a copy of the GNU General Public License
16
along with this program; if not, write to the Free Software
17
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18
 
19
***********************************************************************************/
20
 
21
/**********************************************************************************
22
Description:
23
 This is the top level block for THEIA.
24
 THEIA core has 5 main logical blocks called Units.
25
 This module implements the interconections between the Units.
26
 
27
 Units:
28
  > EXE: Mananges execution logic for the SHADERS.
29
  > GEO: Manages geometry data structures.
30
  > IO: Input/Output (Wishbone).
31
  > MEM: Internal memory, separate for Instructions and data.
32
  > CONTROL: Main control Finite state machine.
33
 
34
 Internal Buses:
35
        THEIA has separate instruction and data buses.
36
        THEIA avoids using tri-state buses by having separate input/output
37
        for each bus.
38
        There are 2 separate data buses since the Data memory
39
        has a Dual read channel.
40
   Please see the MEM unit chapter in the documentation for more details.
41
 
42
 External Buses:
43
        External buses are managed by the IO Unit.
44
        External buses follow the wishbone protocol.
45
        Please see the IO unit chapter in the documentation for more details.
46
**********************************************************************************/
47
 
48
`timescale 1ns / 1ps
49
`include "aDefinitions.v"
50
 
51
module THEIACORE
52
(
53
 
54
input wire                    CLK_I,    //Input clock
55
input wire                    RST_I,    //Input reset
56
//Theia Interfaces
57
input wire                    MST_I,    //Master signal, THEIA enters configuration mode
58
                                       //when this gets asserted (see documentation)
59
//Wish Bone Interface
60
input wire [`WB_WIDTH-1:0]    DAT_I,     //Input data bus  (Wishbone)
61
output wire [`WB_WIDTH-1:0]   DAT_O,     //Output data bus (Wishbone)
62
input wire                    ACK_I,    //Input ack
63
output wire                   ACK_O,    //Output ack
64
output wire [`WB_WIDTH-1:0]   ADR_O,     //Output address
65
input wire [`WB_WIDTH-1:0]    ADR_I,     //Input address
66
output wire                   WE_O,             //Output write enable
67
input wire                    WE_I,    //Input write enable
68
output wire                   STB_O,    //Strobe signal, see wishbone documentation
69
input wire                    STB_I,    //Strobe signal, see wishbone documentation
70
output wire                   CYC_O,    //Bus cycle signal, see wishbone documentation
71
input wire                    CYC_I,   //Bus cycle signal, see wishbone documentation
72
output wire     [1:0]             TGC_O,   //Bus cycle tag, see THEAI documentation
73
input wire [1:0]              TGA_I,   //Input address tag, see THEAI documentation
74
output wire [1:0]             TGA_O,   //Output address tag, see THEAI documentation
75
input wire      [1:0]             TGC_I,   //Bus cycle tag, see THEAI documentation
76
input wire                    GNT_I,   //Bus arbiter 'Granted' signal, see THEAI documentation
77
input wire                    RENDREN_I,
78
 
79
output wire                  HDL_O,             //Data Latched
80
input wire                   HDLACK_I, //Data Latched ACK
81
input wire                   STDONE_I,          //Scene traverse complete
82
input wire                   HDA_I,
83
output wire                  RCOMMIT_O,
84
 
85
output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
86
output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
87
output wire                                              OMEM_WE_O,
88
 
89
input wire                  TMEM_ACK_I,
90
input wire [`WB_WIDTH-1:0]  TMEM_DAT_I ,
91
output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
92
output wire                 TMEM_WE_O,
93
output wire                 TMEM_STB_O,
94
output wire                 TMEM_CYC_O,
95
input wire                  TMEM_GNT_I,
96
 
97
`ifdef DEBUG
98
input wire[`MAX_CORES-1:0]    iDebug_CoreID,
99
`endif
100
//Control Register
101
input wire [15:0]                         CREG_I,
102
output wire                   DONE_O
103
 
104
 
105
);
106
 
107
//When we flip the SMEM, this means we are ready to receive more data
108
 
109
 
110
//Alias this signals
111
wire Clock,Reset;
112
assign Clock = CLK_I;
113
assign Reset = RST_I;
114
 
115
wire                              wIO_Busy;
116
wire [`DATA_ROW_WIDTH-1:0]                        wEXE_2__MEM_WriteData;
117
wire [`DATA_ROW_WIDTH-1:0]                        wUCODE_RAMBus;
118
wire [`DATA_ADDRESS_WIDTH-1:0]    wEXE_2__MEM_wDataWriteAddress;
119
wire                              w2IO__AddrIsImm;
120
wire [`DATA_ADDRESS_WIDTH-1:0]    wUCODE_RAMAddress;
121
wire [`DATA_ADDRESS_WIDTH-1:0]    w2IO__Adr_O_Pointer;
122
wire [`DATA_ADDRESS_WIDTH-1:0]    wGEO2_IO__Adr_O_Pointer;
123
wire                                                                             wEXE_2__DataWriteEnable;
124
wire                                                                             wUCODE_RAMWriteEnable;
125
//wire [2:0]                                                             RamBusOwner;
126
//Unit intercoanection wires
127
 
128
wire                                                                            wCU2__MicrocodeExecutionDone;
129
wire [`ROM_ADDRESS_WIDTH-1:0]            InitialCodeAddress;
130
wire [`ROM_ADDRESS_WIDTH-1:0]            wInstructionPointer1,wInstructionPointer2;
131
wire [`INSTRUCTION_WIDTH-1:0]    wEncodedInstruction1,wEncodedInstruction2,wIO2_MEM__ExternalInstruction;
132
wire                                                                            wCU2__ExecuteMicroCode;
133
wire  [`ROM_ADDRESS_WIDTH-1:0]   wIO2_MEM__InstructionWriteAddr;
134
wire [95:0]                                                      wMEM_2__EXE_DataRead0, wMEM_2__EXE_DataRead1,wMEM_2__IO_DataRead0, wMEM_2__IO_DataRead1;
135
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE_2__MEM_DataReadAddress0,wEXE_2__MEM_DataReadAddress1;
136
wire [`DATA_ADDRESS_WIDTH-1:0]   wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
137
 
138
 
139
wire [`WIDTH-1:0]                                        w2IO__AddressOffset;
140
wire [`DATA_ADDRESS_WIDTH-1:0]   w2IO__DataWriteAddress;
141
wire                                                                            w2IO__Store;
142
wire                                                                            w2IO__EnableWBMaster;
143
 
144
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO2_MEM__DataWriteAddress;
145
wire [`DATA_ADDRESS_WIDTH-1:0]   wIO_2_MEM__DataReadAddress0;
146
wire [`DATA_ROW_WIDTH-1:0]               wIO2_MEM__Bus;
147
wire [`WIDTH-1:0]                                        wIO2_MEM__Data;
148
wire [`WIDTH-1:0]                                        wIO2_WBM__Address;
149
wire                                                                            wIO2_MEM__DataWriteEnable;
150
wire                                                                            wIO2__Done;
151
wire                                                                            wCU2_GEO__GeometryFetchEnable;
152
wire                                                                            wIFU2__MicroCodeReturnValue;
153
wire                                                                            wCU2_BCU__ACK;
154
wire                                                                            wGEO2_CU__RequestAABBIU;
155
wire                                                                            wGEO2_CU__RequestBIU;
156
wire                             wGEO2_CU__RequestTCC;
157
wire                                                                            wGEO2_CU__GeometryUnitDone;
158
wire                                                                            wGEO2_CU__Sync;
159
wire                                                                            wEXE2__uCodeDone;
160
wire                                                                            wEXE2_IFU__EXEBusy;
161
wire [`DATA_ADDRESS_WIDTH-1:0]   wEXE2_IDU_DataFordward_LastDestination;
162
wire                                                                            wALU2_EXE__BranchTaken;
163
wire                                                                            wALU2_IFU_BranchNotTaken;
164
wire                                                                            w2IO__SetAddress;
165
wire                                                                            wIDU2_IFU__IDUBusy;
166
//Control Registe wires
167
wire[15:0]                                                               wCR2_ControlRegister;
168
wire                                                                            wCR2_TextureMappingEnabled;
169
wire                             wGEO2_CU__TFFDone;
170
wire                             wCU2_GEO__TriggerTFF;
171
wire                             wIO2_MEM_InstructionWriteEnable;
172
wire                             wCU2_IO__WritePixel;
173
wire                             wGEO2_IO__AddrIsImm;
174
wire[31:0]                       wGEO2_IO__AddressOffset;
175
wire                             wGEO2_IO__EnableWBMaster;
176
wire                             wGEO2_IO__SetAddress;
177
wire[`WIDTH-1:0]                 wGEO2__CurrentPitch,wCU2_GEO_Pitch;
178
wire                             wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
179
 
180
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteAddress;
181
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteData;
182
wire wEXE_2__IO_OMEMWriteEnable;
183
 
184
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_TMEMAddress;
185
wire [`DATA_ROW_WIDTH-1:0] wIO_2_EXE__TMEMData;
186
wire wIO_2_EXE__DataAvailable;
187
wire wEXE_2_IO__DataRequest;
188
wire wCU2_FlipMem;
189
wire wCU2_FlipMemEnabled;
190
wire w2MEM_FlipMemory;
191
wire wGEO2__RequestingTextures;
192
wire w2IO_WriteBack_Set;
193
wire[`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress1;
194
 
195
`ifdef DEBUG
196
        wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
197
`endif
198
//--------------------------------------------------------
199
 
200
assign HDL_O = wCU2_FlipMem;
201
 
202
assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
203
 
204
//--------------------------------------------------------
205
//Control Unit Instance
206
        ControlUnit CU
207
        (
208
           .Clock(Clock),
209
                .Reset(Reset),
210
                .oFlipMemEnabled(                   wCU2_FlipMemEnabled            ),
211
                .oFlipMem(                          wCU2_FlipMem                   ),
212
                .iControlRegister(                  wCR2_ControlRegister           ),
213
                //.oRamBusOwner(                      RamBusOwner                    ),
214
                .oGFUEnable(                        wCU2_GEO__GeometryFetchEnable  ),
215
                .iTriggerAABBIURequest(             wGEO2_CU__RequestAABBIU        ),
216
                .iTriggerBIURequest(                wGEO2_CU__RequestBIU           ),
217
                .iTriggertTCCRequest(               wGEO2_CU__RequestTCC           ),
218
                .oUCodeEnable(                      wCU2__ExecuteMicroCode         ),
219
                .oCodeInstructioPointer(           InitialCodeAddress             ),
220
                .iUCodeDone(                        wCU2__MicrocodeExecutionDone   ),
221
                .iIODone(                           wIO2__Done                     ),
222
                .oIOWritePixel(                     wCU2_IO__WritePixel            ),
223
                .iUCodeReturnValue(                 wIFU2__MicroCodeReturnValue    ),
224
                .iGEOSync(                          wGEO2_CU__Sync                 ),
225
                .iTFFDone(                          wGEO2_CU__TFFDone              ),
226
                .oTriggerTFF(                       wCU2_GEO__TriggerTFF           ),
227
                .MST_I(                             MST_I                          ),
228
                .oSetCurrentPitch(                  wCU2_GEO__SetPitch             ),
229
                .iGFUDone(                          wGEO2_CU__GeometryUnitDone     ),
230
                .iRenderEnable(                     RENDREN_I                      ),
231
                .iSceneTraverseComplete(            STDONE_I                       ),
232
                .oResultCommited(                   RCOMMIT_O                      ),
233
                .iHostDataAvailable(                HDA_I                                                                        ),
234
                .iHostAckDataRead(                  HDLACK_I                       ),
235
 
236
 
237
                `ifdef DEBUG
238
                .iDebug_CoreID( iDebug_CoreID ),
239
                `endif
240
                .oDone(                             DONE_O                         )
241
 
242
        );
243
 
244
 
245
 
246
 
247
//--------------------------------------------------------      
248
 
249
//assign w2MEM_FlipMemory =  (wCU2__ExecuteMicroCode | wCU2_FlipMem ) & wCU2_FlipMemEnabled;
250
assign w2MEM_FlipMemory =  wCU2_FlipMem  & wCU2_FlipMemEnabled;
251
MemoryUnit MEM
252
(
253
.Clock(Clock),
254
.Reset(Reset),
255
 
256
.iFlipMemory( w2MEM_FlipMemory ),
257
 
258
//Data Bus to/from EXE
259
.iDataReadAddress1_EXE(       wEXE_2__MEM_DataReadAddress0        ),
260
.iDataReadAddress2_EXE(       wEXE_2__MEM_DataReadAddress1        ),
261
.oData1_EXE(                  wMEM_2__EXE_DataRead0               ),
262
.oData2_EXE(                  wMEM_2__EXE_DataRead1               ),
263
.iDataWriteEnable_EXE(        wEXE_2__DataWriteEnable          ),
264
.iDataWriteAddress_EXE(       wEXE_2__MEM_wDataWriteAddress        ),
265
.iData_EXE(                   wEXE_2__MEM_WriteData          ),
266
 
267
//Data Bus to/from IO
268
 
269
.iDataReadAddress1_IO(       wIO_2_MEM__DataReadAddress0        ),
270
.iDataReadAddress2_IO(       wIO_2_MEM__DataReadAddress1        ),
271
.oData1_IO(                  wMEM_2__IO_DataRead0               ),
272
.oData2_IO(                  wMEM_2__IO_DataRead1               ),
273
.iDataWriteEnable_IO(        wIO2_MEM__DataWriteEnable          ),
274
.iDataWriteAddress_IO(       wIO2_MEM__DataWriteAddress        ),
275
.iData_IO(                   wIO2_MEM__Bus          ),
276
 
277
`ifdef DEBUG
278
.iDebug_CoreID( iDebug_CoreID ),
279
`endif
280
 
281
 
282
//Instruction Bus
283
.iInstructionReadAddress1(  wInstructionPointer1             ),
284
.iInstructionReadAddress2(  wInstructionPointer2             ),
285
.oInstruction1(             wEncodedInstruction1             ),
286
.oInstruction2(             wEncodedInstruction2             ),
287
.iInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
288
.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr  ),
289
.iInstruction(             wIO2_MEM__ExternalInstruction   ),
290
.iControlRegister(         CREG_I                          ),
291
.oControlRegister(         wCR2_ControlRegister            )
292
 
293
);
294
 
295
////--------------------------------------------------------
296
 
297
 
298
ExecutionUnit EXE
299
(
300
 
301
.Clock( Clock),
302
.Reset( Reset ),
303
.iInitialCodeAddress(    InitialCodeAddress     ),
304
.iInstruction1(          wEncodedInstruction1      ),
305
.iInstruction2(          wEncodedInstruction2      ),
306
.oInstructionPointer1(   wInstructionPointer1    ),
307
.oInstructionPointer2(   wInstructionPointer2    ),
308
.iDataRead0(             wMEM_2__EXE_DataRead0             ),
309
.iDataRead1(             wMEM_2__EXE_DataRead1             ),
310
.iTrigger(               wCU2__ExecuteMicroCode ),
311
.oDataReadAddress0( wEXE_2__MEM_DataReadAddress0 ),
312
.oDataReadAddress1( wEXE_2__MEM_DataReadAddress1 ),
313
.oDataWriteEnable(  wEXE_2__DataWriteEnable  ),
314
.oDataWriteAddress( wEXE_2__MEM_wDataWriteAddress      ),
315
.oDataBus(          wEXE_2__MEM_WriteData          ),
316
.oReturnCode(       wIFU2__MicroCodeReturnValue ),
317
/**************/
318
.oOMEMWriteAddress(   wEXE_2__IO_WriteAddress ),
319
.oOMEMWriteData(      wEXE_2__IO_WriteData    ),
320
.oOMEMWriteEnable(  wEXE_2__IO_OMEMWriteEnable ),
321
 
322
.oTMEMReadAddress(   wEXE_2__IO_TMEMAddress   ),
323
.iTMEMReadData(      wIO_2_EXE__TMEMData      ),
324
.iTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
325
.oTMEMDataRequest(   wEXE_2_IO__DataRequest   ),
326
/**************/
327
`ifdef DEBUG
328
.iDebug_CoreID( iDebug_CoreID ),
329
`endif
330
.oDone(             wCU2__MicrocodeExecutionDone )
331
 
332
);
333
 
334
////--------------------------------------------------------
335
 
336
 
337
assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
338
//---------------------------------------------------------------------------------------------------
339
 
340
//assign wEXE_2__MEM_DataReadAddress1 = (wCU2_IO__WritePixel == 0) ?  wUCODE_RAMReadAddress1 : wIO_2_MEM__DataReadAddress1;
341
assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
342
assign w2IO__AddrIsImm       = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm       : 1'b0;
343
assign w2IO__AddressOffset   = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset   : 32'b0;
344
assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_ADDR_O;
345
//assign w2IO__Adr_O_Pointer      = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `CREG_PIXEL_2D_INITIAL_POSITION; 
346
 
347
wire w2IO_MasterCycleType;
348
assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
349
 
350
 
351
 
352
assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
353
 
354
 
355
IO_Unit IO
356
(
357
 .Clock(               Clock                            ),
358
 .Reset(               Reset                            ),
359
 .iEnable(           1'b0 ),// w2IO__EnableWBMaster              ),
360
 .iBusCyc_Type(         w2IO_MasterCycleType            ),
361
 
362
 .iStore(              1'b1),//w2IO__Store                      ),
363
 .iAdr_DataWriteBack(    w2IO__DataWriteAddress         ),
364
 .iAdr_O_Set(      w2IO__SetAddress                     ),
365
 .iAdr_O_Imm(       w2IO__AddressOffset                 ),
366
 .iAdr_O_Type(      w2IO__AddrIsImm                     ),
367
 .iAdr_O_Pointer(  w2IO__Adr_O_Pointer                  ),
368
 .iReadDataBus(        wMEM_2__IO_DataRead0                       ),
369
 .iReadDataBus2(        wMEM_2__IO_DataRead1                       ),
370
 .iDat_O_Pointer(     `OREG_PIXEL_COLOR                 ),
371
 
372
 
373
 .oDataReadAddress(    wIO_2_MEM__DataReadAddress0      ),
374
 .oDataReadAddress2(   wIO_2_MEM__DataReadAddress1       ),
375
 .oDataWriteAddress(   wIO2_MEM__DataWriteAddress    ),
376
 .oDataBus(               wIO2_MEM__Bus                 ),
377
 .oInstructionBus(     wIO2_MEM__ExternalInstruction    ),
378
 
379
 .oDataWriteEnable(         wIO2_MEM__DataWriteEnable    ),
380
 .oData(                    wIO2_MEM__Data                       ),
381
 .oInstructionWriteEnable(  wIO2_MEM_InstructionWriteEnable ),
382
 .oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
383
 .iWriteBack_Set( w2IO_WriteBack_Set ),
384
 .oBusy(                      wIO_Busy                  ),
385
 .oDone(               wIO2__Done                       ),
386
 /**********/
387
 .iOMEM_WriteAddress(   wEXE_2__IO_WriteAddress         ),
388
 .iOMEM_WriteData(      wEXE_2__IO_WriteData            ),
389
 .iOMEM_WriteEnable(    wEXE_2__IO_OMEMWriteEnable    ),
390
 .OMEM_DAT_O( OMEM_DAT_O ),
391
 .OMEM_ADR_O( OMEM_ADR_O ),
392
 .OMEM_WE_O( OMEM_WE_O ),
393
 
394
 
395
 .oTMEMReadData(      wIO_2_EXE__TMEMData      ),
396
 .iTMEMDataRequest(   wEXE_2_IO__DataRequest   ),
397
 .iTMEMReadAddress(   wEXE_2__IO_TMEMAddress   ),
398
 .oTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
399
 
400
.TMEM_ACK_I( TMEM_ACK_I ),
401
.TMEM_DAT_I( TMEM_DAT_I ),
402
.TMEM_ADR_O( TMEM_ADR_O ),
403
.TMEM_WE_O(  TMEM_WE_O  ),
404
.TMEM_STB_O( TMEM_STB_O ),
405
.TMEM_CYC_O( TMEM_CYC_O ),
406
.TMEM_GNT_I( TMEM_GNT_I ),
407
 
408
 /**********/
409
 .MST_I( MST_I ),
410
  //Wish Bone Interface
411
.DAT_I( DAT_I ),
412
.DAT_O( DAT_O ),
413
.ACK_I( ACK_I & GNT_I ),
414
.ACK_O( ACK_O ),
415
.ADR_O( ADR_O ),
416
.ADR_I( ADR_I ),
417
.WE_O(  WE_O  ),
418
.WE_I(  WE_I  ),
419
.STB_O( STB_O ),
420
.STB_I( STB_I ),
421
.CYC_O( CYC_O ),
422
.TGA_I( TGA_I ),
423
.CYC_I( CYC_I ),
424
.GNT_I( GNT_I ),
425
.TGC_O( TGC_O )
426
 
427
 
428
);
429
//---------------------------------------------------------------------------------------------------
430
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.