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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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/**********************************************************************************
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Description:
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This is the top level block for THEIA.
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THEIA core has 5 main logical blocks called Units.
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This module implements the interconections between the Units.
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Units:
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> EXE: Mananges execution logic for the SHADERS.
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> GEO: Manages geometry data structures.
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> IO: Input/Output (Wishbone).
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> MEM: Internal memory, separate for Instructions and data.
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> CONTROL: Main control Finite state machine.
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Internal Buses:
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THEIA has separate instruction and data buses.
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THEIA avoids using tri-state buses by having separate input/output
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for each bus.
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There are 2 separate data buses since the Data memory
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has a Dual read channel.
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Please see the MEM unit chapter in the documentation for more details.
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External Buses:
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External buses are managed by the IO Unit.
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External buses follow the wishbone protocol.
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Please see the IO unit chapter in the documentation for more details.
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**********************************************************************************/
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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module THEIACORE
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(
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input wire CLK_I, //Input clock
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input wire RST_I, //Input reset
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//Theia Interfaces
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input wire MST_I, //Master signal, THEIA enters configuration mode
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//when this gets asserted (see documentation)
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//Wish Bone Interface
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
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input wire ACK_I, //Input ack
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output wire ACK_O, //Output ack
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output wire [`WB_WIDTH-1:0] ADR_O, //Output address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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output wire WE_O, //Output write enable
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input wire WE_I, //Input write enable
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output wire STB_O, //Strobe signal, see wishbone documentation
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input wire STB_I, //Strobe signal, see wishbone documentation
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output wire CYC_O, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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input wire GNT_I, //Bus arbiter 'Granted' signal, see THEAI documentation
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input wire RENDREN_I,
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output wire HDL_O, //Data Latched
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input wire HDLACK_I, //Data Latched ACK
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input wire STDONE_I, //Scene traverse complete
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input wire HDA_I,
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output wire RCOMMIT_O,
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output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
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output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
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output wire OMEM_WE_O,
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input wire TMEM_ACK_I,
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input wire [`WB_WIDTH-1:0] TMEM_DAT_I ,
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output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
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output wire TMEM_WE_O,
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output wire TMEM_STB_O,
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output wire TMEM_CYC_O,
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input wire TMEM_GNT_I,
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`ifdef DEBUG
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input wire[`MAX_CORES-1:0] iDebug_CoreID,
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`endif
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//Control Register
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input wire [15:0] CREG_I,
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output wire DONE_O
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);
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//When we flip the SMEM, this means we are ready to receive more data
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//Alias this signals
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wire Clock,Reset;
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assign Clock = CLK_I;
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assign Reset = RST_I;
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wire wIO_Busy;
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wire [`DATA_ROW_WIDTH-1:0] wEXE_2__MEM_WriteData;
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wire [`DATA_ROW_WIDTH-1:0] wUCODE_RAMBus;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE_2__MEM_wDataWriteAddress;
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wire w2IO__AddrIsImm;
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wire [`DATA_ADDRESS_WIDTH-1:0] wUCODE_RAMAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2IO__Adr_O_Pointer;
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wire [`DATA_ADDRESS_WIDTH-1:0] wGEO2_IO__Adr_O_Pointer;
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wire wEXE_2__DataWriteEnable;
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wire wUCODE_RAMWriteEnable;
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//wire [2:0] RamBusOwner;
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//Unit intercoanection wires
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wire wCU2__MicrocodeExecutionDone;
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wire [`ROM_ADDRESS_WIDTH-1:0] InitialCodeAddress;
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wire [`ROM_ADDRESS_WIDTH-1:0] wInstructionPointer1,wInstructionPointer2;
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wire [`INSTRUCTION_WIDTH-1:0] wEncodedInstruction1,wEncodedInstruction2,wIO2_MEM__ExternalInstruction;
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wire wCU2__ExecuteMicroCode;
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wire [`ROM_ADDRESS_WIDTH-1:0] wIO2_MEM__InstructionWriteAddr;
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wire [95:0] wMEM_2__EXE_DataRead0, wMEM_2__EXE_DataRead1,wMEM_2__IO_DataRead0, wMEM_2__IO_DataRead1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE_2__MEM_DataReadAddress0,wEXE_2__MEM_DataReadAddress1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
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wire [`WIDTH-1:0] w2IO__AddressOffset;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2IO__DataWriteAddress;
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wire w2IO__Store;
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wire w2IO__EnableWBMaster;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIO2_MEM__DataWriteAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress0;
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wire [`DATA_ROW_WIDTH-1:0] wIO2_MEM__Bus;
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wire [`WIDTH-1:0] wIO2_MEM__Data;
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wire [`WIDTH-1:0] wIO2_WBM__Address;
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wire wIO2_MEM__DataWriteEnable;
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wire wIO2__Done;
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wire wCU2_GEO__GeometryFetchEnable;
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wire wIFU2__MicroCodeReturnValue;
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wire wCU2_BCU__ACK;
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wire wGEO2_CU__RequestAABBIU;
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wire wGEO2_CU__RequestBIU;
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wire wGEO2_CU__RequestTCC;
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wire wGEO2_CU__GeometryUnitDone;
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wire wGEO2_CU__Sync;
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wire wEXE2__uCodeDone;
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wire wEXE2_IFU__EXEBusy;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE2_IDU_DataFordward_LastDestination;
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wire wALU2_EXE__BranchTaken;
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wire wALU2_IFU_BranchNotTaken;
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wire w2IO__SetAddress;
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wire wIDU2_IFU__IDUBusy;
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//Control Registe wires
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wire[15:0] wCR2_ControlRegister;
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wire wCR2_TextureMappingEnabled;
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wire wGEO2_CU__TFFDone;
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wire wCU2_GEO__TriggerTFF;
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wire wIO2_MEM_InstructionWriteEnable;
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wire wCU2_IO__WritePixel;
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wire wGEO2_IO__AddrIsImm;
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wire[31:0] wGEO2_IO__AddressOffset;
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wire wGEO2_IO__EnableWBMaster;
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wire wGEO2_IO__SetAddress;
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wire[`WIDTH-1:0] wGEO2__CurrentPitch,wCU2_GEO_Pitch;
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wire wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
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wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteAddress;
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wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_WriteData;
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wire wEXE_2__IO_OMEMWriteEnable;
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wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_TMEMAddress;
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wire [`DATA_ROW_WIDTH-1:0] wIO_2_EXE__TMEMData;
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wire wIO_2_EXE__DataAvailable;
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wire wEXE_2_IO__DataRequest;
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wire wCU2_FlipMem;
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wire wCU2_FlipMemEnabled;
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wire w2MEM_FlipMemory;
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wire wGEO2__RequestingTextures;
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wire w2IO_WriteBack_Set;
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wire[`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress1;
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`ifdef DEBUG
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wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
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`endif
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//--------------------------------------------------------
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assign HDL_O = wCU2_FlipMem;
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assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
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//--------------------------------------------------------
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//Control Unit Instance
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ControlUnit CU
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(
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.Clock(Clock),
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.Reset(Reset),
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.oFlipMemEnabled( wCU2_FlipMemEnabled ),
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.oFlipMem( wCU2_FlipMem ),
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.iControlRegister( wCR2_ControlRegister ),
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//.oRamBusOwner( RamBusOwner ),
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.oGFUEnable( wCU2_GEO__GeometryFetchEnable ),
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.iTriggerAABBIURequest( wGEO2_CU__RequestAABBIU ),
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.iTriggerBIURequest( wGEO2_CU__RequestBIU ),
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.iTriggertTCCRequest( wGEO2_CU__RequestTCC ),
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.oUCodeEnable( wCU2__ExecuteMicroCode ),
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.oCodeInstructioPointer( InitialCodeAddress ),
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.iUCodeDone( wCU2__MicrocodeExecutionDone ),
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.iIODone( wIO2__Done ),
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.oIOWritePixel( wCU2_IO__WritePixel ),
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.iUCodeReturnValue( wIFU2__MicroCodeReturnValue ),
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.iGEOSync( wGEO2_CU__Sync ),
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.iTFFDone( wGEO2_CU__TFFDone ),
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.oTriggerTFF( wCU2_GEO__TriggerTFF ),
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.MST_I( MST_I ),
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.oSetCurrentPitch( wCU2_GEO__SetPitch ),
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.iGFUDone( wGEO2_CU__GeometryUnitDone ),
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.iRenderEnable( RENDREN_I ),
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.iSceneTraverseComplete( STDONE_I ),
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.oResultCommited( RCOMMIT_O ),
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.iHostDataAvailable( HDA_I ),
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.iHostAckDataRead( HDLACK_I ),
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`ifdef DEBUG
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.iDebug_CoreID( iDebug_CoreID ),
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`endif
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.oDone( DONE_O )
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);
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//--------------------------------------------------------
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//assign w2MEM_FlipMemory = (wCU2__ExecuteMicroCode | wCU2_FlipMem ) & wCU2_FlipMemEnabled;
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assign w2MEM_FlipMemory = wCU2_FlipMem & wCU2_FlipMemEnabled;
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MemoryUnit MEM
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(
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.Clock(Clock),
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.Reset(Reset),
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.iFlipMemory( w2MEM_FlipMemory ),
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//Data Bus to/from EXE
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.iDataReadAddress1_EXE( wEXE_2__MEM_DataReadAddress0 ),
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.iDataReadAddress2_EXE( wEXE_2__MEM_DataReadAddress1 ),
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.oData1_EXE( wMEM_2__EXE_DataRead0 ),
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.oData2_EXE( wMEM_2__EXE_DataRead1 ),
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.iDataWriteEnable_EXE( wEXE_2__DataWriteEnable ),
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.iDataWriteAddress_EXE( wEXE_2__MEM_wDataWriteAddress ),
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.iData_EXE( wEXE_2__MEM_WriteData ),
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//Data Bus to/from IO
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.iDataReadAddress1_IO( wIO_2_MEM__DataReadAddress0 ),
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.iDataReadAddress2_IO( wIO_2_MEM__DataReadAddress1 ),
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.oData1_IO( wMEM_2__IO_DataRead0 ),
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.oData2_IO( wMEM_2__IO_DataRead1 ),
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.iDataWriteEnable_IO( wIO2_MEM__DataWriteEnable ),
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.iDataWriteAddress_IO( wIO2_MEM__DataWriteAddress ),
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.iData_IO( wIO2_MEM__Bus ),
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`ifdef DEBUG
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.iDebug_CoreID( iDebug_CoreID ),
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`endif
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//Instruction Bus
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.iInstructionReadAddress1( wInstructionPointer1 ),
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.iInstructionReadAddress2( wInstructionPointer2 ),
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.oInstruction1( wEncodedInstruction1 ),
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.oInstruction2( wEncodedInstruction2 ),
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.iInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
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.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
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.iInstruction( wIO2_MEM__ExternalInstruction ),
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.iControlRegister( CREG_I ),
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.oControlRegister( wCR2_ControlRegister )
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);
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////--------------------------------------------------------
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ExecutionUnit EXE
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(
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.Clock( Clock),
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.Reset( Reset ),
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.iInitialCodeAddress( InitialCodeAddress ),
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.iInstruction1( wEncodedInstruction1 ),
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.iInstruction2( wEncodedInstruction2 ),
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.oInstructionPointer1( wInstructionPointer1 ),
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.oInstructionPointer2( wInstructionPointer2 ),
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.iDataRead0( wMEM_2__EXE_DataRead0 ),
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.iDataRead1( wMEM_2__EXE_DataRead1 ),
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.iTrigger( wCU2__ExecuteMicroCode ),
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.oDataReadAddress0( wEXE_2__MEM_DataReadAddress0 ),
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.oDataReadAddress1( wEXE_2__MEM_DataReadAddress1 ),
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.oDataWriteEnable( wEXE_2__DataWriteEnable ),
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.oDataWriteAddress( wEXE_2__MEM_wDataWriteAddress ),
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.oDataBus( wEXE_2__MEM_WriteData ),
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.oReturnCode( wIFU2__MicroCodeReturnValue ),
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/**************/
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.oOMEMWriteAddress( wEXE_2__IO_WriteAddress ),
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.oOMEMWriteData( wEXE_2__IO_WriteData ),
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320 |
|
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.oOMEMWriteEnable( wEXE_2__IO_OMEMWriteEnable ),
|
321 |
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|
322 |
|
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.oTMEMReadAddress( wEXE_2__IO_TMEMAddress ),
|
323 |
|
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.iTMEMReadData( wIO_2_EXE__TMEMData ),
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324 |
|
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.iTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
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325 |
|
|
.oTMEMDataRequest( wEXE_2_IO__DataRequest ),
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326 |
|
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/**************/
|
327 |
|
|
`ifdef DEBUG
|
328 |
|
|
.iDebug_CoreID( iDebug_CoreID ),
|
329 |
|
|
`endif
|
330 |
|
|
.oDone( wCU2__MicrocodeExecutionDone )
|
331 |
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|
332 |
|
|
);
|
333 |
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|
334 |
|
|
////--------------------------------------------------------
|
335 |
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|
336 |
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|
337 |
|
|
assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
|
338 |
|
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//---------------------------------------------------------------------------------------------------
|
339 |
|
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|
340 |
|
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//assign wEXE_2__MEM_DataReadAddress1 = (wCU2_IO__WritePixel == 0) ? wUCODE_RAMReadAddress1 : wIO_2_MEM__DataReadAddress1;
|
341 |
|
|
assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
|
342 |
|
|
assign w2IO__AddrIsImm = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm : 1'b0;
|
343 |
|
|
assign w2IO__AddressOffset = 0;//(wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset : 32'b0;
|
344 |
|
|
assign w2IO__Adr_O_Pointer = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_ADDR_O;
|
345 |
|
|
//assign w2IO__Adr_O_Pointer = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `CREG_PIXEL_2D_INITIAL_POSITION;
|
346 |
|
|
|
347 |
|
|
wire w2IO_MasterCycleType;
|
348 |
|
|
assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
IO_Unit IO
|
356 |
|
|
(
|
357 |
|
|
.Clock( Clock ),
|
358 |
|
|
.Reset( Reset ),
|
359 |
|
|
.iEnable( 1'b0 ),// w2IO__EnableWBMaster ),
|
360 |
|
|
.iBusCyc_Type( w2IO_MasterCycleType ),
|
361 |
|
|
|
362 |
|
|
.iStore( 1'b1),//w2IO__Store ),
|
363 |
|
|
.iAdr_DataWriteBack( w2IO__DataWriteAddress ),
|
364 |
|
|
.iAdr_O_Set( w2IO__SetAddress ),
|
365 |
|
|
.iAdr_O_Imm( w2IO__AddressOffset ),
|
366 |
|
|
.iAdr_O_Type( w2IO__AddrIsImm ),
|
367 |
|
|
.iAdr_O_Pointer( w2IO__Adr_O_Pointer ),
|
368 |
|
|
.iReadDataBus( wMEM_2__IO_DataRead0 ),
|
369 |
|
|
.iReadDataBus2( wMEM_2__IO_DataRead1 ),
|
370 |
|
|
.iDat_O_Pointer( `OREG_PIXEL_COLOR ),
|
371 |
|
|
|
372 |
|
|
|
373 |
|
|
.oDataReadAddress( wIO_2_MEM__DataReadAddress0 ),
|
374 |
|
|
.oDataReadAddress2( wIO_2_MEM__DataReadAddress1 ),
|
375 |
|
|
.oDataWriteAddress( wIO2_MEM__DataWriteAddress ),
|
376 |
|
|
.oDataBus( wIO2_MEM__Bus ),
|
377 |
|
|
.oInstructionBus( wIO2_MEM__ExternalInstruction ),
|
378 |
|
|
|
379 |
|
|
.oDataWriteEnable( wIO2_MEM__DataWriteEnable ),
|
380 |
|
|
.oData( wIO2_MEM__Data ),
|
381 |
|
|
.oInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
|
382 |
|
|
.oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
|
383 |
|
|
.iWriteBack_Set( w2IO_WriteBack_Set ),
|
384 |
|
|
.oBusy( wIO_Busy ),
|
385 |
|
|
.oDone( wIO2__Done ),
|
386 |
|
|
/**********/
|
387 |
|
|
.iOMEM_WriteAddress( wEXE_2__IO_WriteAddress ),
|
388 |
|
|
.iOMEM_WriteData( wEXE_2__IO_WriteData ),
|
389 |
|
|
.iOMEM_WriteEnable( wEXE_2__IO_OMEMWriteEnable ),
|
390 |
|
|
.OMEM_DAT_O( OMEM_DAT_O ),
|
391 |
|
|
.OMEM_ADR_O( OMEM_ADR_O ),
|
392 |
|
|
.OMEM_WE_O( OMEM_WE_O ),
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
.oTMEMReadData( wIO_2_EXE__TMEMData ),
|
396 |
|
|
.iTMEMDataRequest( wEXE_2_IO__DataRequest ),
|
397 |
|
|
.iTMEMReadAddress( wEXE_2__IO_TMEMAddress ),
|
398 |
|
|
.oTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
|
399 |
|
|
|
400 |
|
|
.TMEM_ACK_I( TMEM_ACK_I ),
|
401 |
|
|
.TMEM_DAT_I( TMEM_DAT_I ),
|
402 |
|
|
.TMEM_ADR_O( TMEM_ADR_O ),
|
403 |
|
|
.TMEM_WE_O( TMEM_WE_O ),
|
404 |
|
|
.TMEM_STB_O( TMEM_STB_O ),
|
405 |
|
|
.TMEM_CYC_O( TMEM_CYC_O ),
|
406 |
|
|
.TMEM_GNT_I( TMEM_GNT_I ),
|
407 |
|
|
|
408 |
|
|
/**********/
|
409 |
|
|
.MST_I( MST_I ),
|
410 |
|
|
//Wish Bone Interface
|
411 |
|
|
.DAT_I( DAT_I ),
|
412 |
|
|
.DAT_O( DAT_O ),
|
413 |
|
|
.ACK_I( ACK_I & GNT_I ),
|
414 |
|
|
.ACK_O( ACK_O ),
|
415 |
|
|
.ADR_O( ADR_O ),
|
416 |
|
|
.ADR_I( ADR_I ),
|
417 |
|
|
.WE_O( WE_O ),
|
418 |
|
|
.WE_I( WE_I ),
|
419 |
|
|
.STB_O( STB_O ),
|
420 |
|
|
.STB_I( STB_I ),
|
421 |
|
|
.CYC_O( CYC_O ),
|
422 |
|
|
.TGA_I( TGA_I ),
|
423 |
|
|
.CYC_I( CYC_I ),
|
424 |
|
|
.GNT_I( GNT_I ),
|
425 |
|
|
.TGC_O( TGC_O )
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
);
|
429 |
|
|
//---------------------------------------------------------------------------------------------------
|
430 |
|
|
endmodule
|