OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [trunk/] [test_bench/] [TestBench_THEIA.v] - Blame information for rev 100

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 13 diegovalve
 
2
/**********************************************************************************
3
Theia, Ray Cast Programable graphic Processing Unit.
4
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
5
 
6
This program is free software; you can redistribute it and/or
7
modify it under the terms of the GNU General Public License
8
as published by the Free Software Foundation; either version 2
9
of the License, or (at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19
 
20
***********************************************************************************/
21
 
22
 
23
/*******************************************************************************
24
Module Description:
25
 
26
This is the Main test bench of the GPU. It simulates the behavior of
27
an external control unit or CPU that sends configuration information into DUT.
28
It also implements a second processs that simulates a Wishbone slave that sends
29
data from an external memory. These blocks are just behavioral CTE and therefore
30
are not meant to be synthethized.
31
 
32
*******************************************************************************/
33 61 diegovalve
 
34
 
35 13 diegovalve
`timescale 1ns / 1ps
36
`include "aDefinitions.v"
37
`define CONFIGURATION_PHASE                                             0
38
`define CTE_INITIAL_STATE                                                       0
39
`define CTE_IDLE                                                                                1
40
`define CTE_START_EU_CONFIGURATION_SEQUENCE     2
41
`define CTE_SEND_CONFIGURATION_PACKET                   3
42
`define CTE_ACK_CONFIGURATION_PACKET                    8
43
`define CTE_SEND_LIGHT_PACKET                                           13
44
`define CTE_ACK_LIGTH_PACKET                                            14
45
`define CTE_SEND_RAY_I_TASK                                             15
46
`define CTE_WAIT_FOR_TASK_ACK                                           16
47
`define WAIT_FOR_TASK_COMPLETE                                  17
48
`define CTE_PREPARE_NEW_TASK                                            18
49
`define CTE_RENDER_DONE                                                         19
50
`define CTE_READ_COLOR_DATA                                             20
51
`define CTE_GRANT_BUS_WRITE_PERMISION                   21
52
`define CTE_ACK_GRANT_BUS_PERMISION                             22
53
`define CTE_ACK_READ_COLOR_DATA                                 23
54
`define CTE_SEND_TEXTURE_DIMENSIONS                             24
55
`define CTE_ACK_TEXTURE_DIMENSIONS                              25
56
 
57
 
58
 
59
 
60
`define RESOLUTION_WIDTH                                                        (rSceneParameters[12] >> `SCALE)
61
`define RESOLUTION_HEIGHT                                                       (rSceneParameters[13] >> `SCALE)
62
`define RAYI_TASK                                                                               1
63
`define DELTA_ROW                                                                       (32'h1 << `SCALE)
64
`define DELTA_COL                                                                       (32'h1 << `SCALE)
65 77 diegovalve
 
66 84 diegovalve
`define SELECT_ALL_CORES `MAX_CORES'b1111;
67 13 diegovalve
module TestBench_Theia;
68
 
69
 
70
        //------------------------------------------------------------------------
71
        //**WARNING: Declare all of your varaibles at the begining
72
        //of the file. I hve noticed that sometimes the verilog
73
        //simulator allows you to use some regs even if they have not been 
74
        //previously declared, leadeing to crahses or unexpected behavior
75
        // Inputs
76
        reg Clock;
77
        reg Reset;
78
        reg ExternalBus_DataReady;
79
 
80
        // Outputs
81
        wire ExternalBus_Acknowledge;
82
        wire TaskCompleted;
83
 
84
        //CTE state machin logic
85
 
86
        reg[31:0] CurrentState,NextState;
87
        reg[3:0]  LightCount;
88
        reg[31:0] rLaneA,rLaneB,rLaneC,rLaneD;
89
        reg[16:0] CurrentTaskId;
90
        reg[31:0] CurrentPixelRow, CurrentPixelCol,CurrentRayType;
91
 
92
        reg CTE_WriteEnable;
93
        wire [`WB_WIDTH-1:0] DAT_O;
94
 
95
        reg                                             ACK_O;
96
        wire                                            ACK_I;
97
        wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
98 77 diegovalve
        wire                                            WE_I,STB_I;
99 13 diegovalve
        reg CYC_O,WE_O,TGC_O,STB_O;
100
        wire [1:0] TGC_I;
101
        reg [1:0] TGA_O;
102
        wire [1:0] TGA_I;
103
        wire [31:0] DAT_I;
104
        integer ucode_file;
105
 
106
 
107
        reg [31:0] rInitialCol,rInitialRow;
108
        reg [31:0]       rControlRegister[2:0];
109
 
110
 
111
        integer file, log, r, a, b;
112
 
113
 
114 84 diegovalve
        reg [31:0]  rSceneParameters[64:0];
115 13 diegovalve
        reg [31:0]       rVertexBuffer[6000:0];
116 61 diegovalve
        reg [31:0]       rInstructionBuffer[512:0];
117 13 diegovalve
        `define TEXTURE_BUFFER_SIZE (256*256*3)
118 77 diegovalve
        reg [31:0]  rTextures[`TEXTURE_BUFFER_SIZE:0];            //Lets asume we use 256*256 textures
119
 
120
        integer i,j;
121
        `define MAX_WIDTH 200
122
        `define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
123
        reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
124 13 diegovalve
 
125
        //------------------------------------------------------------------------
126
        //Debug registers
127 69 diegovalve
        `define TASK_TIMEOUTMAX 150000//50000
128 13 diegovalve
 
129
 
130
 
131
        //------------------------------------------------------------------------
132
 
133
 
134
 
135
                reg MST_O;
136 77 diegovalve
//---------------------------------------------------------------       
137 84 diegovalve
reg rIncCoreSelect;
138
wire [`MAX_CORES-1:0] wCoreSelect;
139
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
140
(
141
        .Clock( Clock ),
142
        .Reset( Reset ),
143
        .Initial(`MAX_CORES'b1),
144
        .Enable(rIncCoreSelect),
145
        .O(wCoreSelect)
146
);
147 77 diegovalve
 
148 84 diegovalve
 
149 77 diegovalve
wire [3:0] CYC_I,GNT_O;
150
wire wDone;
151 84 diegovalve
reg [`MAX_CORES-1:0] rCoreSelectMask,rRenderEnable;
152 77 diegovalve
 
153
THEIA GPU
154 13 diegovalve
                (
155
                .CLK_I( Clock ),
156 77 diegovalve
                .RST_I( Reset ),
157
                .RENDREN_I( rRenderEnable ),
158 13 diegovalve
                .DAT_I( DAT_O ),
159
                .ADR_O( ADR_I ),
160
                .ACK_I( ACK_O ),
161
                .WE_O ( WE_I ),
162
                .STB_O( STB_I ),
163 77 diegovalve
 
164 13 diegovalve
                .CYC_I( CYC_O ),
165
                .TGC_O( TGC_I ),
166
                .MST_I( MST_O ),
167
                .TGA_I( TGA_O ),
168
                .ACK_O( ACK_I ),
169
                .ADR_I( ADR_O ),
170
                .DAT_O( DAT_I ),
171 77 diegovalve
                .WE_I(  WE_O  ),
172 84 diegovalve
                .SEL_I( wCoreSelect | rCoreSelectMask),//4'b0001 ),
173 13 diegovalve
                .STB_I( STB_O ),
174
                .TGA_O(TGA_I),
175
 
176
                //Control register
177 77 diegovalve
                .CREG_I( rControlRegister[0][15:0] ),
178
                //Other stuff
179
                .DONE_O( wDone )
180 13 diegovalve
 
181
        );
182 77 diegovalve
 
183
 
184
 
185
 
186 13 diegovalve
        //---------------------------------------------
187
        //generate the clock signal here
188
        always begin
189 61 diegovalve
                #`CLOCK_CYCLE  Clock =  ! Clock;
190 13 diegovalve
 
191
        end
192
        //---------------------------------------------
193
 
194
reg [15:0] rTimeOut;
195
 
196
                `define MAX_INSTRUCTIONS 2
197
 
198
        initial begin
199
                // Initialize Inputs
200
 
201
 
202
                Clock                                   = 0;
203
                Reset                                   = 0;
204
                CTE_WriteEnable                 = 0;
205
                rLaneA                                  = 32'b0;
206
                rLaneB                                  = 32'b0;
207
                rLaneC                                  = 32'b0;
208
                rLaneD                                  = 32'b0;
209
                ExternalBus_DataReady = 0;
210
                rTimeOut              = 0;
211 77 diegovalve
 
212
 
213
 
214 13 diegovalve
        `ifdef DUMP_CODE
215 69 diegovalve
                $write("Opening TestBench.log.... ");
216 13 diegovalve
                ucode_file = $fopen("TestBench.log","w");
217 69 diegovalve
                $display("Done");
218 13 diegovalve
        `endif
219
 
220
                //Read Config register values
221 69 diegovalve
                $write("Loading control register.... ");
222 13 diegovalve
                $readmemh("Creg.mem",rControlRegister);
223 69 diegovalve
                $display("Done");
224 13 diegovalve
 
225
 
226 69 diegovalve
 
227 13 diegovalve
                //Read configuration Data
228 69 diegovalve
                $write("Loading scene parameters.... ");
229 13 diegovalve
                $readmemh("Params.mem", rSceneParameters        );
230 69 diegovalve
                $display("Done");
231
 
232
                rInitialRow = rSceneParameters[18];
233
                rInitialCol = rSceneParameters[19];
234
 
235 13 diegovalve
                //Read Scene Data
236 69 diegovalve
                $write("Loading scene geometry.... ");
237 13 diegovalve
                $readmemh("Vertex.mem",rVertexBuffer);
238 69 diegovalve
                $display("Done");
239
 
240 13 diegovalve
                //Read Texture Data
241 69 diegovalve
                $write("Loading scene texture.... ");
242 13 diegovalve
                $readmemh("Textures.mem",rTextures);
243 69 diegovalve
                $display("Done");
244
 
245
 
246 13 diegovalve
                //Read instruction data
247 69 diegovalve
                $write("Loading code allocation table and user shaders.... ");
248 13 diegovalve
                $readmemh("Instructions.mem",rInstructionBuffer);
249 69 diegovalve
                $display("Done");
250 13 diegovalve
 
251 69 diegovalve
                $display("Control Register : %b",rControlRegister[0]);
252
                $display("Initial Row      : %h",rInitialRow);
253
                $display("Initial Column   : %h",rInitialCol);
254
                $display("Resolution       : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
255
 
256 13 diegovalve
                //Open output file
257
                file = $fopen("Output.ppm");
258
                log  = $fopen("Simulation.log");
259
                $fwrite(log, "Simulation start time : %dns\n",$time);
260
                $fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
261
                $fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
262
 
263
                $fwrite(file,"P3\n");
264
                $fwrite(file,"#This file was generated by Theia's RTL simulation\n");
265
                $fwrite(file,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
266
                $fwrite(file,"255\n");
267
 
268
                CurrentPixelRow = 0;
269
                CurrentPixelCol = 0;
270
                #10
271
                Reset = 1;
272
                ExternalBus_DataReady = 0;
273
 
274
                // Wait 100 ns for global reset to finish
275
                #100  Reset = 0;
276
 
277
        end
278
 
279
        reg [5:0] DataIndex;
280
        reg [31:0] ConfigurationPacketSize;
281
 
282
        reg [7:0] R,G,B;
283
 
284
 
285
//---------------------------------------------
286
 
287
always @ (posedge Clock)
288
begin
289
        rTimeOut = rTimeOut+1'b1;
290
        if (rTimeOut > `TASK_TIMEOUTMAX)
291
        begin
292
                 $display("%dns ERROR: THEIA Timed out after %d of inactivity\n",
293
                 $time(),rTimeOut);
294
                 $stop();
295
        end
296
end
297
 
298
reg [31:0] rSlaveData_O;
299
//reg [31:0] rOutputFrameBuffer[39000:0];
300
reg [31:0] rColor;
301
 
302
reg [7:0] Thingy;
303
//Wish-Bone Slave logic.
304
//
305
//This logic represents a WBS FSM. It will provide
306
//the memory for Vertex and Texture data.
307
//Vertex/Tetxure data is stored in a 4GB RAM.
308
//Vertex data starts at address 0 and ends at address 0x80_000_000.
309
//Texture data starts at address 0x80_000_000 and ends at address
310
//0xFFFFFFFF.
311
//The Bit 31, indcates wheather we look for vertex (b=0)
312
//or texture (b=1)
313
 
314
`define WBS_AFTER_RESET                                 0
315
`define WBS_MOINTOR_STB_I                               1
316
`define WBS_ACK_O                                                       2
317
`define WBS_MOINTOR_STB_I_NEG                   3
318
`define WBS_DONE                    4
319
 
320
        reg [7:0]                        WBSCurrentState,WBSNextState;
321
        reg [31:0]                       rAddress;
322
 
323
        always @(negedge Clock)
324
        begin
325
        if( Reset!=1 )
326
           WBSCurrentState = WBSNextState;
327
                  else
328
                          WBSCurrentState = `WBS_AFTER_RESET;
329
        end
330
 
331
 
332
 
333
        reg [31:0] rConvertedTextureAddress;
334
        //----------------------------------------------------------    
335
        always @(posedge Clock)
336
        begin
337
                case (WBSCurrentState)
338
                //----------------------------------------
339
                `WBS_AFTER_RESET:
340
                begin
341
                        ACK_O = 0;
342
                        rSlaveData_O = 32'b0;
343
 
344
                        WBSNextState = `WBS_MOINTOR_STB_I;
345
                end
346
                //----------------------------------------
347
                `WBS_MOINTOR_STB_I:
348
                begin
349 77 diegovalve
                                if ( STB_I == 1 && wDone == 0)
350
                                WBSNextState = `WBS_ACK_O;
351
                        else if (STB_I == 0 && wDone == 0)
352
                                WBSNextState = `WBS_MOINTOR_STB_I;
353 13 diegovalve
                        else
354 77 diegovalve
                                WBSNextState = `WBS_DONE;
355 13 diegovalve
                end
356
                //----------------------------------------
357
                `WBS_ACK_O:
358
                begin
359
                        if (WE_I == 0)
360
                        begin
361
 
362
                                rAddress = ADR_I;
363
                                if (TGA_I == 2'b01) //replace this by TGA_I
364
                                begin
365
                                 //Multiply pithc (3), Add 2 because the first 2 bytes are text Width, Height
366
                                rConvertedTextureAddress = {1'b0,rAddress[30:0]} + 2;
367
                                if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)
368
                                        rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;
369
 
370
 
371
                                        rSlaveData_O = rTextures[  rConvertedTextureAddress ];
372 84 diegovalve
                                        `ifdef DEBUG_WBM
373 13 diegovalve
 
374
                                        `LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
375
                                        `endif
376
                                end
377
                                else
378
                                begin
379 77 diegovalve
                        //              Thingy = 0;  //THIS IS NOT RE-ENTRANT!!!
380 13 diegovalve
                                        rSlaveData_O = rVertexBuffer[ rAddress ];
381 84 diegovalve
                                        `ifdef DEBUG_WBM
382 13 diegovalve
                                        `LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
383
                                        `endif
384
                                end
385
 
386
                        end
387
                        else
388
                        begin
389 77 diegovalve
                        //      $display("%d Theia Writes value: %h @ %d (Time to process pixel %d Clock cycle)",$time, DAT_I,ADR_I,rTimeOut);
390 13 diegovalve
 
391
 
392 77 diegovalve
                //      if (Thingy == 0)
393
                //      begin
394
 
395
                //      end     
396 13 diegovalve
 
397 77 diegovalve
                //      Thingy = Thingy + 1;
398
                        if (CurrentPixelCol >=  (`RESOLUTION_WIDTH*3))
399 13 diegovalve
                        begin
400 77 diegovalve
                                CurrentPixelCol = 0;
401
                                CurrentPixelRow = CurrentPixelRow + 1;
402
                                $display("]- %d (%d)",CurrentPixelRow,ADR_I);
403 13 diegovalve
                                $write("[");
404
                        end
405
 
406 77 diegovalve
                //      if (Thingy == 3)
407
                //      begin
408
                                CurrentPixelCol = CurrentPixelCol + 1;
409
                                if ( CurrentPixelCol % 3  == 0)
410
                                begin
411
                        //      $fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);
412
                                $write(".");
413
                                end
414
                                //Thingy = 0;
415
                //      end     
416 13 diegovalve
                                rTimeOut = 0;
417 77 diegovalve
                                R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >>  (`SCALE-8));
418
                                rScreen[ ADR_I ] = R;
419
                        //      $fwrite(file,"%d " , R );
420 13 diegovalve
 
421
                        end
422
 
423
 
424
                        ACK_O = 1;
425 61 diegovalve
 
426 77 diegovalve
                //      if (CurrentPixelRow >= `RESOLUTION_HEIGHT)
427
                if (wDone)
428 13 diegovalve
                                WBSNextState = `WBS_DONE;
429
                        else
430
                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;
431
                end
432
                //----------------------------------------
433
                `WBS_MOINTOR_STB_I_NEG:
434
                begin
435
                        if ( STB_I == 0 )
436
                        begin
437
                                ACK_O = 0;
438
                                WBSNextState = `WBS_MOINTOR_STB_I;
439
                        end
440
                        else
441
                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;
442
                end
443
                //----------------------------------------
444 77 diegovalve
                `WBS_DONE:
445
                begin
446
                for (j = 0; j < `RESOLUTION_WIDTH; j = j+1)
447
                begin
448
 
449
                        for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
450
                        begin
451
 
452
                        $fwrite(file,"%d " , rScreen[i+j*`RESOLUTION_WIDTH*3] );
453
                                if ((i %3) == 0)
454
                                                $fwrite(file,"\n# %d %d\n",i,j);
455
 
456
                        end
457
                end
458 13 diegovalve
                $display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",
459
                `RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);
460
                $display("ADR_I = %d\n",ADR_I);
461
                        `LOGME"RENDER COMPLETE");
462
                        `LOGME"Closing File");
463
                        $fclose(file);
464
                        $fwrite(log, "Simulation end time : %dns\n",$time);
465
                        $fclose(log);
466
                        `LOGME"File Closed");
467
                        $stop();
468
                        $fclose(ucode_file);
469
                end
470
                //----------------------------------------
471
                default:
472
                begin
473 61 diegovalve
                $display("WBS Undefined state");
474 13 diegovalve
                end
475
                endcase
476
        end     //end always
477
        //----------------------------------------------------------    
478
 
479
 
480
 
481
 
482
`define TAG_BLOCK_WRITE_CYCLE    2'b01
483
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
484
`define TAG_DATA_ADDRESS_TYPE        2'b10
485
 
486
`define WBM_AFTER_RESET                                                 0
487
`define WBM_WRITE_INSTRUCTION_PHASE1            1
488
`define WBM_ACK_INSTRUCTION_PHASE1                      2
489
`define WBM_WRITE_INSTRUCTION_PHASE2            3
490
`define WBM_ACK_INSTRUCTION_PHASE2                      4
491
`define WBM_END_INSTRUCTION_WRITE_CYCLE   5
492
`define WBM_SEND_DATA_PHASE1                          6
493
`define WBM_ACK_DATA_PHASE1                           7
494
`define WBM_SEND_DATA_PHASE2                          8
495
`define WBM_ACK_DATA_PHASE2                           9
496
`define WBM_SEND_DATA_PHASE3                          10
497
`define WBM_ACK_DATA_PHASE3                           11
498
`define WBM_END_DATA_WRITE_CYCLE          12
499 77 diegovalve
`define WBM_DONE                          13
500
`define WBM_CONFIGURE_CORE0_PHASE1        14
501
`define WBM_ACK_CONFIGURE_CORE0_PHASE1    15
502
`define WBM_CONFIGURE_CORE0_PHASE2        16
503
`define WBM_ACK_CONFIGURE_CORE0_PHASE2    17
504
`define WBM_CONFIGURE_CORE0_PHASE3        18
505
`define WBM_ACK_CONFIGURE_CORE0_PHASE3    19
506
`define WBM_CONFIGURE_CORE1_PHASE1        20
507
`define WBM_ACK_CONFIGURE_CORE1_PHASE1    21
508
`define WBM_CONFIGURE_CORE1_PHASE2        22
509
`define WBM_ACK_CONFIGURE_CORE1_PHASE2    23
510
`define WBM_CONFIGURE_CORE1_PHASE3        24
511
`define WBM_ACK_CONFIGURE_CORE1_PHASE3    25
512
`define WBM_END_CORE0_WRITE_CYCLE         26
513
`define WBM_END_CORE1_WRITE_CYCLE         27
514 84 diegovalve
 
515
`define WBM_CONFIGURE_CORE2_PHASE1        28
516
`define WBM_ACK_CONFIGURE_CORE2_PHASE1    29
517
`define WBM_CONFIGURE_CORE2_PHASE2        30
518
`define WBM_ACK_CONFIGURE_CORE2_PHASE2    31
519
`define WBM_CONFIGURE_CORE2_PHASE3        32
520
`define WBM_ACK_CONFIGURE_CORE2_PHASE3    33
521
`define WBM_CONFIGURE_CORE3_PHASE1        34
522
`define WBM_ACK_CONFIGURE_CORE3_PHASE1    35
523
`define WBM_CONFIGURE_CORE3_PHASE2        36
524
`define WBM_ACK_CONFIGURE_CORE3_PHASE2    37
525
`define WBM_CONFIGURE_CORE3_PHASE3        38
526
`define WBM_ACK_CONFIGURE_CORE3_PHASE3    39
527
`define WBM_END_CORE2_WRITE_CYCLE         40
528
`define WBM_END_CORE3_WRITE_CYCLE         41
529
`define WBM_CONFIGURE_NEXT_CORE           42
530 13 diegovalve
 
531 77 diegovalve
 
532 13 diegovalve
reg[31:0] rInstructionPointer;
533
reg[31:0] rAddressToSend;
534
reg[31:0] rDataAddress;
535
reg[31:0] rDataPointer;
536
 
537 77 diegovalve
reg IncIP,IncIA,IncDP;
538
reg rPrepateWriteAddressForNextCore;
539 13 diegovalve
reg rClearOutAddress;
540
//-----------------------------------------------------
541
always @ (posedge Clock or posedge rClearOutAddress)
542
begin
543
 
544
        if ( IncIA && ~rClearOutAddress)
545
                rAddressToSend = rAddressToSend + 1;
546
        else if (rClearOutAddress)
547
        begin
548
                if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
549
                        rAddressToSend =  {16'd1,16'd0};
550 77 diegovalve
                else if (rPrepateWriteAddressForNextCore)
551
                        rAddressToSend = `CREG_PIXEL_2D_INITIAL_POSITION;
552 13 diegovalve
                else
553
                        rAddressToSend = 0;
554
        end
555
 
556
 
557
end
558
//-----------------------------------------------------
559
always @ (posedge ACK_I or posedge Reset )
560
begin
561
 
562
        if ( ACK_I && ~Reset)
563
                rInstructionPointer = rInstructionPointer + 1;
564
        else if (Reset)
565
                rInstructionPointer = 0;
566
 
567
 
568
 
569
end
570
//-----------------------------------------------------
571
reg rResetDp;
572
 
573
always @ (posedge Clock or posedge rResetDp )
574
begin
575
 
576
        if ( ACK_I && ~rResetDp)//IncDP && ~Reset)
577
                rDataPointer = rDataPointer + 1;
578
        else if (rResetDp)
579
                rDataPointer =  32'b0;
580
 
581
 
582 84 diegovalve
end
583
 
584
reg rIncPacketCount;
585
reg [`WIDTH-1:0] rPacketCount;
586
 
587
always @ (posedge Clock)
588
begin
589
        if (Reset)
590
                rPacketCount = 0;
591
        else
592
        begin
593
                if ( rIncPacketCount )
594
                        rPacketCount = rPacketCount + 1;
595
        end
596 13 diegovalve
end
597
//-----------------------------------------------------
598
 
599
 
600
 
601
 
602
assign DAT_O = ( MST_O == 1'b1 ) ? wMasteData_O : rSlaveData_O;
603
 
604
wire[31:0] wMasteData_O;
605
 
606 61 diegovalve
 
607
 
608
assign wMasteData_O = (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE) ? rInstructionBuffer[rInstructionPointer+1] : rSceneParameters[ rDataPointer  ];
609
 
610
 
611
always @ (posedge STB_O)
612
begin
613
        if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
614
        begin
615 69 diegovalve
                //$display("-- %x\n",wMasteData_O);
616 61 diegovalve
        end
617
end
618 13 diegovalve
assign ADR_O = rAddressToSend;
619
 
620
        reg [7:0]                        WBMCurrentState,WBMNextState;
621
        reg [31:0]                       rWriteAddress;
622
 
623
        always @(posedge Clock or posedge Reset)
624
        begin
625
        if( Reset!=1 )
626
           WBMCurrentState = WBMNextState;
627
                  else
628
                          WBMCurrentState = `WBM_AFTER_RESET;
629
        end
630
 
631
                wire[31:0] wConfigurationPacketSize;
632
                assign wConfigurationPacketSize = rSceneParameters[2];
633
 
634
   reg [31:0]  InstructionIndex;
635
        reg [31:0]  InstructionWriteAddress;
636
        //Send the instructions now...
637
        //----------------------------------------------------------    
638
        always @(posedge Clock)
639
        begin
640
                case (WBMCurrentState)
641
                //----------------------------------------
642 61 diegovalve
 
643
                //Wait until the reset secuence is complete to
644
                //begin sending stuff.
645
 
646 13 diegovalve
                `WBM_AFTER_RESET:
647
                begin
648
                        WE_O <=  0;
649
                        CYC_O <= 0;
650
                        TGC_O <= 0;
651
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
652
                        STB_O <= 0;
653
                //      IncIP <= 0;
654
                        IncIA <= 0;
655
                        MST_O   <= 0;
656
                        IncDP <= 0;
657
                        rResetDp <= 1;
658 77 diegovalve
                        rClearOutAddress <= 1;
659 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
660 77 diegovalve
                        rRenderEnable <= 0;
661 84 diegovalve
                        rPrepateWriteAddressForNextCore <= 0;
662
                        rIncPacketCount <= 0;
663 13 diegovalve
 
664
                        if (Reset == 0)
665
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
666
                        else
667
                                WBMNextState <= `WBM_AFTER_RESET;
668
                end
669
                //----------------------------------------
670 61 diegovalve
 
671
                //CLOCK EDGE 0: MASTER presents a valid address on [ADR_O()]
672
                //MASTER presents valid data on [DAT_O()]
673
                //MASTER asserts [WE_O] to indicate a WRITE cycle.
674
                //MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the cycle.
675
                //MASTER asserts [STB_O] to indicate the start of the phase.
676
 
677 13 diegovalve
                `WBM_WRITE_INSTRUCTION_PHASE1:
678
                begin
679
                        WE_O <=  1;                                                                                                     //Indicate write cycle
680
                        CYC_O <= 1;                                                                                                     //Start of the cycle
681
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
682
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;                 //TAG Address: 01 means instruction address type.
683
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
684
                //      IncIP <= 0;
685
                        IncIA <= 0;
686
                        MST_O   <= 1;
687
                        IncDP <= 0;
688
                        rResetDp <= 1;
689
                        rClearOutAddress <= 0;
690 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
691 77 diegovalve
                        rRenderEnable <= 0;
692
                        rPrepateWriteAddressForNextCore <= 0;
693 84 diegovalve
                                                rIncPacketCount <= 0;
694 13 diegovalve
 
695
                        if ( ACK_I )
696
                                WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
697
                        else
698
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
699
 
700
                end
701
                //----------------------------------------
702
                `WBM_ACK_INSTRUCTION_PHASE1:
703
                begin
704
                        WE_O <=  1;
705
                        CYC_O <= 1;
706
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
707
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
708
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
709
                //      IncIP <= 1;     //*                                                                                     //Increment local inst pointer to send the next 32 bits                                 
710
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
711
                        MST_O   <= 1;
712
                        IncDP <= 0;
713
                        rResetDp <= 1;
714
                        rClearOutAddress <= 0;
715 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
716 77 diegovalve
                        rRenderEnable <= 0;
717
                        rPrepateWriteAddressForNextCore <= 0;
718 84 diegovalve
                                                rIncPacketCount <= 0;
719
 
720 13 diegovalve
                        if (ACK_I == 0)
721
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
722
                        else
723
                                WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
724
                end
725
                //----------------------------------------
726
                `WBM_WRITE_INSTRUCTION_PHASE2:
727
                begin
728
                        WE_O <=  1;
729
                        CYC_O <= 1;
730
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
731
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
732
                        STB_O <= ~ACK_I;
733
                //      IncIP <= 0;
734
                        IncIA <= 0;
735
                        MST_O   <= 1;
736
                        IncDP <= 0;
737
                        rResetDp <= 1;
738
                        rClearOutAddress <= 0;
739 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
740 77 diegovalve
                        rRenderEnable <= 0;
741
                        rPrepateWriteAddressForNextCore <= 0;
742 84 diegovalve
                        rIncPacketCount <= 0;
743 13 diegovalve
 
744
                        if ( ACK_I )
745
                                WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
746
                        else
747
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
748
 
749
                end
750
                //----------------------------------------
751
                `WBM_ACK_INSTRUCTION_PHASE2:
752
                begin
753
                        WE_O <=  1;
754
                        CYC_O <= 0;
755
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
756
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
757
                        STB_O <= 0;      //*
758
 
759
                        MST_O   <= 1;
760
                        IncDP <= 0;
761
                        rResetDp <= 1;
762 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
763 77 diegovalve
                        rRenderEnable <= 0;
764 84 diegovalve
                        rPrepateWriteAddressForNextCore <= 0;
765
                        rIncPacketCount <= 0;
766 13 diegovalve
 
767 84 diegovalve
 
768 61 diegovalve
                if (rInstructionPointer >= rInstructionBuffer[0])
769 13 diegovalve
                begin
770
                                IncIA <= 0;//*   
771
                                rClearOutAddress <= 1;
772
                                WBMNextState    <= `WBM_SEND_DATA_PHASE1;
773
                end
774
                else
775
                begin
776
                                IncIA <= 1;//*  
777
                                rClearOutAddress <= 0;
778
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
779
                end
780
 
781
                end
782
        //****************************************
783
        `WBM_SEND_DATA_PHASE1:
784
                begin
785
                        WE_O <=  1;                                                                                                     //Indicate write cycle
786
                        CYC_O <= 1;                                                                                                     //Start of the cycle
787
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
788
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;                //TAG Address: 01 means instruction address type.
789
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
790
                        IncIA <= 0;
791
                        MST_O   <= 1;
792
                        IncDP <= 0;
793
                        rResetDp <= 0;
794
                        rClearOutAddress <= 0;
795 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
796 77 diegovalve
                        rRenderEnable <= 0;
797 84 diegovalve
                        rPrepateWriteAddressForNextCore <= 0;
798
                        rIncPacketCount <= 0;
799 13 diegovalve
 
800 84 diegovalve
 
801 13 diegovalve
                        if ( ACK_I )
802
                                WBMNextState <= `WBM_ACK_DATA_PHASE1;
803
                        else
804
                                WBMNextState <= `WBM_SEND_DATA_PHASE1;
805
 
806
                end
807
                //----------------------------------------
808
                `WBM_ACK_DATA_PHASE1:
809
                begin
810
                        WE_O <=  1;
811
                        CYC_O <= 1;
812
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
813
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
814
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
815
                //      IncIP <= 1;     //*                                                                                     //Increment local inst pointer to send the next 32 bits                                 
816
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
817
                        MST_O   <= 1;
818
                        IncDP <= 0;
819
                        rResetDp <= 0;
820
                        rClearOutAddress <= 0;
821 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
822 77 diegovalve
                        rRenderEnable <= 0;
823
                        rPrepateWriteAddressForNextCore <= 0;
824 84 diegovalve
                                                rIncPacketCount <= 0;
825
 
826
 
827 13 diegovalve
 
828
                        if (ACK_I == 0)
829
                                WBMNextState <= `WBM_SEND_DATA_PHASE2;
830
                        else
831
                                WBMNextState <= `WBM_ACK_DATA_PHASE1;
832
                end
833
                //----------------------------------------
834
                `WBM_SEND_DATA_PHASE2:
835
                begin
836
                        WE_O <=  1;
837
                        CYC_O <= 1;
838
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
839
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
840
                        STB_O <= ~ACK_I;
841
                //      IncIP <= 0;
842
                        IncIA <= 0;
843
                        MST_O   <= 1;
844
                        IncDP <= 0;
845
                        rResetDp <= 0;
846
                        rClearOutAddress <= 0;
847 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
848 77 diegovalve
                        rRenderEnable <= 0;
849
                        rPrepateWriteAddressForNextCore <= 0;
850 84 diegovalve
                                                rIncPacketCount <= 0;
851
 
852 13 diegovalve
 
853
                        if ( ACK_I )
854
                                WBMNextState <= `WBM_ACK_DATA_PHASE2;
855
                        else
856
                                WBMNextState <= `WBM_SEND_DATA_PHASE2;
857
 
858
                end
859
                //----------------------------------------
860
                `WBM_ACK_DATA_PHASE2:
861
                begin
862
                        WE_O <=  1;
863
                        CYC_O <= 1;
864
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
865
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
866
                        STB_O <= 0;      //*
867
                        IncIA <= 0;
868
                        MST_O   <= 1;
869
                        IncDP <= 0;//*           
870
                        rResetDp <= 0;
871
                        rClearOutAddress <= 0;
872 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
873 77 diegovalve
                        rRenderEnable <= 0;
874
                        rPrepateWriteAddressForNextCore <= 0;
875 84 diegovalve
                                                rIncPacketCount <= 0;
876
 
877
 
878 77 diegovalve
 
879 13 diegovalve
                        if (ACK_I == 0)
880
                                WBMNextState <= `WBM_SEND_DATA_PHASE3;
881
                        else
882
                                WBMNextState <= `WBM_ACK_DATA_PHASE2;
883
 
884
                end
885
                //----------------------------------------
886
                `WBM_SEND_DATA_PHASE3:
887
                begin
888
                        WE_O <=  1;
889
                        CYC_O <= 1;
890
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
891
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
892
                        STB_O <= ~ACK_I;
893
                //      IncIP <= 0;
894
                        IncIA <= 0;
895
                        MST_O   <= 1;
896
                        IncDP <= 0;
897
                        rResetDp <= 0;
898
                        rClearOutAddress <= 0;
899 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
900 77 diegovalve
                        rRenderEnable <= 0;
901
                        rPrepateWriteAddressForNextCore <= 0;
902 84 diegovalve
                                                rIncPacketCount <= 0;
903
 
904
 
905 13 diegovalve
 
906
                        if ( ACK_I )
907
                                WBMNextState <= `WBM_ACK_DATA_PHASE3;
908
                        else
909
                                WBMNextState <= `WBM_SEND_DATA_PHASE3;
910
 
911
                end
912
                //----------------------------------------
913
                `WBM_ACK_DATA_PHASE3:
914
                begin
915
                        WE_O <=  1;
916
                        CYC_O <= 1;
917
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
918
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
919
                        STB_O <= 0;      //*
920
                        IncIA <= 0;
921
                        MST_O   <= 1;
922
                        IncDP <= 1;//*          
923
                        rResetDp <= 0;
924
                        rClearOutAddress <= 0;
925 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
926 77 diegovalve
                        rRenderEnable <= 0;
927
                        rPrepateWriteAddressForNextCore <= 0;
928 84 diegovalve
                                                rIncPacketCount <= 0;
929
 
930
 
931 77 diegovalve
 
932 13 diegovalve
                        WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
933
 
934
                end
935
                //----------------------------------------
936
                `WBM_END_DATA_WRITE_CYCLE:
937
                begin
938
                        WE_O <=  0;
939
                        CYC_O <= 0;      //*                                                                                             
940
                        TGC_O <= 0;
941
                        TGA_O <= 0;
942
                        STB_O <= 0;
943
                        IncIA <= 1;//*          
944
                        MST_O   <= 1;
945
                        IncDP <= 0;
946
                        rResetDp <= 0;
947
                        rClearOutAddress <= 0;
948 84 diegovalve
                        rCoreSelectMask <= `SELECT_ALL_CORES;
949 77 diegovalve
                        rRenderEnable <= 0;
950
                        rPrepateWriteAddressForNextCore <= 0;
951 84 diegovalve
                                                rIncPacketCount <= 0;
952
 
953
 
954 77 diegovalve
 
955
                        if (rDataPointer > 3*5)//wConfigurationPacketSize*3)
956
                                WBMNextState    <= `WBM_CONFIGURE_CORE0_PHASE1;
957 13 diegovalve
                        else
958
                                WBMNextState <= `WBM_SEND_DATA_PHASE1;
959
 
960 77 diegovalve
                end
961
                //----------------------------------------
962
                `WBM_CONFIGURE_CORE0_PHASE1:
963
                begin
964
 
965
                        WE_O <=  1;                                                                                                     //Indicate write cycle
966
                        CYC_O <= 1;                                                                                                     //Start of the cycle
967
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
968
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;                                        //TAG Address: 01 means instruction address type.
969
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
970
                        IncIA <= 0;
971
                        MST_O   <= 1;
972
                        IncDP <= 0;
973
                        rResetDp <= 0;
974 84 diegovalve
                        rClearOutAddress <= 0;
975
 
976
                        rIncCoreSelect <= 0;
977
                        rCoreSelectMask <= 0;
978 77 diegovalve
                        rRenderEnable <= 0;
979 84 diegovalve
                        rPrepateWriteAddressForNextCore <= 0;
980
                        rIncPacketCount <= 0;
981 77 diegovalve
 
982 84 diegovalve
 
983 77 diegovalve
                        if ( ACK_I )
984
                                WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
985
                        else
986
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
987 13 diegovalve
                end
988 77 diegovalve
                //----------------------------------------
989
                `WBM_ACK_CONFIGURE_CORE0_PHASE1:
990
                begin
991
                        WE_O <=  1;
992
                        CYC_O <= 1;
993
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
994
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
995
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
996
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
997
                        MST_O   <= 1;
998
                        IncDP <= 0;
999
                        rResetDp <= 0;
1000 84 diegovalve
                        rClearOutAddress <= 0;
1001
                        rIncCoreSelect <= 0;
1002
                        rCoreSelectMask <= 0;
1003 77 diegovalve
                        rRenderEnable <= 0;
1004
                        rPrepateWriteAddressForNextCore <= 0;
1005 84 diegovalve
                                                rIncPacketCount <= 0;
1006
 
1007 77 diegovalve
 
1008
                        if (ACK_I == 0)
1009
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
1010
                        else
1011
                                WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
1012
                end
1013
        //----------------------------------------
1014
                `WBM_CONFIGURE_CORE0_PHASE2:
1015
                begin
1016
                        WE_O <=  1;                                                                                                     //Indicate write cycle
1017
                        CYC_O <= 1;                                                                                                     //Start of the cycle
1018
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
1019
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;                                        //TAG Address: 01 means instruction address type.
1020
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
1021
                        IncIA <= 0;
1022
                        MST_O   <= 1;
1023
                        IncDP <= 0;
1024
                        rResetDp <= 0;
1025 84 diegovalve
                        rClearOutAddress <= 0;
1026
 
1027
                        rIncCoreSelect <= 0;
1028
                        rCoreSelectMask <= 0;
1029 77 diegovalve
                        rRenderEnable <= 0;
1030
                        rPrepateWriteAddressForNextCore <= 0;
1031 84 diegovalve
                                                rIncPacketCount <= 0;
1032 77 diegovalve
 
1033
                        if ( ACK_I )
1034
                                WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
1035
                        else
1036
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
1037
                end
1038
                //----------------------------------------
1039
                `WBM_ACK_CONFIGURE_CORE0_PHASE2:
1040
                begin
1041
                        WE_O <=  1;
1042
                        CYC_O <= 1;
1043
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
1044
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
1045
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
1046
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
1047
                        MST_O   <= 1;
1048
                        IncDP <= 0;
1049
                        rResetDp <= 0;
1050 84 diegovalve
                        rClearOutAddress <= 0;
1051
 
1052
                        rIncCoreSelect <= 0;
1053
                        rCoreSelectMask <= 0;
1054 77 diegovalve
                        rRenderEnable <= 0;
1055
                        rPrepateWriteAddressForNextCore <= 0;
1056 84 diegovalve
                                                rIncPacketCount <= 0;
1057 77 diegovalve
 
1058
                        if (ACK_I == 0)
1059
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
1060
                        else
1061
                                WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
1062
                end
1063
//----------------------------------------
1064
                `WBM_CONFIGURE_CORE0_PHASE3:
1065
                begin
1066
                        WE_O <=  1;                                                                                                     //Indicate write cycle
1067
                        CYC_O <= 1;                                                                                                     //Start of the cycle
1068
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
1069
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;                                        //TAG Address: 01 means instruction address type.
1070
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
1071
                        IncIA <= 0;
1072
                        MST_O   <= 1;
1073
                        IncDP <= 0;
1074
                        rResetDp <= 0;
1075 84 diegovalve
                        rClearOutAddress <= 0;
1076
                                                rIncPacketCount <= 0;
1077
 
1078
 
1079
                        rIncCoreSelect <= 0;
1080
                        rCoreSelectMask <= 0;
1081 77 diegovalve
                        rRenderEnable <= 0;
1082
                        rPrepateWriteAddressForNextCore <= 0;
1083
 
1084
                        if ( ACK_I )
1085
                                WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
1086
                        else
1087
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
1088
                end
1089
                //----------------------------------------
1090
                `WBM_ACK_CONFIGURE_CORE0_PHASE3:
1091
                begin
1092
                        WE_O <=  1;
1093
                        CYC_O <= 1;
1094
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
1095
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
1096
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
1097
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
1098
                        MST_O   <= 1;
1099
                        IncDP <= 0;
1100
                        rResetDp <= 0;
1101 84 diegovalve
                        rClearOutAddress <= 0;
1102
 
1103
                        rIncCoreSelect <= 0;
1104
                        rCoreSelectMask <= 0;
1105 77 diegovalve
                        rRenderEnable <= 0;
1106
                        rPrepateWriteAddressForNextCore <= 0;
1107 84 diegovalve
                                                rIncPacketCount <= 1;
1108 77 diegovalve
 
1109
                        if (ACK_I == 0)
1110
                                WBMNextState <= `WBM_END_CORE0_WRITE_CYCLE;
1111
                        else
1112
                                WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
1113
                end
1114
//----------------------------------------
1115
                `WBM_END_CORE0_WRITE_CYCLE:
1116
                begin
1117
                        WE_O <=  0;
1118
                        CYC_O <= 0;      //*                                                                                             
1119
                        TGC_O <= 0;
1120
                        TGA_O <= 0;
1121
                        STB_O <= 0;
1122
                        IncIA <= 1;//*          
1123
                        MST_O   <= 1;
1124
                        IncDP <= 0;
1125
                        rResetDp <= 0;
1126 84 diegovalve
                        rIncCoreSelect <= 0;
1127
                        rCoreSelectMask <= 0;
1128
                        rRenderEnable <= 0;
1129
                                                rIncPacketCount <= 0;
1130 77 diegovalve
 
1131
 
1132 84 diegovalve
                        if ((rPacketCount %2) == 0) //Two packets per Core
1133 77 diegovalve
                        begin
1134
                                rClearOutAddress <= 1;
1135
                                rPrepateWriteAddressForNextCore <= 1;
1136 84 diegovalve
                                WBMNextState    <= `WBM_CONFIGURE_NEXT_CORE;
1137 77 diegovalve
                        end
1138
                        else
1139
                        begin
1140
                                rClearOutAddress <= 0;
1141
                                rPrepateWriteAddressForNextCore <= 0;
1142
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
1143
                        end
1144
 
1145
                end
1146
 
1147 84 diegovalve
//------------------------------------------
1148 77 diegovalve
 
1149 84 diegovalve
`WBM_CONFIGURE_NEXT_CORE:
1150
begin
1151
                        WE_O    <=  0;
1152
                        CYC_O <= 0;
1153 77 diegovalve
                        TGC_O <= 0;
1154
                        TGA_O <= 0;
1155
                        STB_O <= 0;
1156 84 diegovalve
                        IncIA <= 0;
1157 77 diegovalve
                        MST_O   <= 1;
1158
                        IncDP <= 0;
1159
                        rResetDp <= 0;
1160 84 diegovalve
 
1161
                        rCoreSelectMask <= 0;
1162
                        rIncCoreSelect <= 1;
1163
                        rRenderEnable <= 0;
1164
                        rIncPacketCount <= 0;
1165 77 diegovalve
 
1166 84 diegovalve
 
1167
                        if (wCoreSelect[`MAX_CORES-1] == 1)
1168
                                WBMNextState <= `WBM_DONE;
1169 77 diegovalve
                        else
1170 84 diegovalve
                                WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
1171
 
1172
 
1173
end
1174
 
1175 77 diegovalve
 
1176 84 diegovalve
 
1177
                //----------------------------------------
1178 61 diegovalve
                //Here everything is ready so just start!
1179
 
1180 13 diegovalve
                `WBM_DONE:
1181
                begin
1182
                        WE_O <=  0;
1183
                        CYC_O <= 0;
1184
                        TGC_O <= 0;
1185
                        TGA_O <= 0;
1186
                        STB_O <= 0;
1187
                        IncIA <= 0;
1188
                        MST_O   <= 0;
1189
                        IncDP <= 0;
1190
                        rResetDp <= 1;
1191 77 diegovalve
                        rClearOutAddress <= 1;
1192 84 diegovalve
                        rCoreSelectMask <= 0;
1193
                        rRenderEnable <= 4'b1111;
1194 77 diegovalve
                        rPrepateWriteAddressForNextCore <= 0;
1195 13 diegovalve
 
1196
                        WBMNextState <= `WBM_DONE;
1197
                end
1198
                //----------------------------------------
1199
 
1200
 
1201
                endcase
1202
        end     //end always
1203
        //----------------------------------------------------------    
1204
 
1205
 
1206
 
1207
 
1208
 
1209
endmodule
1210
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.