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-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

-- --------------------------------------------------------------------------------

-- Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct  4 19:58:22 MDT 2017

-- Date        : Fri Jan 26 22:39:31 2018

-- Host        : Ateana3 running 64-bit major release  (build 9200)

-- Command     : write_vhdl -force -mode synth_stub

--               C:/Cores5/FT64/FT64/FT64.srcs/sources_1/ip/NexysVideoClkgen/NexysVideoClkgen_stub.vhdl

-- Design      : NexysVideoClkgen

-- Purpose     : Stub declaration of top-level module interface

-- Device      : xc7a200tsbg484-1

-- --------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity NexysVideoClkgen is

  Port (

    clk100 : out STD_LOGIC;

    clk400 : out STD_LOGIC;

    clk80 : out STD_LOGIC;

    clk50 : out STD_LOGIC;

    clk200 : out STD_LOGIC;

    reset : in STD_LOGIC;

    locked : out STD_LOGIC;

    clk_in1 : in STD_LOGIC

  );

end NexysVideoClkgen;

architecture stub of NexysVideoClkgen is

attribute syn_black_box : boolean;

attribute black_box_pad_pin : string;

attribute syn_black_box of stub : architecture is true;

attribute black_box_pad_pin of stub : architecture is "clk100,clk400,clk80,clk50,clk200,reset,locked,clk_in1";

begin

end;