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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2012-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module bootrom(rst_i, clk_i, cti_i, cs_i, cyc_i, stb_i, ack_o, adr_i, dat_o);
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parameter WID=64;
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//parameter FNAME = "c:\\cores5\\FT64\\trunk\\software\\boot\\boot.ve0";
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input rst_i;
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input clk_i;
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input [2:0] cti_i;
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input cs_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input [17:0] adr_i;
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output [WID-1:0] dat_o;
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reg [WID-1:0] dat_o;
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integer n;
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reg [WID-1:0] rommem [32767:0];
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reg [14:0] radr;
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reg [2:0] cnt;
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initial begin
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`include "c:\\cores5\\FT64\\trunk\\software\\boot\\boottc.ve0";
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end
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wire cs = cs_i && cyc_i && stb_i;
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reg rdy,rdy1,rdy2;
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always @(posedge clk_i)
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begin
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rdy1 <= cs;
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rdy <= rdy1 & cs & cnt!=3'b100;
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end
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assign ack_o = cs ? rdy : 1'b0;
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wire pe_cs;
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edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee() );
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reg [14:0] ctr;
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always @(posedge clk_i)
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if (pe_cs) begin
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if (cti_i==3'b000)
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ctr[1:0] <= adr_i[4:3];
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else
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ctr[1:0] <= adr_i[4:3] + 2'd1;
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ctr[14:2] <= adr_i[17:5];
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cnt <= 3'b00;
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end
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else if (cs && cnt!=3'b11 && cti_i != 3'b000) begin
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ctr[1:0] <= ctr[1:0] + 2'd1;
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cnt <= cnt + 3'd1;
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end
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always @(posedge clk_i)
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radr <= pe_cs ? adr_i[17:3] : ctr;
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//assign dat_o = cs ? {smemH[radr],smemG[radr],smemF[radr],smemE[radr],
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// smemD[radr],smemC[radr],smemB[radr],smemA[radr]} : 64'd0;
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always @(posedge clk_i)
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dat_o <= rommem[radr];
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endmodule
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