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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64_RSB.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`include "FT64_defines.vh"
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// Return address stack predictor is updated during the fetch stage on the
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// assumption that previous flow controls (branches) predicted correctly.
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// Otherwise many small routines wouldn't predict the return address
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// correctly because they hit the RET before the CALL reaches the
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// commit stage.
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module FT64_RSB(rst, clk, regLR, queued1, queued2,
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fetchbuf0_v, fetchbuf0_pc, fetchbuf0_instr,
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fetchbuf1_v, fetchbuf1_pc, fetchbuf1_instr,
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stompedRets, stompedRet,
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pc
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);
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parameter AMSB = 31;
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parameter DEPTH = 32;
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input rst;
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input clk;
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input [4:0] regLR;
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input queued1;
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input queued2;
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input fetchbuf0_v;
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input [31:0] fetchbuf0_instr;
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input [AMSB:0] fetchbuf0_pc;
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input fetchbuf1_v;
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input [31:0] fetchbuf1_instr;
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input [AMSB:0] fetchbuf1_pc;
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input [3:0] stompedRets;
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input stompedRet;
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output [AMSB:0] pc;
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parameter RSTPC = 32'hFFFC0100;
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integer n;
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reg [AMSB:0] ras [0:DEPTH-1];
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reg [4:0] rasp;
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assign pc = ras[rasp];
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always @(posedge clk)
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if (rst) begin
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for (n = 0; n < 32; n = n + 1)
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ras[n] <= RSTPC;
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rasp <= 5'd0;
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end
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else begin
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if (fetchbuf0_v && fetchbuf1_v && (queued1 || queued2)) begin
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case(fetchbuf0_instr[`INSTRUCTION_OP])
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`JAL:
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begin
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// JAL LR,xxxx assume call
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if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
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ras[((rasp-6'd1)&31)] <= fetchbuf0_pc + 32'd4;
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rasp <= rasp - 4'd1;
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end
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// JAL r0,[r29] assume a ret
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else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
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fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
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rasp <= rasp + 4'd1;
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end
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end
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`CALL:
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begin
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ras[((rasp-6'd1)&31)] <= fetchbuf0_pc + 32'd4;
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rasp <= rasp - 4'd1;
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end
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`RET: begin
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$display("RSP: Added 1");
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rasp <= rasp + 4'd1;
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end
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default: ;
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endcase
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end
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else if (fetchbuf1_v && queued1)
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case(fetchbuf1_instr[`INSTRUCTION_OP])
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`JAL:
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if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
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ras[((rasp-6'd1)&31)] <= fetchbuf1_pc + 32'd4;
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rasp <= rasp - 4'd1;
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end
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else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
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fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
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rasp <= rasp + 4'd1;
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end
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`CALL:
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begin
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ras[((rasp-6'd1)&31)] <= fetchbuf1_pc + 32'd4;
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rasp <= rasp - 4'd1;
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end
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`RET: begin
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rasp <= rasp + 4'd1;
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$display("RSP: Added 1");
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end
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default: ;
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endcase
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else if (fetchbuf0_v && queued1)
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case(fetchbuf0_instr[`INSTRUCTION_OP])
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`JAL:
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if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
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ras[((rasp-6'd1)&31)] <= fetchbuf0_pc + 32'd4;
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rasp <= rasp - 4'd1;
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end
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else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
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fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
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rasp <= rasp + 4'd1;
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end
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`CALL:
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begin
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ras[((rasp-6'd1)&31)] <= fetchbuf0_pc + 32'd4;
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rasp <= rasp - 4'd1;
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end
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`RET: begin
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$display("RSP: Added 1");
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rasp <= rasp + 4'd1;
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end
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default: ;
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endcase
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if (stompedRets > 4'd0) begin
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$display("Stomped Rets: %d", stompedRets);
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rasp <= rasp - stompedRets;
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end
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else if (stompedRet) begin
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$display("Stomped Ret");
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rasp <= rasp - 5'd1;
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end
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end
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endmodule
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