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[/] [thor/] [trunk/] [FT64/] [rtl/] [common/] [FT64_bitfield.v] - Blame information for rev 43

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1 43 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2016-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      FT64_bitfield.v
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//              
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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// ============================================================================
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//
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`ifndef BFSET
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`define BFSET     4'd0
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`define BFCLR     4'd1
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`define BFCHG     4'd2
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`define BFINS     4'd3
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`define BFINSI    4'd4
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`define BFEXT     4'd5
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`define BFEXTU    4'd6
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`endif
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module FT64_bitfield(inst, a, b, o, masko);
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parameter DWIDTH=64;
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input [31:0] inst;
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input [DWIDTH-1:0] a;
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input [DWIDTH-1:0] b;
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output [DWIDTH-1:0] o;
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reg [DWIDTH-1:0] o;
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output [DWIDTH-1:0] masko;
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reg [DWIDTH-1:0] o1;
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reg [DWIDTH-1:0] o2;
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// generate mask
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reg [DWIDTH-1:0] mask;
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assign masko = mask;
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wire [3:0] op = inst[31:28];
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wire [5:0] mb = inst[21:16];
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wire [5:0] me = inst[27:22];
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wire [5:0] ml = me-mb;           // mask length-1
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wire [63:0] imm = {59'd0,inst[10:6]};
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integer nn,n;
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always @(mb or me or nn)
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        for (nn = 0; nn < DWIDTH; nn = nn + 1)
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                mask[nn] <= (nn >= mb) ^ (nn <= me) ^ (me >= mb);
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always @(op,mask,b,a,imm,mb,ml)
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case (op)
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`BFINS:         begin
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                                o2 = a << mb;
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                                for (n = 0; n < DWIDTH; n = n + 1) o[n] = (mask[n] ? o2[n] : b[n]);
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                        end
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`BFINSI:        begin
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                                o2 = imm << mb;
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                                for (n = 0; n < DWIDTH; n = n + 1) o[n] = (mask[n] ? o2[n] : b[n]);
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                        end
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`BFSET:         begin for (n = 0; n < DWIDTH; n = n + 1) o[n] = mask[n] ? 1'b1 : a[n]; end
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//`BFCLR:       begin for (n = 0; n < DWIDTH; n = n + 1) o[n] = mask[n] ? 1'b0 : a[n]; end
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`BFCHG:         begin for (n = 0; n < DWIDTH; n = n + 1) o[n] = mask[n] ? ~a[n] : a[n]; end
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`BFEXTU:        begin
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                                for (n = 0; n < DWIDTH; n = n + 1)
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                                        o1[n] = mask[n] ? a[n] : 1'b0;
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                                o = o1 >> mb;
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                        end
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`BFEXT:         begin
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                                for (n = 0; n < DWIDTH; n = n + 1)
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                                        o1[n] = mask[n] ? a[n] : 1'b0;
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                                o2 = o1 >> mb;
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                                for (n = 0; n < DWIDTH; n = n + 1)
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                                        o[n] = n > ml ? o2[ml] : o2[n];
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                        end
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`ifdef I_SEXT
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`SEXT:          begin for (n = 0; n < DWIDTH; n = n + 1) o[n] = mask[n] ? a[mb] : a[n]; end
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`endif
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default:        o = {DWIDTH{1'b0}};
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endcase
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endmodule
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