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[/] [thor/] [trunk/] [FT64/] [rtl/] [lib/] [down_counter.v] - Blame information for rev 46

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1 46 robfinch
// ============================================================================
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//  down_counter.v
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//  - counts down
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//
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//
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//      2010  Robert Finch
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//      pfingh>remove<@birdcomputer.ca
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//
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//
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//  This source code is available for evaluation and validation purposes
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//  only. This copyright statement and disclaimer must remain present in
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//  the file.
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//
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//
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//      NO WARRANTY.
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//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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//  EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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//  Work.
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//
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//  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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//
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//  IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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//  IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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//  REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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//  LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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//  AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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//  LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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//
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//
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//      Verilog 1995
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// ============================================================================
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module down_counter(rst, clk, ce, ld, d, q, z);
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parameter WID=8;
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input rst;
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input clk;
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input ce;
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input ld;
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input [WID:1] d;
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output [WID:1] q;
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reg [WID:1] q;
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output z;
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always @(posedge clk)
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        if (rst)
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                q <= 0;
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        else if (ce) begin
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                if (ld)
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                        q <= d;
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                else
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                        q <= q + {WID{1'b1}};
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        end
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assign z = q == 0;
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endmodule

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