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//

//      COPYRIGHT 2000 by Bruce L. Jacob

//      (contact info: http://www.ece.umd.edu/~blj/)

//

//      You are welcome to use, modify, copy, and/or redistribute this implementation, provided:

//        1. you share with the author (Bruce Jacob) any changes you make;

//        2. you properly credit the author (Bruce Jacob) if used within a larger work; and

//        3. you do not modify, delete, or in any way obscure the implementation's copyright 

//           notice or following comments (i.e. the first 3-4 dozen lines of this file).

//

//      RiSC-16

//

//      This is an out-of-order implementation of the RiSC-16, a teaching instruction-set used by

//      the author at the University of Maryland, and which is a blatant (but sanctioned) rip-off

//      of the Little Computer (LC-896) developed by Peter Chen at the University of Michigan.

//      The primary differences include the following:

//        1. a move from 17-bit to 16-bit instructions; and

//        2. the replacement of the NOP and HALT opcodes by ADDI and LUI ... HALT and NOP are

//           now simply special instances of other instructions: NOP is a do-nothing ADD, and

//           HALT is a subset of JALR.

//

//      RiSC stands for Ridiculously Simple Computer, which makes sense in the context in which

//      the instruction-set is normally used -- to teach simple organization and architecture to

//      undergraduates who do not yet know how computers work.  This implementation was targetted

//      towards more advanced undergraduates doing design & implementation and was intended to 

//      demonstrate some high-performance concepts on a small scale -- an 8-entry reorder buffer,

//      eight opcodes, two ALUs, two-way issue, two-way commit, etc.  However, the out-of-order 

//      core is much more complex than I anticipated, and I hope that its complexity does not 

//      obscure its underlying structure.  We'll see how well it flies in class ...

//

//      CAVEAT FREELOADER: This Verilog implementation was developed and debugged in a (somewhat

//      frantic) 2-week period before the start of the Fall 2000 semester.  Not surprisingly, it

//      still contains many bugs and some horrible, horrible logic.  The logic is also written so

//      as to be debuggable and/or explain its function, rather than to be efficient -- e.g. in

//      several places, signals are over-constrained so that they are easy to read in the debug

//      output ... also, you will see statements like

//

//          if (xyz[`INSTRUCTION_OP] == `BEQ || xyz[`INSTRUCTION_OP] == `SW)

//

//      instead of and/nand combinations of bits ... sorry; can't be helped.  Use at your own risk.

//

//      DOCUMENTATION: Documents describing the RiSC-16 in all its forms (sequential, pipelined,

//      as well as out-of-order) can be found on the author's website at the following URL:

//

//          http://www.ece.umd.edu/~blj/RiSC/

//

//      If you do not find what you are looking for, please feel free to email me with suggestions

//      for more/different/modified documents.  Same goes for bug fixes.

//

//

//      KNOWN PROBLEMS (i.e., bugs I haven't got around to fixing yet)

//

//      - If the target of a backwards branch is a backwards branch, the fetchbuf steering logic

//        will get confused.  This can be fixed by having a separate did_branchback status register

//        for each of the fetch buffers.

//

// ============================================================================

//        __

//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@finitron.ca

//       ||

//

//      FT64.v

//      Modification to RiSC-16 include:

//  - move to 32 bit instructions

//  - additional instructions added

//  - vector instruction set,

//  - SIMD instructions

//  - extension of data width to 64 bits

//      - 32 general purpose registers

//  - 32 floating point registers

//      - 32 vector registers, length 63

//  - addition of more powerful branch prediction

//  - branch target buffer (BTB)

//  - return address predictor (RSB)

//  - bus interface unit

//  - instruction and data caches

//  - asynchronous logic loops for issue and branch miss

//    re-written for synchronous operation, not as elegant

//    but required for operation in an FPGA

//      - fine-grained simultaneous multi-threading (SMT)

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//

// Approx. 100,000 LUTs. 160,000 LC's.

// ============================================================================

//

`include "FT64_defines.vh"

`define SUPPORT_SMT             1'b1

//`define SUPPORT_DBG           1'b1

`define FULL_ISSUE_LOGIC        1'b1

`define QBITS           2:0

`define QENTRIES        8

module FT64(hartid, rst, clk, clk4x, irq_i, vec_i, bte_o, cti_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,

    ol_o, pcr_o, pcr2_o, exv_i, rdv_i, wrv_i, icl_o, sr_o, cr_o, rbi_i, signal_i);

input [63:0] hartid;

input rst;

input clk;

input clk4x;

input [2:0] irq_i;

input [8:0] vec_i;

output reg [1:0] bte_o;

output reg [2:0] cti_o;

output reg cyc_o;

output reg stb_o;

input ack_i;

input err_i;

output reg we_o;

output reg [7:0] sel_o;

output reg [31:0] adr_o;

output reg [63:0] dat_o;

input [63:0] dat_i;

output [2:0] ol_o;

output [31:0] pcr_o;

output [63:0] pcr2_o;

input exv_i;

input rdv_i;

input wrv_i;

output reg icl_o;

output reg cr_o;

output reg sr_o;

input rbi_i;

input [31:0] signal_i;

parameter QENTRIES = `QENTRIES;

parameter RSTPC = 32'hFFFC0100;

parameter BRKPC = 32'hFFFC0000;

`ifdef SUPPORT_SMT

parameter PREGS = 256;   // number of physical registers - 1

parameter AREGS = 256;   // number of architectural registers

`else

parameter PREGS = 128;

parameter AREGS = 128;

`endif

parameter RBIT = 11;

parameter DEBUG = 1'b0;

parameter NMAP = QENTRIES;

parameter BRANCH_PRED = 1'b0;

parameter SUP_TXE = 1'b0;

parameter SUP_VECTOR = 1;

parameter DBW = 64;

parameter ABW = 32;

parameter AMSB = ABW-1;

parameter NTHREAD = 1;

reg [3:0] i;

integer n;

integer j;

genvar g;

parameter TRUE = 1'b1;

parameter FALSE = 1'b0;

// Memory access sizes

parameter byt = 3'd0;

parameter wyde = 3'd1;

parameter tetra = 3'd2;

parameter octa = 3'd3;

wire [RBIT:0] Ra0, Ra1;

wire [RBIT:0] Rb0, Rb1;

wire [RBIT:0] Rc0, Rc1;

wire [RBIT:0] Rt0, Rt1;

wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a;

wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a;

`ifdef SUPPORT_SMT

wire [7:0] Ra0s = {Ra0[7:0]};

wire [7:0] Ra1s = {Ra1[7:0]};

wire [7:0] Rb0s = {Rb0[7:0]};

wire [7:0] Rb1s = {Rb1[7:0]};

wire [7:0] Rc0s = {Rc0[7:0]};

wire [7:0] Rc1s = {Rc1[7:0]};

wire [7:0] Rt0s = {Rt0[7:0]};

wire [7:0] Rt1s = {Rt1[7:0]};

`else

wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};

wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};

wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};

wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};

wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};

wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};

wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};

wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};

/*

wire [5:0] Ra0s = {Ra0[5:0]};

wire [5:0] Ra1s = {Ra1[5:0]};

wire [5:0] Rb0s = {Rb0[5:0]};

wire [5:0] Rb1s = {Rb1[5:0]};

wire [5:0] Rc0s = {Rc0[5:0]};

wire [5:0] Rc1s = {Rc1[5:0]};

wire [5:0] Rt0s = {Rt0[5:0]};

wire [5:0] Rt1s = {Rt1[5:0]};

*/

`endif

reg  [PREGS-1:0] rf_v;

reg  [4:0] rf_source[0:AREGS-1];

initial begin

for (n = 0; n < AREGS; n = n + 1)

        rf_source[n] = 5'd0;

end

wire [31:0] pc0;

wire [31:0] pc1;

reg excmiss;

reg [31:0] excmisspc;

reg excthrd;

reg exception_set;

reg rdvq;               // accumulated read violation

reg errq;               // accumulated err_i input status

reg exvq;

// Vector

reg [5:0] vqe0, vqe1;   // vector element being queued

reg [5:0] vqet0, vqet1;

reg [7:0] vl;           // vector length

reg [63:0] vm [0:7];    // vector mask registers

reg [1:0] m2;

// CSR's

reg [63:0] cr0;

wire snr = cr0[17];             // sequence number reset

wire dce = cr0[30];     // data cache enable

wire bpe = cr0[32];     // branch predictor enable

wire ctgtxe = cr0[33];

// Simply setting this flag to zero should strip out almost all the logic

// associated SMT.

`ifdef SUPPORT_SMT

wire thread_en = cr0[16];

`else

wire thread_en = 1'b0;

`endif

wire vechain = cr0[18];

reg [7:0] fcu_timeout;

reg [63:0] tick;

reg [31:0] pcr;

reg [63:0] pcr2;

assign pcr_o = pcr;

assign pcr2_o = pcr2;

reg [63:0] aec;

reg [15:0] cause[0:15];

reg [31:0] epc [0:NTHREAD];

reg [31:0] epc0 [0:NTHREAD];

reg [31:0] epc1 [0:NTHREAD];

reg [31:0] epc2 [0:NTHREAD];

reg [31:0] epc3 [0:NTHREAD];

reg [31:0] epc4 [0:NTHREAD];

reg [31:0] epc5 [0:NTHREAD];

reg [31:0] epc6 [0:NTHREAD];

reg [31:0] epc7 [0:NTHREAD];

reg [31:0] epc8 [0:NTHREAD];                      // exception pc and stack

reg [63:0] mstatus [0:NTHREAD];           // machine status

wire [2:0] im = mstatus[0][2:0];

wire [2:0] ol [0:NTHREAD];

assign ol[0] = mstatus[0][5:3];   // operating level

wire [7:0] cpl [0:NTHREAD];

assign cpl[0] = mstatus[0][13:6]; // current privilege level

wire [5:0] rgs [0:NTHREAD];

assign rgs[0] = mstatus[0][19:14];

`ifdef SUPPORT_SMT

assign ol[1] = mstatus[1][5:3]; // operating level

assign cpl[1] = mstatus[1][13:6];       // current privilege level

assign rgs[1] = mstatus[1][19:14];

`endif

reg [23:0] ol_stack [0:NTHREAD];

reg [23:0] im_stack [0:NTHREAD];

reg [63:0] pl_stack [0:NTHREAD];

reg [63:0] rs_stack [0:NTHREAD];

reg [63:0] fr_stack [0:NTHREAD];

wire mprv = mstatus[0][55];

wire [5:0] fprgs = mstatus[0][25:20];

assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];

wire vca = mstatus[0][32];               // vector chaining active

reg [31:0] badaddr[0:15];

reg [31:0] tvec[0:7];

reg [63:0] sema;

reg [63:0] cas;         // compare and swap

reg [63:0] ve_hold;

reg isCAS, isAMO;

reg [`QBITS] casid;

reg [31:0] sbl, sbu;

reg [4:0] regLR = 5'd29;

reg [2:0] fp_rm;

reg fp_inexe;

reg fp_dbzxe;

reg fp_underxe;

reg fp_overxe;

reg fp_invopxe;

reg fp_giopxe;

reg fp_nsfp = 1'b0;

reg fp_fractie;

reg fp_raz;

reg fp_neg;

reg fp_pos;

reg fp_zero;

reg fp_inf;

reg fp_inex;            // inexact exception

reg fp_dbzx;            // divide by zero exception

reg fp_underx;          // underflow exception

reg fp_overx;           // overflow exception

reg fp_giopx;           // global invalid operation exception

reg fp_sx;                      // summary exception

reg fp_swtx;        // software triggered exception

reg fp_gx;

reg fp_invopx;

reg fp_infzerox;

reg fp_zerozerox;

reg fp_subinfx;

reg fp_infdivx;

reg fp_NaNCmpx;

reg fp_cvtx;

reg fp_sqrtx;

reg fp_snanx;

wire [31:0] fp_status = {

        fp_rm,

        fp_inexe,

        fp_dbzxe,

        fp_underxe,

        fp_overxe,

        fp_invopxe,

        fp_nsfp,

        fp_fractie,

        fp_raz,

        1'b0,

        fp_neg,

        fp_pos,

        fp_zero,

        fp_inf,

        fp_swtx,

        fp_inex,

        fp_dbzx,

        fp_underx,

        fp_overx,

        fp_giopx,

        fp_gx,

        fp_sx,

        fp_cvtx,

        fp_sqrtx,

        fp_NaNCmpx,

        fp_infzerox,

        fp_zerozerox,

        fp_infdivx,

        fp_subinfx,

        fp_snanx

        };

reg [63:0] fpu_csr;

//reg [25:0] m[0:8191];

reg  [3:0] panic;                // indexes the message structure

reg [128:0] message [0:15];       // indexed by panic

wire int_commit;

reg StatusHWI;

reg [31:0] insn0, insn1;

wire [31:0] insn0a, insn1a;

reg tgtq;

// Only need enough bits in the seqnence number to cover the instructions in

// the queue plus an extra count for skipping on branch misses. In this case

// that would be four bits minimum (count 0 to 8). 

reg [31:0] seq_num;

reg [31:0] seq_num1;

wire [63:0] rdat0,rdat1,rdat2;

reg [63:0] xdati;

reg canq1, canq2;

reg queued1;

reg queued2;

reg queuedNop;

reg [31:0] codebuf[0:63];

reg [7:0] setpred;

// instruction queue (ROB)

reg [31:0]  iqentry_sn   [0:QENTRIES-1];  // instruction sequence number

reg [QENTRIES-1:0] iqentry_v;                    // entry valid?  -- this should be the first bit

reg        iqentry_out  [0:QENTRIES-1];  // instruction has been issued to an ALU ... 

reg        iqentry_done [0:QENTRIES-1];  // instruction result valid

reg        iqentry_cmt  [0:QENTRIES-1];

reg [QENTRIES-1:0] iqentry_thrd;         // which thread the instruction is in

reg        iqentry_pred [0:QENTRIES-1];  // predicate bit

reg        iqentry_bt   [0:QENTRIES-1];  // branch-taken (used only for branches)

reg        iqentry_agen         [0:QENTRIES-1];  // address-generate ... signifies that address is ready (only for LW/SW)

reg        iqentry_alu  [0:QENTRIES-1];  // alu type instruction

reg [QENTRIES-1:0] iqentry_alu0;  // only valid on alu #0

reg        iqentry_fpu  [0:QENTRIES-1];  // floating point instruction

reg        iqentry_fc   [0:QENTRIES-1];   // flow control instruction

reg        iqentry_canex[0:QENTRIES-1];  // true if it's an instruction that can exception

reg        iqentry_load [0:QENTRIES-1];  // is a memory load instruction

reg        iqentry_mem  [0:QENTRIES-1];  // touches memory: 1 if LW/SW

reg        iqentry_memndx   [0:QENTRIES-1];  // indexed memory operation 

reg        iqentry_memdb    [0:QENTRIES-1];

reg        iqentry_memsb    [0:QENTRIES-1];

reg        iqentry_aq   [0:QENTRIES-1];  // memory aquire

reg        iqentry_rl   [0:QENTRIES-1];  // memory release

reg        iqentry_jmp  [0:QENTRIES-1];  // changes control flow: 1 if BEQ/JALR

reg        iqentry_br   [0:QENTRIES-1];  // Bcc (for predictor)

reg        iqentry_sync [0:QENTRIES-1];  // sync instruction

reg        iqentry_fsync[0:QENTRIES-1];

reg        iqentry_rfw  [0:QENTRIES-1];  // writes to register file

reg  [7:0] iqentry_we   [0:QENTRIES-1];   // enable strobe

reg [63:0] iqentry_res   [0:QENTRIES-1];  // instruction result

reg [31:0] iqentry_instr[0:QENTRIES-1];   // instruction opcode

reg  [3:0] iqentry_exc   [0:QENTRIES-1];  // only for branches ... indicates a HALT instruction

reg [RBIT:0] iqentry_tgt [0:QENTRIES-1];  // Rt field or ZERO -- this is the instruction's target (if any)

reg  [5:0] iqentry_ven  [0:QENTRIES-1];  // vector element number

reg [63:0] iqentry_a0    [0:QENTRIES-1];  // argument 0 (immediate)

reg [63:0] iqentry_a1    [0:QENTRIES-1];  // argument 1

reg        iqentry_a1_v [0:QENTRIES-1];  // arg1 valid

reg  [4:0] iqentry_a1_s  [0:QENTRIES-1];  // arg1 source (iq entry # with top bit representing ALU/DRAM bus)

reg [63:0] iqentry_a2    [0:QENTRIES-1];  // argument 2

reg        iqentry_a2_v [0:QENTRIES-1];  // arg2 valid

reg  [4:0] iqentry_a2_s  [0:QENTRIES-1];  // arg2 source (iq entry # with top bit representing ALU/DRAM bus)

reg [63:0] iqentry_a3    [0:QENTRIES-1];  // argument 3

reg        iqentry_a3_v [0:QENTRIES-1];  // arg3 valid

reg  [4:0] iqentry_a3_s  [0:QENTRIES-1];  // arg3 source (iq entry # with top bit representing ALU/DRAM bus)

reg [31:0] iqentry_pc    [0:QENTRIES-1];  // program counter for this instruction

reg [RBIT:0] iqentry_Ra [0:QENTRIES-1];

reg [RBIT:0] iqentry_Rb [0:QENTRIES-1];

reg [RBIT:0] iqentry_Rc [0:QENTRIES-1];

// debugging

//reg  [4:0] iqentry_ra   [0:7];  // Ra

initial begin

for (n = 0; n < QENTRIES; n = n + 1)

        iqentry_a1_s[n] = 5'd0;

        iqentry_a2_s[n] = 5'd0;

        iqentry_a3_s[n] = 5'd0;

end

wire  [QENTRIES-1:0] iqentry_source;

reg   [QENTRIES-1:0] iqentry_imm;

wire  [QENTRIES-1:0] iqentry_memready;

wire  [QENTRIES-1:0] iqentry_memopsvalid;

reg  [QENTRIES-1:0] memissue;

reg [1:0] missued;

integer last_issue;

reg  [QENTRIES-1:0] iqentry_memissue;

wire [QENTRIES-1:0] iqentry_stomp;

reg [3:0] stompedOnRets;

reg  [QENTRIES-1:0] iqentry_issue;

reg [1:0] iqentry_islot [0:QENTRIES-1];

reg [1:0] iqentry_mem_islot [0:QENTRIES-1];

reg [1:0] iqentry_fpu_islot [0:QENTRIES-1];

reg [QENTRIES-1:0] iqentry_fcu_issue;

reg [QENTRIES-1:0] iqentry_fpu_issue;

wire [PREGS-1:1] livetarget;

wire  [PREGS-1:1] iqentry_0_livetarget;

wire  [PREGS-1:1] iqentry_1_livetarget;

wire  [PREGS-1:1] iqentry_2_livetarget;

wire  [PREGS-1:1] iqentry_3_livetarget;

wire  [PREGS-1:1] iqentry_4_livetarget;

wire  [PREGS-1:1] iqentry_5_livetarget;

wire  [PREGS-1:1] iqentry_6_livetarget;

wire  [PREGS-1:1] iqentry_7_livetarget;

wire  [PREGS-1:1] iqentry_0_latestID;

wire  [PREGS-1:1] iqentry_1_latestID;

wire  [PREGS-1:1] iqentry_2_latestID;

wire  [PREGS-1:1] iqentry_3_latestID;

wire  [PREGS-1:1] iqentry_4_latestID;

wire  [PREGS-1:1] iqentry_5_latestID;

wire  [PREGS-1:1] iqentry_6_latestID;

wire  [PREGS-1:1] iqentry_7_latestID;

wire  [PREGS-1:1] iqentry_0_cumulative;

wire  [PREGS-1:1] iqentry_1_cumulative;

wire  [PREGS-1:1] iqentry_2_cumulative;

wire  [PREGS-1:1] iqentry_3_cumulative;

wire  [PREGS-1:1] iqentry_4_cumulative;

wire  [PREGS-1:1] iqentry_5_cumulative;

wire  [PREGS-1:1] iqentry_6_cumulative;

wire  [PREGS-1:1] iqentry_7_cumulative;

wire  [PREGS-1:1] iq0_out;

wire  [PREGS-1:1] iq1_out;

wire  [PREGS-1:1] iq2_out;

wire  [PREGS-1:1] iq3_out;

wire  [PREGS-1:1] iq4_out;

wire  [PREGS-1:1] iq5_out;

wire  [PREGS-1:1] iq6_out;

wire  [PREGS-1:1] iq7_out;

reg  [`QBITS] tail0;

reg  [`QBITS] tail1;

reg  [`QBITS] head0;

reg  [`QBITS] head1;

reg  [`QBITS] head2;    // used only to determine memory-access ordering

reg  [`QBITS] head3;    // used only to determine memory-access ordering

reg  [`QBITS] head4;    // used only to determine memory-access ordering

reg  [`QBITS] head5;    // used only to determine memory-access ordering

reg  [`QBITS] head6;    // used only to determine memory-access ordering

reg  [`QBITS] head7;    // used only to determine memory-access ordering

wire  [`QBITS] missid;

wire take_branch0;

wire take_branch1;

reg [3:0] nop_fetchbuf;

wire        fetchbuf;   // determines which pair to read from & write to

wire [31:0] fetchbuf0_instr;

wire [31:0] fetchbuf0_pc;

wire        fetchbuf0_v;

wire            fetchbuf0_thrd;

wire        fetchbuf0_mem;

wire            fetchbuf0_memld;

wire        fetchbuf0_jmp;

wire        fetchbuf0_rfw;

wire [31:0] fetchbuf1_instr;

wire [31:0] fetchbuf1_pc;

wire        fetchbuf1_v;

wire            fetchbuf1_thrd;

wire        fetchbuf1_mem;

wire            fetchbuf1_memld;

wire        fetchbuf1_jmp;

wire        fetchbuf1_rfw;

wire [31:0] fetchbufA_instr;

wire [31:0] fetchbufA_pc;

wire        fetchbufA_v;

wire [31:0] fetchbufB_instr;

wire [31:0] fetchbufB_pc;

wire        fetchbufB_v;

wire [31:0] fetchbufC_instr;

wire [31:0] fetchbufC_pc;

wire        fetchbufC_v;

wire [31:0] fetchbufD_instr;

wire [31:0] fetchbufD_pc;

wire        fetchbufD_v;

//reg        did_branchback0;