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[/] [thor/] [trunk/] [FT64/] [rtl/] [twoway/] [FT64_regfile2w6r_oc.v] - Blame information for rev 43

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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2013-2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
// Register file with two write ports and six read ports.
// ============================================================================
//
`define SIM
 
module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);
parameter WID=64;
parameter RBIT = 11;
input clka;
input ena;
input [7:0] wea;
input [RBIT:0] addra;
input [WID-1:0] dina;
input clkb;
input enb;
input [RBIT:0] addrb;
output [WID-1:0] doutb;
 
integer n;
(* RAM_STYLE="BLOCK" *)
reg [63:0] mem [0:4095];
reg [RBIT:0] raddrb;
 
initial begin
        for (n = 0; n < 4096; n = n + 1)
                mem[n] = 0;
end
 
always @(posedge clka) if (ena & wea[0]) mem[addra][7:0] <= dina[7:0];
always @(posedge clka) if (ena & wea[1]) mem[addra][15:8] <= dina[15:8];
always @(posedge clka) if (ena & wea[2]) mem[addra][23:16] <= dina[23:16];
always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];
always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];
always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];
always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];
always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];
 
always @(posedge clkb)
        raddrb <= addrb;
assign doutb = mem[raddrb];
 
endmodule
 
module FT64_regfile2w6r_oc(clk4x, clk, wr0, wr1, we0, we1, wa0, wa1, i0, i1,
        rclk, ra0, ra1, ra2, ra3, ra4, ra5,
        o0, o1, o2, o3, o4, o5);
parameter WID=64;
parameter RBIT = 11;
input clk4x;
input clk;
input wr0;
input wr1;
input [7:0] we0;
input [7:0] we1;
input [RBIT:0] wa0;
input [RBIT:0] wa1;
input [WID-1:0] i0;
input [WID-1:0] i1;
input rclk;
input [RBIT:0] ra0;
input [RBIT:0] ra1;
input [RBIT:0] ra2;
input [RBIT:0] ra3;
input [RBIT:0] ra4;
input [RBIT:0] ra5;
output [WID-1:0] o0;
output [WID-1:0] o1;
output [WID-1:0] o2;
output [WID-1:0] o3;
output [WID-1:0] o4;
output [WID-1:0] o5;
 
reg wr;
reg [RBIT:0] wa;
reg [WID-1:0] i;
reg [7:0] we;
wire [WID-1:0] o00, o01, o02, o03, o04, o05;
reg wr1x;
reg [RBIT:0] wa1x;
reg [WID-1:0] i1x;
reg [7:0] we1x;
 
`ifdef SIM
FT64_regfileRam_sim urf10 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra0),
  .doutb(o00)
);
 
FT64_regfileRam_sim urf11 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra1),
  .doutb(o01)
);
 
FT64_regfileRam_sim urf12 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra2),
  .doutb(o02)
);
 
FT64_regfileRam_sim urf13 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra3),
  .doutb(o03)
);
 
FT64_regfileRam_sim urf14 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra4),
  .doutb(o04)
);
 
FT64_regfileRam_sim urf15 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra5),
  .doutb(o05)
);
`else
FT64_regfileRam urf10 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra0),
  .doutb(o00)
);
 
FT64_regfileRam urf11 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra1),
  .doutb(o01)
);
 
FT64_regfileRam urf12 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra2),
  .doutb(o02)
);
 
FT64_regfileRam urf13 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra3),
  .doutb(o03)
);
 
FT64_regfileRam urf14 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra4),
  .doutb(o04)
);
 
FT64_regfileRam urf15 (
  .clka(clk4x),
  .ena(wr),
  .wea(we),
  .addra(wa),
  .dina(i),
  .clkb(rclk),
  .enb(1'b1),
  .addrb(ra5),
  .doutb(o05)
);
`endif
 
// The same clock edge that would normally update the register file is the
// clock edge that causes the data to disappear for the next cycle. The
// data needs to be held onto so that it can update the register file on
// the next 4x clock.
always @(posedge clk)
begin
        wr1x <= wr1;
        we1x <= we1;
        wa1x <= wa1;
        i1x <= i1;
end
 
reg wclk2;
always @(posedge clk4x)
begin
        wclk2 <= clk;
        if (clk & ~wclk2) begin
                wr <= wr0;
                we <= we0;
                wa <= wa0;
                i <= i0;
        end
        else if (clk & wclk2) begin
                wr <= wr1x;
                we <= we1x;
                wa <= wa1x;
                i <= i1x;
        end
        else begin
                wr <= 1'b0;
                we <= 8'h00;
                wa <= 'd0;
                i <= 'd0;
        end
end
 
assign o0 = ra0[4:0]==5'd0 ? {WID{1'b0}} :
        (wr1 && (ra0==wa1)) ? i1 :
        (wr0 && (ra0==wa0)) ? i0 : o00;
assign o1 = ra1[4:0]==5'd0 ? {WID{1'b0}} :
        (wr1 && (ra1==wa1)) ? i1 :
        (wr0 && (ra1==wa0)) ? i0 : o01;
assign o2 = ra2[4:0]==5'd0 ? {WID{1'b0}} :
        (wr1 && (ra2==wa1)) ? i1 :
        (wr0 && (ra2==wa0)) ? i0 : o02;
assign o3 = ra3[4:0]==5'd0 ? {WID{1'b0}} :
        (wr1 && (ra3==wa1)) ? i1 :
        (wr0 && (ra3==wa0)) ? i0 : o03;
assign o4 = ra4[4:0]==5'd0 ? {WID{1'b0}} :
    (wr1 && (ra4==wa1)) ? i1 :
    (wr0 && (ra4==wa0)) ? i0 : o04;
assign o5 = ra5[4:0]==5'd0 ? {WID{1'b0}} :
    (wr1 && (ra5==wa1)) ? i1 :
    (wr0 && (ra5==wa0)) ? i0 : o05;
 
endmodule
 

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[/] [thor/] [trunk/] [FT64/] [rtl/] [twoway/] [FT64_regfile2w6r_oc.v] - Blame information for rev 43

Line No.	Rev	Author	Line
1	43	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2013-2018 Robert Finch, Waterloo`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`// Register file with two write ports and six read ports.`
24			`// ============================================================================`
25			`//`
26			`define SIM
27
28			`module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);`
29			`parameter WID=64;`
30			`parameter RBIT = 11;`
31			`input clka;`
32			`input ena;`
33			`input [7:0] wea;`
34			`input [RBIT:0] addra;`
35			`input [WID-1:0] dina;`
36			`input clkb;`
37			`input enb;`
38			`input [RBIT:0] addrb;`
39			`output [WID-1:0] doutb;`
40
41			`integer n;`
42			`(* RAM_STYLE="BLOCK" *)`
43			`reg [63:0] mem [0:4095];`
44			`reg [RBIT:0] raddrb;`
45
46			`initial begin`
47			`for (n = 0; n < 4096; n = n + 1)`
48			`mem[n] = 0;`
49			`end`
50
51			`always @(posedge clka) if (ena & wea[0]) mem[addra][7:0] <= dina[7:0];`
52			`always @(posedge clka) if (ena & wea[1]) mem[addra][15:8] <= dina[15:8];`
53			`always @(posedge clka) if (ena & wea[2]) mem[addra][23:16] <= dina[23:16];`
54			`always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];`
55			`always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];`
56			`always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];`
57			`always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];`
58			`always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];`
59
60			`always @(posedge clkb)`
61			`raddrb <= addrb;`
62			`assign doutb = mem[raddrb];`
63
64			`endmodule`
65
66			`module FT64_regfile2w6r_oc(clk4x, clk, wr0, wr1, we0, we1, wa0, wa1, i0, i1,`
67			`rclk, ra0, ra1, ra2, ra3, ra4, ra5,`
68			`o0, o1, o2, o3, o4, o5);`
69			`parameter WID=64;`
70			`parameter RBIT = 11;`
71			`input clk4x;`
72			`input clk;`
73			`input wr0;`
74			`input wr1;`
75			`input [7:0] we0;`
76			`input [7:0] we1;`
77			`input [RBIT:0] wa0;`
78			`input [RBIT:0] wa1;`
79			`input [WID-1:0] i0;`
80			`input [WID-1:0] i1;`
81			`input rclk;`
82			`input [RBIT:0] ra0;`
83			`input [RBIT:0] ra1;`
84			`input [RBIT:0] ra2;`
85			`input [RBIT:0] ra3;`
86			`input [RBIT:0] ra4;`
87			`input [RBIT:0] ra5;`
88			`output [WID-1:0] o0;`
89			`output [WID-1:0] o1;`
90			`output [WID-1:0] o2;`
91			`output [WID-1:0] o3;`
92			`output [WID-1:0] o4;`
93			`output [WID-1:0] o5;`
94
95			`reg wr;`
96			`reg [RBIT:0] wa;`
97			`reg [WID-1:0] i;`
98			`reg [7:0] we;`
99			`wire [WID-1:0] o00, o01, o02, o03, o04, o05;`
100			`reg wr1x;`
101			`reg [RBIT:0] wa1x;`
102			`reg [WID-1:0] i1x;`
103			`reg [7:0] we1x;`
104
105			`ifdef SIM
106			`FT64_regfileRam_sim urf10 (`
107			`.clka(clk4x),`
108			`.ena(wr),`
109			`.wea(we),`
110			`.addra(wa),`
111			`.dina(i),`
112			`.clkb(rclk),`
113			`.enb(1'b1),`
114			`.addrb(ra0),`
115			`.doutb(o00)`
116			`);`
117
118			`FT64_regfileRam_sim urf11 (`
119			`.clka(clk4x),`
120			`.ena(wr),`
121			`.wea(we),`
122			`.addra(wa),`
123			`.dina(i),`
124			`.clkb(rclk),`
125			`.enb(1'b1),`
126			`.addrb(ra1),`
127			`.doutb(o01)`
128			`);`
129
130			`FT64_regfileRam_sim urf12 (`
131			`.clka(clk4x),`
132			`.ena(wr),`
133			`.wea(we),`
134			`.addra(wa),`
135			`.dina(i),`
136			`.clkb(rclk),`
137			`.enb(1'b1),`
138			`.addrb(ra2),`
139			`.doutb(o02)`
140			`);`
141
142			`FT64_regfileRam_sim urf13 (`
143			`.clka(clk4x),`
144			`.ena(wr),`
145			`.wea(we),`
146			`.addra(wa),`
147			`.dina(i),`
148			`.clkb(rclk),`
149			`.enb(1'b1),`
150			`.addrb(ra3),`
151			`.doutb(o03)`
152			`);`
153
154			`FT64_regfileRam_sim urf14 (`
155			`.clka(clk4x),`
156			`.ena(wr),`
157			`.wea(we),`
158			`.addra(wa),`
159			`.dina(i),`
160			`.clkb(rclk),`
161			`.enb(1'b1),`
162			`.addrb(ra4),`
163			`.doutb(o04)`
164			`);`
165
166			`FT64_regfileRam_sim urf15 (`
167			`.clka(clk4x),`
168			`.ena(wr),`
169			`.wea(we),`
170			`.addra(wa),`
171			`.dina(i),`
172			`.clkb(rclk),`
173			`.enb(1'b1),`
174			`.addrb(ra5),`
175			`.doutb(o05)`
176			`);`
177			`else
178			`FT64_regfileRam urf10 (`
179			`.clka(clk4x),`
180			`.ena(wr),`
181			`.wea(we),`
182			`.addra(wa),`
183			`.dina(i),`
184			`.clkb(rclk),`
185			`.enb(1'b1),`
186			`.addrb(ra0),`
187			`.doutb(o00)`
188			`);`
189
190			`FT64_regfileRam urf11 (`
191			`.clka(clk4x),`
192			`.ena(wr),`
193			`.wea(we),`
194			`.addra(wa),`
195			`.dina(i),`
196			`.clkb(rclk),`
197			`.enb(1'b1),`
198			`.addrb(ra1),`
199			`.doutb(o01)`
200			`);`
201
202			`FT64_regfileRam urf12 (`
203			`.clka(clk4x),`
204			`.ena(wr),`
205			`.wea(we),`
206			`.addra(wa),`
207			`.dina(i),`
208			`.clkb(rclk),`
209			`.enb(1'b1),`
210			`.addrb(ra2),`
211			`.doutb(o02)`
212			`);`
213
214			`FT64_regfileRam urf13 (`
215			`.clka(clk4x),`
216			`.ena(wr),`
217			`.wea(we),`
218			`.addra(wa),`
219			`.dina(i),`
220			`.clkb(rclk),`
221			`.enb(1'b1),`
222			`.addrb(ra3),`
223			`.doutb(o03)`
224			`);`
225
226			`FT64_regfileRam urf14 (`
227			`.clka(clk4x),`
228			`.ena(wr),`
229			`.wea(we),`
230			`.addra(wa),`
231			`.dina(i),`
232			`.clkb(rclk),`
233			`.enb(1'b1),`
234			`.addrb(ra4),`
235			`.doutb(o04)`
236			`);`
237
238			`FT64_regfileRam urf15 (`
239			`.clka(clk4x),`
240			`.ena(wr),`
241			`.wea(we),`
242			`.addra(wa),`
243			`.dina(i),`
244			`.clkb(rclk),`
245			`.enb(1'b1),`
246			`.addrb(ra5),`
247			`.doutb(o05)`
248			`);`
249			`endif
250
251			`// The same clock edge that would normally update the register file is the`
252			`// clock edge that causes the data to disappear for the next cycle. The`
253			`// data needs to be held onto so that it can update the register file on`
254			`// the next 4x clock.`
255			`always @(posedge clk)`
256			`begin`
257			`wr1x <= wr1;`
258			`we1x <= we1;`
259			`wa1x <= wa1;`
260			`i1x <= i1;`
261			`end`
262
263			`reg wclk2;`
264			`always @(posedge clk4x)`
265			`begin`
266			`wclk2 <= clk;`
267			`if (clk & ~wclk2) begin`
268			`wr <= wr0;`
269			`we <= we0;`
270			`wa <= wa0;`
271			`i <= i0;`
272			`end`
273			`else if (clk & wclk2) begin`
274			`wr <= wr1x;`
275			`we <= we1x;`
276			`wa <= wa1x;`
277			`i <= i1x;`
278			`end`
279			`else begin`
280			`wr <= 1'b0;`
281			`we <= 8'h00;`
282			`wa <= 'd0;`
283			`i <= 'd0;`
284			`end`
285			`end`
286
287			`assign o0 = ra0[4:0]==5'd0 ? {WID{1'b0}} :`
288			`(wr1 && (ra0==wa1)) ? i1 :`
289			`(wr0 && (ra0==wa0)) ? i0 : o00;`
290			`assign o1 = ra1[4:0]==5'd0 ? {WID{1'b0}} :`
291			`(wr1 && (ra1==wa1)) ? i1 :`
292			`(wr0 && (ra1==wa0)) ? i0 : o01;`
293			`assign o2 = ra2[4:0]==5'd0 ? {WID{1'b0}} :`
294			`(wr1 && (ra2==wa1)) ? i1 :`
295			`(wr0 && (ra2==wa0)) ? i0 : o02;`
296			`assign o3 = ra3[4:0]==5'd0 ? {WID{1'b0}} :`
297			`(wr1 && (ra3==wa1)) ? i1 :`
298			`(wr0 && (ra3==wa0)) ? i0 : o03;`
299			`assign o4 = ra4[4:0]==5'd0 ? {WID{1'b0}} :`
300			`(wr1 && (ra4==wa1)) ? i1 :`
301			`(wr0 && (ra4==wa0)) ? i0 : o04;`
302			`assign o5 = ra5[4:0]==5'd0 ? {WID{1'b0}} :`
303			`(wr1 && (ra5==wa1)) ? i1 :`
304			`(wr0 && (ra5==wa0)) ? i0 : o05;`
305
306			`endmodule`
307